WO2021142830A1

WO2021142830A1 - Random number generation circuit, random number generation method, and electronic device

Info

Publication number: WO2021142830A1
Application number: PCT/CN2020/072982
Authority: WO
Inventors: 魏祥野; 修黎明; 白一鸣
Original assignee: 京东方科技集团股份有限公司; 北京京东方技术开发有限公司
Priority date: 2020-01-19
Filing date: 2020-01-19
Publication date: 2021-07-22
Also published as: CN113498506A; CN113498506B

Abstract

Provided are a random number generation circuit and method, and an electronic device. The random number generation circuit comprises: a pulse generation sub-circuit, configured to generate a plurality of pulses, wherein the frequency of the pulses varies with a change in environmental parameters; a frequency-locked loop circuit, wherein the frequency-locked loop circuit comprises a frequency-discrimination and phase-discrimination sub-circuit, configured to generate a phase relationship indicator signal and a frequency relationship indicator signal according to a phase relationship between an input signal and a feedback signal, the phase relationship indicator signal indicates whether the phase of the input signal is ahead of the phase of the feedback signal, and the frequency relationship indicator signal indicates a frequency magnitude relationship between the input signal and the feedback signal; a feedback sub-circuit, configured to generate the feedback signal according to the frequency relationship indicator signal and the frequency of the pulses; a seed generation sub-circuit, configured to generate a random number seed according to the phase relationship indicator signal; and a random number generation sub-circuit, configured to generate a random number sequence according to the random number seed.

Description

Random number generating circuit, random number generating method and electronic equipment

Technical field

The present disclosure relates to the field of display technology, and in particular to a random number generation circuit, a random number generation method, and electronic equipment.

Background technique

Communication is one of the cornerstones of the Internet of everything. With the development of the times, communication will play an important role in future electronic systems. However, the Internet of everything also brings network security issues. Therefore, highly secure network encryption is indispensable. The current encryption method mainly relies on the True Random Number Generator (TRNG) in the hardware, which uses random numbers for encryption.

Summary of the invention

The present disclosure aims to solve at least one of the technical problems existing in the prior art, and proposes a random number generation circuit, a random number generation method, and an electronic device.

The present disclosure provides a random number generation circuit, including:

The pulse generating sub-circuit is configured to generate a plurality of pulses, and the frequency of the pulses changes with changes in environmental parameters;

A frequency-locked loop loop, the frequency-locked loop loop comprising: a frequency and phase-discrimination sub-circuit configured to generate a phase relationship indicating signal and a frequency relationship indicating signal according to the phase relationship between the input signal and the feedback signal, the phase relationship indicating signal indicating Whether the phase of the input signal leads the phase of the feedback signal, the frequency relationship indicating signal indicates the frequency relationship between the input signal and the feedback signal; the feedback sub-circuit is configured to indicate according to the frequency relationship The frequency of the signal and the pulse to generate the feedback signal;

A seed generation sub-circuit, configured to generate a random number seed according to the phase relationship indication signal;

The random number generating sub-circuit is configured to generate a random number sequence according to the random number seed.

In some embodiments, the pulse generation sub-circuit includes: a loop oscillator.

In some embodiments, the feedback sub-circuit includes:

A control unit configured to generate a frequency control word according to the frequency relationship indication signal;

The digital control oscillating unit is configured to generate an intermediate signal according to the frequency control word and the frequency of the pulse, the frequency of the intermediate signal is K*f/F, where K is all generated by the pulse generating sub-circuit The number of the pulses, f is the frequency of the pulses, and F is the frequency control word;

The first frequency dividing unit is configured to divide the frequency of the intermediate signal to generate the feedback signal.

In some embodiments, the frequency division coefficient of the first frequency division unit is 1.

In some embodiments, the first frequency dividing unit is further configured to adjust the frequency dividing coefficient of the first frequency dividing unit according to the control parameter.

In some embodiments, the digitally controlled oscillation unit includes: a time average frequency direct period synthesizer.

In some embodiments, the phase relationship indicator signal is a digital signal, and the random number seed is: a binary number obtained by combining multiple values of the phase relationship indicator signal.

In some embodiments, the random number seed is a binary number with n+1 bits, and the random number generation sub-circuit is specifically configured to: shift the random number seed to the right multiple times, each time right Shifting to generate a binary sequence, and the random number sequence is composed of at least one of the binary sequences;

Wherein, the first bit in the first binary sequence is generated by performing a predetermined logical operation on the values of the last two bits of the random number seed, and the other bits in the first binary sequence are generated by the first n bits of the random number seed. The bit position is shifted to the right by one bit; the first bit in the i+1th binary sequence is generated by the last two bits of the i-th binary sequence after a predetermined logical operation, and the other bits in the i+1th binary sequence are generated by the first bit in the i+1th binary sequence. The first n bits of i binary sequences are shifted to the right by one bit, n is an integer greater than 0, and i is an integer greater than 0 and less than the total number of the binary sequences.

In some embodiments, the predetermined logical operation is an exclusive OR operation.

In some embodiments, the random number generating sub-circuit includes: a pseudo-random binary sequence code generator.

In some embodiments, the frequency and phase discrimination sub-circuit includes:

The first input terminal is configured to receive the input signal;

The second input terminal is configured to receive the feedback signal;

The second frequency dividing unit is configured to divide the frequency of the input signal;

A register unit configured to obtain multiple signal values of the output signal of the second frequency dividing unit at multiple edges of the feedback signal;

The first logic unit is configured to perform logic operations on the multiple signal values output by the register unit to output a first digital signal to the first output terminal when the phase of the input signal leads the phase of the feedback signal , Output a second digital signal to the second output terminal; and output the first digital signal to the second output terminal and output to the first output terminal when the phase of the input signal lags the phase of the feedback signal A second digital signal; the phase relationship indication signal is obtained by processing the output signal of the first output terminal and the output signal of the second output terminal according to the first logic rule;

The second logic unit is configured to perform logic operations on the output signals of the first output terminal and the second output terminal to output to the third output terminal when the frequency of the input signal is greater than the frequency of the feedback signal The first digital signal, the second digital signal is output to a fourth output terminal, and the second digital signal is output to the third output terminal when the frequency of the input signal is less than the frequency of the feedback signal, The first digital signal is output to the fourth output terminal; the frequency relationship indication signal is obtained by processing the output signal of the third output terminal and the output signal of the fourth output terminal according to a second logic rule.

In some embodiments, the register unit includes: a first D flip-flop, a second D flip-flop, a third D flip-flop, and a fourth D flip-flop, the input terminal of the first D flip-flop and the first D flip-flop The input ends of the three D flip-flops are all connected to the output end of the second frequency dividing unit, the input end of the second D flip-flop is connected to the output end of the first D flip-flop, and the fourth D trigger is connected to the output end of the first D flip-flop. The input terminal of the device is connected to the output terminal of the third D flip-flop, the clock terminal of the first D flip-flop, the clock terminal of the second D flip-flop and the clock terminal of the fourth D flip-flop are all Connected to the second input terminal, and the clock terminal of the third D flip-flop is connected to the second input terminal through a first NOT gate.

In some embodiments, the first logic unit includes: a first XOR gate and a second XOR gate, and two input terminals of the first XOR gate are respectively connected to the output terminal of the second D flip-flop Is connected to the output terminal of the fourth D flip-flop, the two input terminals of the second XOR gate are respectively connected to the output terminal of the first D flip-flop and the output terminal of the fourth D flip-flop, the The output terminal of the first XOR gate is connected to the first output terminal, and the output terminal of the second XOR gate is connected to the second output terminal;

The second logic unit includes: a second NOT gate, a third NOT gate, a first AND gate, and a second AND gate. Two input terminals of the first AND gate are connected to the first output terminal and the The second output terminal is connected, one of the input terminals of the second AND gate is connected to the first output terminal through the second NOT gate, and the other output terminal of the second AND gate is connected through the third inverter. The gate is connected to the second output terminal.

Correspondingly, an embodiment of the present disclosure also provides a random number generation method, including:

Generating a plurality of pulses, the frequency of the pulses changing with changes in environmental parameters;

A phase relationship indicator signal and a frequency relationship indicator signal are generated according to the phase relationship between the input signal and the feedback signal, the phase relationship indicator signal indicates whether the phase of the input signal is ahead of the phase of the feedback signal, and the frequency relationship indicator signal indicates The frequency relationship between the input signal and the feedback signal; the feedback signal is generated according to the frequency relationship indicator signal and the frequency of the pulse;

Generating a random number seed according to the phase relationship indication signal;

A random number sequence is generated according to the random number seed.

In some embodiments, the feedback signal is generated according to the following steps:

Generating a frequency control word according to the frequency relationship indication signal;

Generate an intermediate signal according to the frequency control word and the frequency of the pulse. The frequency of the intermediate signal is K*f/F, where K is the number of pulses generated by the pulse generation sub-circuit, and f is The frequency of the pulse, F is the frequency control word;

The intermediate signal is frequency-divided to generate the feedback signal.

In some embodiments, in the step of frequency division of the intermediate signal, the frequency division coefficient is 1.

In some embodiments, the step of dividing the frequency of the intermediate signal includes: adjusting a frequency dividing coefficient according to a control parameter, and dividing the frequency of the intermediate signal by using the adjusted frequency dividing coefficient.

In some embodiments, the random number seed is a binary number with n+1 bits,

The step of generating a random number sequence according to the random number seed includes:

The random number seed is shifted right multiple times, and each right shift generates a binary sequence, and the random number sequence is composed of at least one binary sequence; wherein, the first bit in the first binary sequence is The value of the last two bits of the random number seed is generated after a predetermined logical operation. The other bits in the first binary sequence are generated by shifting the first n bits of the random number seed to the right by one bit; the i+1th binary The first bit in the sequence is generated by performing a predetermined logical operation on the last two bits of the i-th binary sequence, and the other bits in the i+1-th binary sequence are generated by shifting the first n bits of the i-th binary sequence to the right by one bit. n is an integer greater than 0, and i is an integer greater than 0 and less than the total number of the binary sequence.

Correspondingly, an embodiment of the present disclosure also provides an electronic device including the above-mentioned random number generation circuit.

Description of the drawings

The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure, but do not constitute a limitation to the present disclosure. In the attached picture:

Fig. 1 shows a schematic block diagram of a random number generating circuit according to some embodiments of the present disclosure.

FIG. 2 shows a circuit diagram of a ring oscillator according to some embodiments of the present disclosure.

Fig. 3 shows a schematic diagram of a frequency and phase discrimination sub-circuit according to some embodiments of the present disclosure.

Fig. 4 shows a schematic diagram of the waveforms of the input signal and the feedback signal of the input phase discrimination sub-circuit according to some embodiments of the present disclosure.

FIG. 5 shows a circuit diagram of a time average frequency direct period synthesizer according to some embodiments of the present disclosure.

FIG. 6 shows a schematic diagram of the principle of time average frequency according to some embodiments of the present disclosure.

FIG. 7 shows a schematic diagram of a random number generation sub-circuit according to some embodiments of the present disclosure.

FIG. 8 shows a schematic diagram of the imaging effect of a random number sequence generated by a random number generating circuit according to some embodiments of the present disclosure.

FIG. 9 shows a schematic diagram of a random number generation method according to some embodiments of the present disclosure.

FIG. 10 shows a schematic diagram of generating a feedback signal according to some embodiments of the present disclosure.

Detailed ways

In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative labor are within the protection scope of the present disclosure.

The terms used here to describe the embodiments of the present disclosure are not intended to limit and/or define the scope of the present disclosure. For example, unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the usual meanings understood by those with ordinary skills in the field to which the present disclosure belongs. It should be understood that the "first", "second" and similar words used in the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Unless the context clearly dictates otherwise, the singular form "a", "an" or "the" and other similar words do not mean a quantitative limitation, but instead mean that there is at least one.

It will be further understood that the terms "including" or "including" and other similar words mean that the elements or items appearing before the word cover the elements or items listed after the word and their equivalents, but do not exclude other elements or items . Similar words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "Down", "Left", "Right", etc. are only used to indicate the relative position relationship. When the absolute position of the described object changes, the relative position relationship may also change accordingly.

In the first aspect, embodiments of the present disclosure provide a random number generation circuit. FIG. 1 shows a schematic block diagram of a random number generation circuit according to some embodiments of the present disclosure. As shown in FIG. 1, the random number generation circuit includes: The pulse generation sub-circuit 10, the frequency-locked loop loop, the seed generation sub-circuit 40, and the random number generation sub-circuit 50.

The pulse generating sub-circuit 10 is configured to generate a plurality of pulses, and the frequency of the pulses generated by the pulse generating sub-circuit 10 changes with changes in environmental parameters. For example, the pulse generation sub-circuit 10 is an oscillator, and its oscillation frequency drifts with changes in environmental parameters (such as temperature).

The frequency-locked loop loop is a time average frequency-locked loop (TAF-FLL) loop, which is configured to lock the frequency of the input signal and the frequency of the feedback signal. The frequency-locked loop loop includes: a frequency and phase discrimination sub-circuit 20 and a feedback sub-circuit 30. The frequency and phase discrimination sub-circuit 20 is configured to generate a phase relationship indicator signal and a frequency relationship indicator signal according to the phase relationship between the input signal (whose frequency is fi) and the feedback signal (whose frequency is fb), and the phase relationship indicator signal indicates the phase relationship of the input signal. Whether the phase is ahead of the phase of the feedback signal fb, the frequency relationship indicator signal indicates the magnitude relationship between the frequency fi of the input signal and the frequency fb of the feedback signal. The feedback sub-circuit 30 is configured to generate the feedback signal fb according to the frequency relationship indicator signal and the frequency of the pulse.

In the embodiments of the present disclosure, the input signal may be generated by an external crystal oscillator (Crystal), or by a Micro-Electro-Mechanical System (MEMS), or by an oscillator (for example, a ring oscillator (Ring Oscillator)). , RO)) produced.

In the embodiment of the present disclosure, the input signal fi input to the phase-locked loop loop is easily jittered under the interference of thermal noise. At the same time, the frequency of the pulse generated by the pulse generating sub-circuit 10 will also drift with the change of environmental parameters, regardless of How the input signal jitters and how the pulse frequency drifts, the feedback sub-circuit 30 will make the frequency fb of the feedback signal consistent with the frequency fi of the input signal according to the relationship between the frequency of the input signal and the feedback signal. Due to the jitter of the input signal and the drift of the pulse frequency, the phase of the input signal and the feedback signal received by the phase discrimination sub-circuit 20 will be highly uncertain. Therefore, the phase relationship indicator signal generated according to the phase relationship has a high degree of uncertainty. The high uncertainty improves the randomness of the random number seed generated according to the phase relationship indicator signal, which in turn increases the randomness of the generated random number, and realizes the generation of a true random number.

In some embodiments, the pulse generation sub-circuit 10 includes a ring oscillator 11, for example, an oscillator based on cross-cascaded NAND gates (CROSS NAND GATEs). Fig. 2 shows a circuit diagram of a ring oscillator according to some embodiments of the present disclosure. As shown in Fig. 2, the ring oscillator 11 includes 8-stage NAND units (P0～P15) in cross-cascade connection. The level includes a pair of NAND gates. The ring oscillator 11 generates a plurality of evenly spaced pulses in phase. The biggest characteristic of the ring oscillator 11 is that it is unstable. The initial condition of its oscillation is random, and its oscillation frequency is very sensitive to the environment. When the temperature changes slightly, the oscillation frequency will drift.

In some embodiments, the frequency discrimination sub-circuit 20 adopts a phase frequency detector (Phase Frequency Detector, PFD). FIG. 3 shows a schematic diagram of the phase discrimination sub-circuit according to some embodiments of the present disclosure, such as As shown in FIG. 3, the frequency and phase discrimination sub-circuit 20 includes: a first input terminal, a second input terminal, a first output terminal out1, a second output terminal out2, a third output terminal out3, a fourth output terminal out4, and a second output terminal out2. The frequency dividing unit 21, the register unit 22, the first logic unit 23, and the second logic unit 24. The first input terminal is configured to receive an input signal with a frequency fi. The second input terminal is configured to receive a feedback signal with a frequency of fb. The second frequency dividing unit 21 is configured to divide the frequency of the input signal. For example, the second frequency dividing unit 21 adopts a two frequency divider.

The register unit 22 is configured to obtain multiple signal values of the output signal of the second frequency dividing unit 21 at multiple edges of the feedback signal. For example, the signal value of the second frequency dividing unit 21 at the two adjacent rising edges of the feedback signal and the falling edge between the two rising edges is obtained.

For example, the register unit 22 includes: a first D flip-flop 221, a second D flip-flop 222, a third D flip-flop 223, and a fourth D flip-flop 224, the input terminal of the first D flip-flop 221 and the third D flip-flop The input terminals of 223 are all connected to the output terminal of the second frequency dividing unit 21, the input terminal of the second D flip-flop 222 is connected to the output terminal of the first D flip-flop 221, and the input terminal of the fourth D flip-flop 224 is connected to the third The output terminal of the D flip-flop 223 is connected, the clock terminal of the first D flip-flop 221, the clock terminal of the second D flip-flop 222 and the clock terminal of the fourth D flip-flop 224 are all connected to the second input terminal, and the third D flip-flop The clock terminal of the converter 223 is connected to the second input terminal through the first NOT gate 25.

The first logic unit 23 is connected to the first output terminal out1 and the second output terminal out2. The first logic unit 23 is configured to perform logic operations on multiple signal values output by the register unit 22, so that the phase of the input signal leads the feedback signal The first digital signal is output to the first output terminal out1 and the second digital signal is output to the second output terminal out2; and the first digital signal is output to the second output terminal out2 when the phase of the input signal lags the phase of the feedback signal. Signal, output a second digital signal to the first output terminal out1. The phase relationship indication signal is obtained by processing the output signal of the first output terminal out1 and the output signal of the second output terminal out2 according to the first logic rule.

For example, the first logic rule is: when the first output terminal out1 outputs the first digital signal and the second output terminal out2 outputs the second digital signal, the phase relationship indicator signal is set to the first digital signal; when the first output terminal out1 When the second digital signal is output and the second output terminal out2 outputs the first digital signal, the phase relationship indicating signal is set to the second digital signal; wherein, when the phase relationship indicating signal is the first digital signal, the phase of the indicating input signal is ahead of The phase of the feedback signal; when the phase relationship indicator signal is the second digital signal, the phase of the indicator input signal lags the phase of the feedback signal. For example, the value of the first digital signal is 1 and the value of the second digital signal is 0. When the value of the output signal of the first output terminal out1 is 1, and the value of the output signal of the second output terminal out2 is 0, the phase relationship The value of the indicating signal is 1; when the value of the output signal of the first output terminal out1 is 0 and the value of the output signal of the second output terminal out2 is 1, the value of the phase relationship indicating signal is 0; when the first output terminal out1 When the values of the output signal of and the output signal of the second output terminal out2 are both 1 or both are 0, they are discarded. When the value of the phase relationship indicator signal is 1, it indicates that the phase of the input signal is ahead of the phase of the feedback signal; when the value of the phase relationship indicator signal is 0, it indicates that the phase of the input signal lags the phase of the feedback signal.

The second logic unit 24 is connected to the third output terminal out3 and the fourth output terminal out4. The second logic unit 24 is configured to perform logic operations on the output signals of the first output terminal out1 and the second output terminal out2 to determine the difference between the input signals When the frequency is greater than the frequency of the feedback signal, the first digital signal is output to the third output terminal out3, and the second digital signal is output to the fourth output terminal out4. When the frequency fi of the input signal is less than the frequency fb of the feedback signal, the third output terminal out3 is output. The second digital signal is output, and the first digital signal is output to the fourth output terminal out4. The frequency relationship indication signal is obtained by processing the output signal of the third output terminal out3 and the output signal of the fourth output terminal out4 according to the second logic rule.

For example, the second logic rule is: when the third output terminal out3 outputs the first digital signal and the fourth output terminal out4 outputs the second digital signal, the frequency relationship indicator signal is set to the first digital signal; when the third output terminal out3 When the second digital signal is output and the fourth output terminal out4 outputs the first digital signal, the frequency indicating signal is set to the second digital signal; wherein, when the frequency relationship indicating signal is the first digital signal, the frequency of the indicating input signal is greater than the feedback signal When the frequency relationship indicator signal is the second digital signal, it indicates that the frequency of the input signal is less than the frequency of the feedback signal. For example, when the value of the first digital signal is 1, and the value of the second digital signal is 0, when the value of the output signal of the third output terminal out3 is 1, and the value of the output signal of the fourth output terminal out4 is 0, the frequency relationship The value of the indicating signal is 1; when the value of the output signal of the third output terminal out3 is 0 and the value of the output signal of the fourth output terminal out4 is 1, the value of the frequency relationship indicating signal is 0; when the third output terminal out3 When the values of the output signal of and the output signal of the fourth output terminal out4 are both 0 or both, they are discarded. When the value of the frequency relationship indicator signal is 1, it indicates that the frequency fi of the input signal is greater than the frequency fb of the feedback signal; when the value of the frequency relationship indicator signal is 0, it indicates that the frequency fi of the input signal is less than the frequency fb of the feedback signal.

In some embodiments, as shown in FIG. 3, the register unit 22 includes: a first D flip-flop 221, a second D flip-flop 222, a third D flip-flop 223, and a fourth D flip-flop 224, the first D flip-flop The input terminal of 221 and the input terminal of the third D flip-flop 223 are both connected to the output terminal of the second frequency dividing unit 21, the input terminal of the second D flip-flop 222 is connected to the output terminal of the first D flip-flop 221, and the fourth The input terminal of the D flip-flop 224 is connected to the output terminal of the third D flip-flop 223, the clock terminal of the first D flip-flop 221, the clock terminal of the second D flip-flop 222, and the clock terminal of the fourth D flip-flop 224 are all connected to The second input terminal is connected, and the clock terminal of the third D flip-flop 223 is connected to the second input terminal through the first NOT gate 25.

The first logic unit 23 includes: a first XOR gate 231 and a second XOR gate 232, the two input terminals of the first XOR gate 231 are respectively connected to the output terminal of the second D flip-flop 222 and the fourth D flip-flop 224 The two input terminals of the second XOR gate 232 are connected to the output terminal of the first D flip-flop 221 and the output terminal of the fourth D flip-flop 224 respectively. The output terminal of the first XOR gate 231 is connected to the output terminal of the fourth D flip-flop 224, respectively. An output terminal out1 is connected, and the output terminal of the second XOR gate 232 is connected to the second output terminal out2. The second logic unit 24 includes: a second inverter gate 241, a third inverter gate 242, a first AND gate 243, and a second AND gate 244. The two input terminals of the first AND gate 243 are connected to the first output terminal out1 and the first output terminal, respectively. The two output terminals out2 are connected, one of the input terminals of the second AND gate 244 is connected to the first output terminal out1 through the second NOT gate 241, and the other output terminal of the second AND gate 244 is connected to the second output terminal through the third NOT gate 242 End connected.

Fig. 4 shows a schematic diagram of the input signal and the feedback signal of the input phase discrimination sub-circuit according to some embodiments of the present disclosure. As shown in Fig. 4, the solid line in the upper part represents the ideal input signal waveform, and the lower part The solid line in the middle represents the ideal feedback signal waveform. Both the input signal and the feedback signal will jitter due to their own noise. The dashed line represents the boundary of the pulse edge when the input signal/feedback signal is disturbed by noise. The pulse edge is anywhere within the dashed line. The probability of occurrence is the same. When the frequency and phase discrimination sub-circuit 20 determines the phase relationship between the input signal and the output signal, uncertainty will occur. For example, it may happen that the phase of the input signal leads the phase of the feedback signal, it may also happen that the phase of the input signal lags behind the phase of the feedback signal, or it may happen that the input signal and the feedback phase coincide. Moreover, in the frequency discrimination sub-circuit 20 shown in FIG. 3, the feedback signal (or its inverted signal) is used as the clock signal of the first D flip-flop 221 to the fourth D flip-flop 224, and the frequency discrimination The input signal in the phase sub-circuit 20 is used as the input signal of the first D flip-flop 221 and the third D flip-flop 223. When the phases of the input signal of the D flip-flop and the clock signal are very close, the D flip-flop is in a metastable state. State, it is possible to

output

0 or 1, thereby increasing the uncertainty of the phase relationship indicator signal generated by the frequency and phase discrimination sub-circuit 20, thereby increasing the randomness of the random number generated according to the phase relationship indicator signal.

In some embodiments, the feedback sub-circuit 30 includes: a control unit 31, a digitally controlled oscillation unit 32 and a first frequency dividing unit 33.

The control unit 31 is configured to generate the frequency control word F according to the frequency relationship indication signal output by the frequency discrimination sub-circuit 20. For example, the control unit 31 reads the initial frequency control word F from the storage device. When the frequency relationship indication signal indicates that the frequency fi of the input signal is greater than the frequency fb of the feedback signal, the control unit 31 reduces the current frequency control word by 1. ; When the frequency relationship indication signal indicates that the frequency of the input signal fi is less than the frequency of the feedback signal fb, the control unit 31 increases the current frequency control word by 1.

The digital control oscillating unit 32 is configured to generate an intermediate signal according to the frequency control word and the frequency of the pulse generated by the pulse generating sub-circuit 10, the frequency of the intermediate signal fo=K*f/F, where K is generated by the pulse generating sub-circuit 10 The number of pulses, f is the frequency of the pulses, and F is the frequency control word.

The first frequency dividing unit 33 is configured to divide the frequency of the intermediate signal to generate the aforementioned feedback signal.

In some embodiments, the digitally controlled oscillation unit 32 adopts a time average frequency direct period synthesis (TAF-DPS) circuit architecture based on a time average frequency direct period synthesis (TAF-DPS) circuit architecture. FIG. 5 shows a circuit diagram of a time average frequency direct period synthesizer according to some embodiments of the present disclosure. As shown in FIG. 5, the time average frequency direct period synthesizer 320 may include a first input module, a second input module 3230, and Output module 3240.

For example, as shown in FIG. 5, the first input module includes a first logic control circuit 3210 and a second logic control circuit 3220. The first logic control circuit 3210 includes a first adder 3211, a first register 3212, and a second register 3213. The second logic control circuit 3220 may include a second adder 3221, a third register 3222, and a fourth register 3223.

The second input module 3230 includes a first K→1 multiplexer 3231, a second K→1 multiplexer 3232, and a 2→1 multiplexer 3233. The first K→1 multiplexer 3231 and the second K→1 multiplexer 3232 each include a plurality of input terminals, a control input terminal, and an output terminal. The multiple input ends of the first K→1 multiplexer 3231 and the second K→1 multiplexer 3232 are respectively used to receive K (K is an integer greater than 1) output by the pulse generation sub-circuit. The phases are uniform Interval pulses. The 2→1 multiplexer 3233 includes a control input terminal, an output terminal, a first input terminal for receiving the output of the first K→1 multiplexer 3231, and a second K→1 multiplexer for receiving the output. The second input terminal of the output of the user 3232. For example, the time span (for example, the phase difference) between any two adjacent pulses among the K pulses with uniformly spaced phases may be the reference time unit Δ.

For example, as shown in FIG. 5, the output module 3240 includes a trigger circuit. The trigger circuit is used to generate pulse trains. The trigger circuit includes a D flip-flop 3241, a first inverter 3242, and a second inverter 3243. The D flip-flop 3241 includes a data input terminal, a clock input terminal for receiving the output from the output terminal of the 2→1 multiplexer 3233, and an output terminal for outputting the first clock signal CLK1. The first inverter 3242 includes an input terminal for receiving the first clock signal CLK1 and an output terminal for outputting a signal to the data input terminal of the D flip-flop 3241. The second inverter 3243 includes an input terminal for receiving the first clock signal CLK1 and an output terminal for outputting the second clock signal CLK2.

The first clock signal CLK1 is output to the control input terminal of the 2→1 multiplexer 3233, and the output terminal of the first inverter 3242 is connected to the data input terminal of the D flip-flop 3241.

For example, the first adder 3211 may add the frequency control word F and the most significant bits (for example, 5 bits) stored in the first register 3212, and then add them at the rising edge of the second clock signal CLK2 The result is saved in the first register 3212; alternatively, the first adder 3211 may add the frequency control word F and all the information stored in the first register 3212, and then save the addition result at the rising edge of the second clock signal CLK2 To the first register 3212. At the next rising edge of the second clock signal CLK2, the most significant bit stored in the first register 3212 will be stored in the second register 3213 and used as the selection signal of the first K→1 multiplexer 3231 for One pulse is selected from the K pulses as the output signal of the first K→1 multiplexer 3231.

For example, the second adder 3221 may add the frequency control word F/2 and the most significant bit stored in the first register 3212, and then save the addition result in the third register 3222 at the rising edge of the second clock signal CLK2 . At the next rising edge of the first clock signal CLK1, the information stored in the third register 3222 will be stored in the fourth register 3223 and used as the selection signal of the second K→1 multiplexer 3223 for slave K One of these pulses is selected as the output signal of the second K→1 multiplexer 3223.

The 2→1 multiplexer 3233 can select the output signal from the first K→1 multiplexer 3231 and the second K→1 multiplexer 3232 at the rising edge of the first clock signal CLK1 One of the output signals is used as the output signal of the 2→1 multiplexer 3233 and used as the input clock signal of the D flip-flop 3241.

For example, one of the output terminal of the D flip-flop 3241 and the output terminal of the second inverter 3243 can be used as the output of the time average frequency direct periodic synthesizer 320.

For example, the selection signal output by the second register 3213 can be used to select the falling edge of the synthesized clock signal generated by the time average frequency direct cycle synthesizer 320, and the selection signal output by the fourth register 3223 can be used to select the time average frequency direct cycle. The rising edge of the synthesized clock signal generated by the synthesizer 320, and the signal fed back to the first adder 3211 by the first register 3212 can be used to control the period switching of the synthesized clock generated by the time average frequency direct cycle synthesizer 320.

The time average frequency direct period synthesizer 320 generates the intermediate signal based on the time average frequency (TAF). FIG. 6 shows a schematic diagram of the principle of the time average frequency according to some embodiments of the present disclosure. In conjunction with FIG. 5 and FIG. 6, the output time period of the average frequency synthesizer 320 directly, there are two, two kinds of output signal are periodic first period and the second period T _A T _B. 6, a reference time unit for the frequency control word and Δ F = I + r, can obtain two time periods: a first period and a second period T _A T _B. The first period and the second period T _A T _B can be represented by the following formula (1) and formula (2). Among them, I is the integer part of the frequency control word F, and r is the decimal part of the frequency control word F.

T _A ＝I·Δ (1)

T _B ＝(I+1)·Δ (2)

Using the first period and the second period T _A T _B, can be generated by a staggered manner comprises two different periods (different frequencies) of the clock signal. The average period of the generated clock signal is T _TAF , and the average frequency f _{TAF is} as shown in the following formula (3).

Among them, f is the frequency of the pulse, and K is the number of pulses generated by the pulse generating sub-circuit 10. The characteristic of the time average frequency direct period synthesizer 320 is: changing the frequency control word F, the frequency f _{TAF of} the generated clock signal can complete the frequency switching after two cycles.

The time average frequency direct period synthesizer 320 is based on the working mode of TAF, so that the frequency of the output signal changes between the two frequencies. Therefore, the phase of the intermediate signal changes. This phase change makes the frequency discrimination sub-circuit 20 The randomness of the output signal is improved, thereby further improving the randomness of generating random numbers.

In some embodiments, the first frequency dividing unit 33 adopts a frequency divider.

In order to transmit all the noise of the pulse generation sub-circuit 10 to the frequency and phase discrimination sub-circuit 20, in some embodiments, the frequency division coefficient of the first frequency division unit 33 is set to a small value, for example, the frequency division coefficient N = 1.

In some embodiments, in order to increase the randomness of the output signal of the frequency discrimination sub-circuit 20, the first frequency division unit 33 is configured as a dither circuit. For example, the first frequency division unit 33 is further configured to adjust the first frequency division unit 33 according to the control parameter. A frequency division coefficient of the frequency division unit 33.

For example, the control parameter is generated by a parameter generation circuit, which may be the same circuit as the random number generation sub-circuit 50, and the value of each random number in the random number sequence generated by the random number generation sub-circuit 50 is used as the control parameter. For example, when the random number generating sub-circuit 50 outputs 0, the frequency division coefficient of the first frequency dividing unit 33 is adjusted to 2; when the random number generating sub-circuit 50 outputs 1, the frequency dividing coefficient of the first frequency dividing unit 33 is adjusted to 1. For another example, when the random number generating sub-circuit 50 continuously outputs 0 and 0, the frequency division coefficient of the first frequency dividing unit 33 is adjusted to 2. When the random number generating sub-circuit 50 continuously outputs 0, 1, the first frequency dividing unit 33 When the frequency division coefficient of the first frequency division unit 33 is adjusted to 3 when the random number generation sub-circuit 50 continuously outputs 1 and 0, the frequency division coefficient of the first frequency division unit 33 is adjusted to 3. Of course, the parameter generation circuit may also be a circuit other than the random number generation sub-circuit 50.

In some embodiments, the phase relationship indicator signal is a digital signal, and the random number seed is a binary number obtained by combining values of a plurality of phase relationship indicator signals. It should be noted that in the embodiments of the present disclosure, a certain signal being 0 means that the value of the signal is 0, and a certain signal being 1 means that the value of the signal is 1.

For example, the value of the phase relationship indicator signal is 0 or 1. When the value of the phase relationship indicator signal is 0, it indicates that the phase of the input signal lags behind the phase of the feedback signal. When the value of the phase relationship indicator signal is 1, it indicates the input signal. The phase of is ahead of the phase of the feedback signal.

For example, within a predetermined period of time, the frequency and phase discrimination sub-circuit 20 performs m (for example, m=10) phase comparisons to generate m phase relationship indicator signals, and the values of the m phase relationship indicator signals are 0, 1, respectively. 1, 0, 0, 1, 1, 1, 1, 0, then the digital signal sequence composed of the values of m phase relationship indicator signals constitutes a random number seed, that is, 0110011110. It should be understood that m=10 is only an exemplary illustration. In practical applications, m can take a larger value to generate a random number seed with more digits, for example, 64, 128, 256, etc. Therefore, the complexity of the random number generated by the random number generating sub-circuit 50 is increased.

In some embodiments, the random number seed is a binary number, which has n+1 bits, and the random number generation sub-circuit 50 is specifically configured to: perform multiple right shifts on the random number seed, and each right shift generates one A binary sequence, the random number sequence is composed of at least one binary sequence. Among them, the first bit in the first binary sequence is generated by performing a predetermined logical operation on the values of the last two bits of the random number seed, and the other bits in the first binary sequence are generated by the first n bits of the random number seed. Generated by shifting one bit to the right; the first bit in the i+1th binary sequence is generated by the last two digits of the i-th binary sequence after a predetermined logical operation, and the other bits in the i+1th binary sequence are generated by the i-th The first n bits of the binary sequence are generated by shifting one bit to the right, n is an integer greater than 0, and i is an integer greater than 0 and less than the total number of the binary sequence. It should be noted that the first bit in the binary sequence is the highest bit in the binary sequence, and the last two bits of the random number seed are the lowest bit and its adjacent bits among the multiple bits of the random number seed.

For example, the random number generating sub-circuit 50 includes a pseudo-random binary sequence code generator. FIG. 7 shows a schematic diagram of a random number generating sub-circuit according to some embodiments of the present disclosure. As shown in FIG. 7, the random number generating sub-circuit 51 includes: a logic operation unit 512, a shift register, and a plurality of data selectors 513 , The number of bits of the random number seed SG is n+1, and the shift register includes n+1 stage D flip-flops 514, the input terminals of n+1 stage D flip-flops 514 and n+1 data selectors 513 The output terminals o1 are connected in one-to-one correspondence. Specifically, the input terminal of the first level D flip-flop 514 is connected to the output terminal o1 of the first data selector 513, and the input terminal 514 of the second level D flip-flop is connected to the second data selection The output terminal o1 of the device 513, and so on, until the input terminal of the n+1-th stage D flip-flop 514 is connected to the output terminal o1 of the n+1-th data selector 513. The first input terminal i1 of the first data selector 513 is connected to the output terminal of the logic operation unit 512, and the first input terminal i1 of the jth data selector 513 is connected to the output terminal of the j-1th stage D flip-flop 514, where , J is an integer, and 1<j≤n+1. The n+1 bit values of the random number seed SG are respectively input to the second input terminal i2 of the n+1 data selectors 512, and the two input terminals of the logical operation unit 512 are respectively connected to the D flip-flops 514 of the latter two stages. The output terminal. When the random number generation sub-circuit 51 is triggered to generate a random number, the second input terminal i2 and the output terminal o1 of each data selector 513 are controlled to be turned on, so that n+1 bits of data of the random number seed SG are input to n+1 respectively The input terminal of the stage D flip-flop 514 is then controlled to conduct the first input terminal i1 and the output terminal o1 of each data selector 513. Each bit in the binary sequence output by the n+1 level D flip-flop 514 is denoted as prbs[0], prbs[1]...prbs[n], prbs[n-1] and prbs[n] are input to Two input terminals of the logic operation unit 512.

For example, a plurality of binary sequences generated by the random number generation sub-circuit 51 after multiple right shifts are arranged in sequence to form the random number sequence, and the first bit prbs[0] in the first binary sequence is used as the first random number sequence. Bit, the last bit of the last binary sequence prbs[n] is used as the last bit of the random number sequence.

For example, the random number seed is 01100010, the binary sequence generated by the random number generation sub-circuit 51 after the first right shift operation is: 10110001; the binary sequence generated by the second right shift operation is: 11011000; the third right shift is performed The binary sequence generated by the shift operation is: 01101100; the binary sequence generated by the fourth right shift operation is: 00110110, and so on. The random number sequence is composed of four binary sequences arranged in the order of generation, that is, the random number sequence is 10110001110110000110110000110110.

FIG. 8 shows a schematic diagram of the imaging effect of a random number sequence generated by a random number generating circuit according to some embodiments of the present disclosure, wherein the random number sequence generated by the random number generating circuit includes 65536-bit random numbers, each of which is randomly The number is 0 or 1. The image size of Figure 8 is 256*256, including 65536 pixels in total. Each pixel corresponds to a random number. The gray scale of each pixel is determined by the value of the corresponding random number. The random number is When 0, the pixel is black, when the random number is 1, the pixel is white. It can be seen from Figure 8 that the random number distribution of the random number sequence meets the requirements of white noise, and there is no obvious pattern.

Most random number generators in the prior art include analog circuits, which have a long production cycle and high cost. In the embodiments of the present disclosure, each part of the random number generator circuit is a digital circuit, which has low power consumption, low power consumption, and high cost. The low-cost feature is beneficial to be integrated in various chips, and the random number generated by the random generation circuit is relatively high, which can provide higher security and reliability in the communication process.

In the second aspect, the present disclosure also provides a random number generation method. FIG. 9 shows a schematic diagram of a random number generation method according to some embodiments of the present disclosure. The random number generation method can be executed by the above-mentioned random number generation circuit. As shown in FIG. 9, the random number generation method in the embodiment of the present disclosure includes the following steps S10 to S40.

Step S10, multiple pulses are generated, and the frequency of the pulses changes with changes in environmental parameters.

Step S20: Generate a phase relationship indicator signal and a frequency relationship indicator signal according to the phase relationship between the input signal and the feedback signal, the phase relationship indicator signal indicates whether the phase of the input signal is ahead of the phase of the feedback signal, and the frequency relationship indicator signal indicates the input signal and the feedback signal The frequency of the relationship. The feedback signal is generated based on the frequency relationship indicator signal and the frequency of the pulse.

For example, the phase relationship indication signal is obtained by processing the output signal of the first output terminal out1 and the output signal of the second output terminal out2 of the frequency discrimination sub-circuit 20 in FIG. 3 according to the first logic rule. The output signal of the first output terminal out1, the output signal of the second output terminal out2, and the phase relationship indicator signal are all digital signals. For example, the value of the first digital signal is 1, and the value of the second digital signal is 0. The first rule is: when the value of the output signal of the first output terminal out1 is 1, the value of the output signal of the second output terminal out2 is When 0, the value of the phase relationship indicating signal is 1; when the value of the output signal of the first output terminal out1 is 0 and the value of the output signal of the second output terminal out2 is 1, the value of the phase relationship indicating signal is 0; When the value of the output signal of the first output terminal out1 and the value of the output signal of the second output terminal out2 are both 1 or 0, they are discarded. When the value of the phase relationship indicator signal is 1, it indicates that the phase of the input signal is ahead of the phase of the feedback signal; when the value of the phase relationship indicator signal is 0, it indicates that the phase of the input signal lags the phase of the feedback signal.

FIG. 10 shows a schematic diagram of generating a feedback signal according to some embodiments of the present disclosure. As shown in FIG. 10, the feedback signal is generated according to the following steps S21 to S23.

Step S21: Generate a frequency control word according to the frequency relationship indication signal.

For example, step S21 is executed by the control unit 31 in FIG. 1. Before step S21, first obtain the initial frequency control word. In step S21, when the frequency relationship indicating signal indicates that the frequency fi of the input signal is greater than the frequency fb of the feedback signal, the control unit 31 reduces the current frequency control word by 1; When the frequency relationship indicator signal indicates that the frequency of the input signal fi is less than the frequency of the feedback signal fb, the current frequency control word is increased by 1.

Step S22: Generate an intermediate signal according to the frequency control word and the frequency of the pulse. The frequency of the intermediate signal is K*f/F, where K is the number of pulses generated by the pulse generating sub-circuit, and f is step S10 The frequency of the pulse generated in, F is the frequency control word.

Step S23: Frequency division is performed on the intermediate signal to generate a feedback signal.

For example, in step S23, the frequency division coefficient for dividing the intermediate signal is 1; for another example, step S23 includes: adjusting the frequency division coefficient according to the control parameter, and dividing the intermediate signal by using the adjusted frequency division coefficient.

Step S30: Generate a random number seed according to the phase relationship indicator signal.

In an embodiment, the phase relationship indicator signal is a digital signal, and the random number seed is: a digital signal sequence formed based on a combination of multiple phase relationship indicator signals. For example, the value of the phase relationship indicator signal is 0 or 1. When the value of the phase relationship indicator signal is 0, it indicates that the phase of the input signal is behind the phase of the feedback signal. When the phase relationship indicator signal is 1, it indicates that the phase of the input signal is ahead of the feedback signal. The phase of the feedback signal.

For example, within a predetermined period of time, the frequency and phase discrimination sub-circuit performs m (for example, m=10) phase comparisons to generate m phase relationship indicator signals, and the values of the m phase relationship indicator signals are 0, 1, and 1, respectively. , 0, 0, 1, 1, 1, 1, 0, the digital signal sequence composed of m phase relationship indicating signals constitutes a random number seed, that is, 0110011110. It should be understood that m=10 is only an exemplary illustration. In practical applications, m can take a larger value to generate a random number seed with more digits, for example, 64-bit, 128-bit, 256-bit, etc. Thereby improving the randomness of the random number generating sub-circuit.

Step S40: Generate a random number sequence according to the random number seed.

For example, the random number seed is a binary number with multiple bits. In some embodiments, step S40 is performed by a pseudo-random binary sequence code generator, and step S40 includes: performing multiple right shifts on the values of multiple bits of the random number seed, and each right shift generates a binary sequence. , The random number sequence is composed of at least one binary sequence; among them, the first bit in the first binary sequence is generated by performing a predetermined logical operation on the value of the last two bits of the random number seed, and the other bits in the first binary sequence The bit is generated by shifting the first n bits of the random number seed to the right by one bit; the first bit in the i+1th binary sequence is generated by the last two bits of the i-th binary sequence after a predetermined logical operation, the i+1th The other bits in a binary sequence are generated by shifting the first n bits of the i-th binary sequence by one bit to the right, where n is an integer greater than 0, and i is an integer greater than 0 and less than the total number of the binary sequence.

In a third aspect, an embodiment of the present disclosure also provides an electronic device, which includes the aforementioned random number generation circuit provided in the embodiment of the present disclosure.

The electronic device in the embodiment of the present disclosure may be a chip in a communication device. All parts of the random number generating circuit provided by the embodiments of the present disclosure adopt digital circuits, so that they can be easily integrated in various chips.

The random number generated by the random number generating circuit in the embodiment of the present disclosure has a high degree of randomness, thereby improving the security and reliability of the electronic device in communication.

It can be understood that the above implementations are merely exemplary implementations used to illustrate the principle of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also deemed to be within the protection scope of the present disclosure.

Claims

A random number generation circuit, including:

The pulse generating sub-circuit is configured to generate a plurality of pulses, and the frequency of the pulses changes with changes in environmental parameters;

A frequency-locked loop loop, the frequency-locked loop loop comprising: a frequency and phase-discrimination sub-circuit configured to generate a phase relationship indicating signal and a frequency relationship indicating signal according to the phase relationship between the input signal and the feedback signal, the phase relationship indicating signal indicating Whether the phase of the input signal leads the phase of the feedback signal, the frequency relationship indicating signal indicates the frequency relationship between the input signal and the feedback signal; the feedback sub-circuit is configured to indicate according to the frequency relationship The frequency of the signal and the pulse to generate the feedback signal;

A seed generation sub-circuit, configured to generate a random number seed according to the phase relationship indication signal;

The random number generating sub-circuit is configured to generate a random number sequence according to the random number seed.
The random number generating circuit according to claim 1, wherein the pulse generating sub-circuit includes: a ring oscillator.
The random number generating circuit according to claim 1, wherein the feedback sub-circuit comprises:

A control unit configured to generate a frequency control word according to the frequency relationship indication signal;

The digital control oscillating unit is configured to generate an intermediate signal according to the frequency control word and the frequency of the pulse, the frequency of the intermediate signal is K*f/F, where K is all generated by the pulse generating sub-circuit The number of the pulses, f is the frequency of the pulses, and F is the frequency control word;

The first frequency dividing unit is configured to divide the frequency of the intermediate signal to generate the feedback signal.
4. The random number generating circuit according to claim 3, wherein the frequency division coefficient of the first frequency division unit is 1.
3. The random number generating circuit according to claim 3, wherein the first frequency dividing unit is further configured to adjust the frequency dividing coefficient of the first frequency dividing unit according to a control parameter.
4. The random number generating circuit according to claim 3, wherein the digitally controlled oscillation unit comprises: a time average frequency direct periodic synthesizer.
4. The random number generating circuit according to claim 1, wherein the phase relationship indicating signal is a digital signal, and the random number seed is a binary number obtained by combining a plurality of values of the phase relationship indicating signal.
The random number generation circuit according to claim 1, wherein the random number seed is a binary number with n+1 bits, and the random number generation sub-circuit is specifically configured to: Multiple right shifts, each right shift generates a binary sequence, and the random number sequence is composed of at least one binary sequence;

Wherein, the first bit in the first binary sequence is generated by performing a predetermined logical operation on the values of the last two bits of the random number seed, and the other bits in the first binary sequence are generated by the first n bits of the random number seed. The bit position is shifted to the right by one bit; the first bit in the i+1th binary sequence is generated by the last two digits of the i-th binary sequence after a predetermined logic operation, and the other bits in the i+1th binary sequence are generated by the i+1th binary sequence. The first n bits of i binary sequences are shifted to the right by one bit, n is an integer greater than 0, and i is an integer greater than 0 and less than the total number of the binary sequences.
The random number generating circuit according to claim 8, wherein the predetermined logical operation is an exclusive OR operation.
8. The random number generating circuit according to claim 8, wherein the random number generating sub-circuit comprises: a pseudo-random binary sequence code generator.
The random number generating circuit according to claim 1, wherein the frequency and phase discrimination sub-circuit comprises:

The first input terminal is configured to receive the input signal;

The second input terminal is configured to receive the feedback signal;

The second frequency dividing unit is configured to divide the frequency of the input signal;

A register unit configured to obtain multiple signal values of the output signal of the second frequency dividing unit at multiple edges of the feedback signal;

The first logic unit is configured to perform logic operations on the multiple signal values output by the register unit to output a first digital signal to the first output terminal when the phase of the input signal leads the phase of the feedback signal , Output a second digital signal to the second output terminal; and output the first digital signal to the second output terminal and output to the first output terminal when the phase of the input signal lags the phase of the feedback signal A second digital signal; the phase relationship indication signal is obtained by processing the output signal of the first output terminal and the output signal of the second output terminal according to the first logic rule;

The second logic unit is configured to perform logic operations on the output signals of the first output terminal and the second output terminal to output to the third output terminal when the frequency of the input signal is greater than the frequency of the feedback signal The first digital signal, the second digital signal is output to a fourth output terminal, and the second digital signal is output to the third output terminal when the frequency of the input signal is less than the frequency of the feedback signal, The first digital signal is output to the fourth output terminal; the frequency relationship indication signal is obtained by processing the output signal of the third output terminal and the output signal of the fourth output terminal according to a second logic rule.
The random number generation circuit according to claim 11, wherein the register unit comprises: a first D flip-flop, a second D flip-flop, a third D flip-flop, and a fourth D flip-flop, the first D flip-flop The input terminal of the device and the input terminal of the third D flip-flop are both connected to the output terminal of the second frequency dividing unit, and the input terminal of the second D flip-flop is connected to the output terminal of the first D flip-flop. Connected, the input terminal of the fourth D flip-flop is connected to the output terminal of the third D flip-flop, the clock terminal of the first D flip-flop, the clock terminal of the second D flip-flop and the first D flip-flop The clock terminals of the four D flip-flops are all connected to the second input terminal, and the clock terminal of the third D flip-flop is connected to the second input terminal through a first NOT gate.
The random number generating circuit according to claim 12, wherein the first logic unit comprises: a first XOR gate and a second XOR gate, and two input terminals of the first XOR gate are respectively connected to the The output terminal of the second D flip-flop is connected to the output terminal of the fourth D flip-flop, and the two input terminals of the second XOR gate are respectively connected to the output terminal of the first D flip-flop and the fourth D flip-flop The output terminal of the XOR gate is connected to the output terminal, the output terminal of the first XOR gate is connected to the first output terminal, and the output terminal of the second XOR gate is connected to the second output terminal;

The second logic unit includes: a second NOT gate, a third NOT gate, a first AND gate, and a second AND gate. Two input terminals of the first AND gate are connected to the first output terminal and the The second output terminal is connected, one of the input terminals of the second AND gate is connected to the first output terminal through the second NOT gate, and the other output terminal of the second AND gate is connected through the third inverter. The gate is connected to the second output terminal.
A random number generation method, including:

Generating a plurality of pulses, the frequency of the pulses changing with changes in environmental parameters;

A phase relationship indicator signal and a frequency relationship indicator signal are generated according to the phase relationship between the input signal and the feedback signal, the phase relationship indicator signal indicates whether the phase of the input signal is ahead of the phase of the feedback signal, and the frequency relationship indicator signal indicates The frequency relationship between the input signal and the feedback signal; the feedback signal is generated according to the frequency relationship indicator signal and the frequency of the pulse;

Generating a random number seed according to the phase relationship indication signal;

A random number sequence is generated according to the random number seed.
The method according to claim 14, wherein the feedback signal is generated according to the following steps:

Generating a frequency control word according to the frequency relationship indication signal;

Generate an intermediate signal according to the frequency control word and the frequency of the pulse. The frequency of the intermediate signal is K*f/F, where K is the number of pulses generated by the pulse generation sub-circuit, and f is The frequency of the pulse, F is the frequency control word;

The intermediate signal is frequency-divided to generate the feedback signal.
The method according to claim 15, wherein in the step of dividing the frequency of the intermediate signal, the frequency dividing coefficient is 1.
The method according to claim 15, wherein the step of dividing the frequency of the intermediate signal comprises: adjusting a frequency dividing coefficient according to a control parameter, and dividing the frequency of the intermediate signal by using the adjusted frequency dividing coefficient.
The method according to claim 14, wherein the phase relationship indicator signal is a digital signal, and the random number seed is: a binary number obtained by combining a plurality of values of the phase relationship indicator signal.
The method according to claim 14, wherein the random number seed is a binary number with n+1 bits,

The step of generating a random number sequence according to the random number seed includes:

The random number seed is shifted right multiple times, and each right shift generates a binary sequence, and the random number sequence is composed of at least one binary sequence; wherein, the first bit in the first binary sequence is The value of the last two bits of the random number seed is generated after a predetermined logical operation. The other bits in the first binary sequence are generated by shifting the first n bits of the random number seed by one bit to the right; the i+1th binary The first bit in the sequence is generated by performing a predetermined logical operation on the last two bits of the i-th binary sequence, and the other bits in the i+1-th binary sequence are generated by shifting the first n bits of the i-th binary sequence to the right by one bit. n is an integer greater than 0, and i is an integer greater than 0 and less than the total number of the binary sequence.
An electronic device comprising the random number generating circuit according to claim 1.