TWI706320B - Real random number generating device and method of field programmable gate array - Google Patents

Abstract

The invention discloses a random number generator of a field programmable gate array, which has a random source group, an environment sensing group, a sampling controller and an entropy harvester. The random source group is used to provide random signals. The environmental sensing group is used to provide environmental signals. The sampling controller is connected to the random source group and the environment sensing group. The entropy harvester is connected to the random source group and the sampling controller, so that the entropy harvester generates random numbers with random signals and environmental signals.

Description

Real random number generating device and method of field programmable gate array

The present invention relates to random number generation, and particularly to a real random number generation device and method of a field programmable gate array.

Random numbers can be used to protect data security, and random number generators can be used to generate random numbers. The random numbers generated by some random number generators cannot be manipulated. These random number generators can be called "true random number generators". The random numbers generated by other random number generators are easy to be expected, and these random number generators can be called "unreal random number generators". Real random number generators are mostly used in application-specific integrated circuits (ASIC). No real random number generator has been effectively used for field programmable gate array (FPGA). The current random number generator of the field programmable gate array uses an unreal random number generator, so that the real random number cannot be generated and the data security cannot be effectively protected.

The random number generator shown in US20110169579A1 uses two random sources. One random source is a high frequency oscillator 71, and the other random source is a low frequency oscillator 72. However, this patent does not generate real random numbers in FPGA implementation.

The random number generator shown in US20150019605A1 uses a phase-locked loop (PLL) as a random source. However, this patent is not related to FPGA Realize the generation of real random numbers.

As shown in WO2014007583A1, a random number generator uses a physical data base path (PDB path) 110 as a random source, and uses a binary counter 140 to delay the signal. However, the random source generation method of this patent is a single form, which requires a compensation circuit to increase its randomness.

The random number generator shown in CN101515228A uses a random source module 1 and a post-processing module 2. Random source module 1 has multiple ring oscillators 31, 32, …, 3N as random sources, and uses an exclusive or 4 to process the signals from these ring oscillators, and uses one The sampler 5 samples the signal from the mutex or gate 4. The signal from sampler 5 is regarded as the original random number. The post-processor module 2 processes the original random numbers. The signal from the post-processor module 2 is regarded as a random number. However, this patent does not generate real random numbers in FPGA implementation.

In view of the above-mentioned problems of the prior art, the purpose of the present invention is to provide a random number generator of a field programmable gate array.

To achieve the above purpose, the random number generator of the field programmable gate array has a random source group, an environment sensing group, a sampling controller and an entropy harvester. The random source group is used to provide random signals. The environmental sensing group is used to provide environmental signals. The sampling controller is connected to the random source group and the environment sensing group. The entropy harvester is connected to the random source group and the sampling controller, so that the entropy harvester generates random numbers with random signals and environmental signals.

10‧‧‧Real random number generator

12‧‧‧Entropy Harvester

14‧‧‧Post processor

16‧‧‧User Interface

18‧‧‧Sampling Controller

20‧‧‧Random source group

22, 24, 26‧‧‧ random source

30‧‧‧Environmental Sensing Group

32‧‧‧Thermometer

34‧‧‧Voltmeter

36、38‧‧‧Multiplexer

40、42‧‧‧Ring oscillator

44‧‧‧Sampler

46、47‧‧‧Inverter

48‧‧‧Configurable signal generator

50‧‧‧Phase lock loop

52, 54‧‧‧ Delay serial circuit

56‧‧‧Sampler

58‧‧‧Configurable controller

59‧‧‧Configurable multiplexer

60‧‧‧Configurable static random access memory array

62、64‧‧‧Analog to Digital Converter

66‧‧‧Temperature sensor

68‧‧‧Voltage Sensor

Figure 1 is a block diagram of the random number generator of the field programmable gate array of the preferred embodiment of the present invention; Figure 2 is the first of the random number generator of the field programmable gate array shown in Figure 1 A block diagram of a random source; Figure 3 is a block diagram of a ring oscillator of the first random source shown in Figure 2; Figure 4 is a random number generation of the field programmable gate array shown in Figure 1 A block diagram of the second random source of the device; Fig. 5 is a block diagram of the third random source of the random number generator of the field programmable gate array shown in Fig. 1; Fig. 6 shows that shown in Fig. 5 The principle of the third random source; Figure 7 is a block diagram of a configurable signal generator, this configurable signal generator can be used for the first random source inverter, the second random source delay and The inverter and delayer of the third random source; and Fig. 8 is a block pattern of an environmental sensing group of the random number generator of the field programmable gate array shown in Fig. 1.

The preferred embodiments of the present invention are further described below with reference to related drawings. In order to facilitate the understanding of the present invention, the same symbols are used to denote the same elements below.

Referring to Figure 1, according to a preferred embodiment of the present invention, a true random number generator 10 includes an entropy harvester 12, a post-processor 14, a user interface 16, a A sampling controller 18, a random source group 20 and an environmental sensing group 30. The random number generator 10 is made as part of a field programmable gate array. Real random number generator 10 can be used for a data storage device or any other suitable device. The real random number generator 10 and such a device constitute a system.

In this embodiment, the random source group 20 includes three random sources 22, 24, and 26. Random sources 22, 24, and 26 are all connected to the entropy harvester 12. Therefore, the random sources 22, 24, and 26 provide random signals to the entropy harvester 12. In other embodiments, the random source group 20 may include other numbers and/or types of random sources. Random sources 22, 24, and 26 are all connected to the entropy harvester 12. Regardless of the number or type, the random source is connected to the entropy harvester 12.

In this embodiment, the environment sensing group 30 includes a thermometer 32 and a voltmeter 34. Both the thermometer 32 and the voltmeter 34 are connected to the sampling controller 18. The thermometer 32 measures the system temperature and provides a signal to the sampling controller 18 accordingly. The voltmeter 34 measures the system voltage and provides a signal to the sampling controller 18 accordingly. The environmental sensing group 30 detects environmental conditions and provides environmental signals accordingly. These environmental signals are converted from analog to digital, and then used to generate random numbers. The random number thus obtained is difficult to accurately predict. In other embodiments, the environmental sensing group 30 may include other numbers and/or other types of environmental sensing meters, such as hygrometers and pressure meters. Regardless of the number or type, the environmental sensor is connected to the sampling controller 18.

The entropy harvester 12 is connected to the post processor 14. The post processor 14 is connected to the user interface 16 and the sampling controller 18. The user interface 16 is connected to the sampling controller 18. The sampling controller 18 is connected to the entropy harvester 12 and the random source group 20.

The entropy harvester 12 directly receives random signals from the random source group 20 and receives environmental signals from the environmental sensing group 30 through the sampling controller 18. The entropy harvester 12 uses random signals and environmental signals to generate random numbers.

The post processor 14 receives the random numbers from the entropy harvester 12 and converts them into the format required by the system. In addition, the post-processor 14 feeds back the sampling controller 18, and this feedback is used to generate unexpected control signals to the random source group 20.

The user interface 16 sends random numbers in the format required by the system to the system. The user interface 16 receives the system signal and feeds it back to the sampling controller 18. This feedback is used to generate unexpected control signals to the random source group 20.

As mentioned above, the environmental sensing group 30 provides environmental signals, which increases the unpredictability of random numbers. The feedback from the post-processor 14 further enhances the unpredictability of random numbers. The feedback from the user interface 16 further enhances the unpredictability of random numbers.

Referring to FIGS. 2 and 3, the random source 22 includes two ring oscillators 40 and 42 and a sampler 44. Both the ring oscillators 40 and 42 are connected to the sampler 44. Both the ring oscillators 40 and 42 are formed by a plurality of inverters 46 connected in series. Each inverter 46 is composed of a number of configurable signal generators 48 (Figure 7). The ring oscillator 40 generates a set of clock signals, and the ring oscillator 42 generates another set of clock signals. The clock signal generated by the ring oscillator 40 is the data of the sampler 44, and the clock signal generated by the ring oscillator 42 is the clock of the sampler 44, and the frequencies of the two are not completely the same. In addition, clock jitter is an unpredictable interference factor. Therefore, the data sampled by the sampler 44 falls into the metastability interval and an unexpected random source is obtained.

Referring to FIG. 4, the random source 24 includes a phase-locked loop (PLL) 50, two delay serial circuits 52 and 54 and a sampler 56. The phase locked loop 50 is part of a field programmable gate array. The phase locked loop 50 generates two sets of clock signal sources C0 and C1. The clock signal source C1 is the clock signal source of the sampler 56. C0 is the data source of the sampler 56. Clock jitter is an unpredictable interference factor. Therefore, it is impossible to predict whether the sampled data falls within the metastable interval and obtain unexpected data. The clock signal source C0 is connected to the delay serial circuit 52. The clock signal source C1 is connected to the delay serial circuit 54. The delay serial circuits 52 and 54 are composed of a number of configurable signal generators 48.

Referring to Figures 5 and 6, the random source 26 is a metastable random source, It also includes two multiplexers 36 and 38, two inverters 46 and 47, and two delay serial circuits 52 and 54. The multiplexer 36, the inverter 46 and the delay series circuit 52 are connected. The multiplexer 38, the inverter 47 and the delay series circuit 54 are connected. When the selection signal is true (1), inverters 46 and 47 each generate an oscillation signal between 0 and 1. When the selection signal is false (0), the output of the inverter 46 is connected to the input of the multiplexer 38, and the output of the inverter 47 is connected to the input of the multiplexer 36. At this time, the input and output values of inverters 46 and 47 cannot be determined. When the logic state conflicts, it will enter the metastable interval, and the steady-state result after the mean time between failures (MTBF) time cannot be expected. , Resulting in unexpected value of sampling register. In this way, a random number is generated.

Referring to FIG. 7, the inverters 46 and 47 and the delay serial circuits 52 and 54 may include a number of configurable signal generators 48. Each configurable signal generator 48 can output the same direction or reverse signal according to the mode, and includes a connected configurable controller 58, a configurable multiplexer 59 and a configurable static random access memory array 60 . The configurable controller 58, the configurable multiplexer 59, and the configurable static random access memory array 60 are not limited to a specific number and form. The configurable controller 58 dynamically selects the output path of the configurable multiplexer 59 to achieve different delay effects and ensure unpredictability.

Referring to FIG. 8, the thermometer 32 includes a temperature sensor 66 and is connected to the sampling controller 18 through an analog-to-digital converter (ADC) 62 of the field programmable gate array. The voltmeter 34 includes a voltage sensor 68 and is connected to the sampling controller 18 through another analog-to-digital converter 64 of the field programmable gate array. The analog-to-digital converters 62 and 64 are substantially the same. In this way, the analog-to-digital converters 62 and 64 respectively convert the signals from the temperature sensor 66 and the voltage sensor 68 from analog to digital for the sampling controller 18 to use.

The above is only a description of the preferred embodiments of the present invention and is not intended to limit Determine the scope of the invention. The equal changes made by those skilled in the art based on the above-mentioned embodiments and the changes well known to those skilled in the art are still within the scope of the present invention.

10‧‧‧Real random number generator

12‧‧‧Entropy Harvester

14‧‧‧Post processor

16‧‧‧User Interface

18‧‧‧Sampling Controller

20‧‧‧Random source group

22, 24, 26‧‧‧ random source

30‧‧‧Environmental Sensing Group

32‧‧‧Thermometer

34‧‧‧Voltmeter

Claims (12)

A random number generator of field programmable gate array includes: a random source group (20) is used to provide random signals; an environmental sensing group (30) is used to provide environmental signals; a sampling controller (18) is connected The random source group (20) and the environmental sensing group (30); and an entropy harvester (12) is connected to the random source group (20) and the sampling controller (18), so that the entropy harvester (12) Use random signals and environmental signals to generate random numbers; a post processor (14) is connected to the entropy harvester (12), receives the random numbers from the entropy harvester (12), and converts them into the required format; The user interface (16) is connected to the post processor (14), provides random numbers in the required format, receives external signals and connects to the sampling controller (18) so that the user interface (16) feeds back the sampling controller (18) ) Is used to generate unexpected control signals to the random source group (20). The random number generator of the field programmable gate array described in the scope of patent application, wherein the random source group (20) includes a first random source (22), a second random source (24) and a third random source (26). The random number generator of the field programmable gate array described in the second item of the scope of patent application, wherein the first random source (22) includes: two ring oscillators (40, 42), each ring oscillator (40, 42) It includes several inverters (46) connected in series, and each inverter (46) includes several configurable signal generators (48); and A sampler (44) is connected to the two ring oscillators (40, 42). The random number generator of the field programmable gate array described in item 3 of the scope of patent application, in which each configurable signal generator (48) outputs a forward or reverse signal according to the mode, and includes connected configurable State controller (58), configurable multiplexer (59) and configurable static random access memory array (60), wherein the configurable controller (58) dynamically adjusts the configurable multiplexer ( 59) Output path, thus ensuring unpredictability. The random number generator of the field programmable gate array described in item 2 of the scope of patent application, wherein the second random source (24) includes: a phase locked loop (50) including two clock signal sources (C0, C1); Two delay serial circuits (52, 54) are respectively connected to the two clock signal sources (C0, C1), each delay serial circuit (52, 54) includes a number of configurable signal generators (48); and a sampler (56) Connect the two delay serial circuits (52, 54). The random number generator of the field programmable gate array described in item 5 of the scope of patent application, wherein each configurable signal generator (48) outputs a forward or reverse signal according to the mode, and includes the connected configurable State controller (58), configurable multiplexer (59) and configurable static random access memory array (60), wherein the configurable controller (58) dynamically adjusts the configurable multiplexer ( 59) Output path, thus ensuring unpredictability. The random number generator of the field programmable gate array described in item 2 of the scope of patent application, wherein the third random source (26) includes: a plurality of delay serial circuits (52, 54), each delay serial circuit ( 52,54) including several configurable signal generators (48); several multiplexers (36,38); and Several inverters (46, 47), connected to the delay serial circuit (52, 54) and the multiplexer (36, 38), can determine the working mode of the third random source (26), each inverted The device includes several configurable signal generators (48). The random number generator of the field programmable gate array as described in item 7 of the scope of patent application, wherein each configurable signal generator (48) outputs a forward or reverse signal according to the mode, and includes the connected configurable State controller (58), configurable multiplexer (59) and configurable static random access memory array (60), wherein the configurable controller (58) dynamically adjusts the configurable multiplexer ( 59) output path, therefore ensuring unpredictability. According to the field programmable gate array random number generator described in the first item of the patent application, the environmental sensing group (30) includes a thermometer (32) and a voltmeter (34). According to the field programmable gate array random number generator described in item 9 of the scope of patent application, the thermometer (32) includes a temperature sensor (66) and an analog-to-digital converter (62). According to the field programmable gate array random number generator described in the scope of patent application, the voltmeter (34) includes a voltage sensor (68) and an analog-to-digital converter (64). The random number generator of the field programmable gate array described in item 1 of the scope of patent application, wherein the post processor (14) is connected to the sampling controller (18) so that the post processor (14) feeds back the sampling controller ( 18) And this feedback is used to generate unexpected control signals to the random source group (20).

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