CN102497206A - Clock control device and system-on-chip comprising same - Google Patents
Clock control device and system-on-chip comprising same Download PDFInfo
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- CN102497206A CN102497206A CN2011103881360A CN201110388136A CN102497206A CN 102497206 A CN102497206 A CN 102497206A CN 2011103881360 A CN2011103881360 A CN 2011103881360A CN 201110388136 A CN201110388136 A CN 201110388136A CN 102497206 A CN102497206 A CN 102497206A
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Abstract
The invention discloses a clock control device. The clock control device comprises a frequency dividing unit and a gating unit, wherein the frequency dividing unit is used for receiving a plurality of clock domain signals and dividing frequency of the clock domain signals on a system-on-chip to obtain a signal required by a functional module on the system-on-chip; the gating unit is used for gating the signal output by the frequency dividing unit and forms a bypass circuit, and the bypass circuit is used for outputting the clock frequency required by the functional module through the gating unit when an enabling signal port is tested to be low level or high level; and when an enabling signal port is tested to be high level or low level, the bypass unit outputs a preset signal. Clock signals with a plurality of frequencies are provided to a plurality of functional modules of the system-on-chip by generating high-frequency clock through an externally input crystal oscillator clock, dividing frequency of medium and high clocks and controlling the medium and high clocks; and the bypass unit is designed according to the requirement that the clock signals are required to be controllable in overall situation when the system-on-chip is tested, so the normal work of the system-on-chip and the overall controllability of the clock signals during test are ensured.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly, the present invention relates to clock control device and comprise the SOC(system on a chip) of clock control device.
Background technology
SOC(system on a chip) is on a slice Semiconductor substrate, to form a complete electronic system, is the inexorable trend of application-specific integrated circuit (ASIC) development, and as a kind of world sophisticated technology, SOC(system on a chip) just occurs as far back as the nineties in 20th century.Along with the development of integrated circuit technique continuity Moore's Law, system-on-chip designs has developed into mainstream technology.Architecture based on ARM is the main flow of current system-on-chip designs; This is comprising selecting ARM (Advanced RISC Machines for use; Senior reduced instruction set processor) processor core and AMBA bus protocol (Advanced controller Bus Architecture, advanced microprocessor bus framework).SOC(system on a chip) comprises other functional modules such as embedded central processing unit, digital signal processor and communication module, and these modules are carried out interconnected through the bus based on the AMBA agreement.Clock signal is one of of paramount importance signal in the SOC(system on a chip).The difficult SOC(system on a chip) demand that satisfies the function complicacy in single clock territory; Therefore SOC(system on a chip) need provide a plurality of clock zones; Consider the low-power consumption demand of SOC(system on a chip) further; SOC(system on a chip) need carry out frequency division design to clock zone, so SOC(system on a chip) proposed very high requirement to the management of clock signal, and any point design error all will cause the chip cisco unity malfunction.
In the prior art; A kind of functional module of SOC(system on a chip); For example embedded central processing unit and/or APB bridge module all do not have bus clock; Can only come perception bus clock rising edge whether to arrive through high level, so the system clock control device must guarantee that the sequential relationship of master clock and enable signal of each module is correct, otherwise the functional module of SOC(system on a chip) is with cisco unity malfunction in master clock rising edge sense enable signal.
Therefore; Needs based on reality; Be necessary to propose the corresponding techniques scheme; Embedded central processing unit, digital signal processor and the communication modules etc. that solve SOC(system on a chip) are accomplished the controlling Design of this SOC(system on a chip) clock signal for the demand for control of clock signal separately, guarantee that each module of SOC(system on a chip) can operate as normal.
Summary of the invention
The object of the invention is intended to solve at least one of above-mentioned technological deficiency, particularly through clock control device a plurality of clock zones is carried out frequency division and control, provides multiple clock frequency to guarantee that each module of SOC(system on a chip) can operate as normal to a plurality of functional modules thereafter.
The embodiment of the invention has proposed a kind of clock control device on the one hand, comprises frequency unit and gating unit,
Said frequency unit is used to receive a plurality of clock zone signals, and said a plurality of clock zone signals of SOC(system on a chip) are carried out frequency division, obtains the required signal of functional module of SOC(system on a chip);
Said gating unit; Be used for the signal of said frequency unit output is carried out gating; Said gating unit forms bypass circuit; Said bypass circuit is used for when the test enable signal port is low level or high level, and said bypass circuit is exported the required clock frequency of said functional module through said gating unit; When the test enable signal port is high level or low level, said bypass circuit output preset signals.
The embodiment of the invention has proposed a kind of SOC(system on a chip) that comprises the clock control device with above-mentioned technical characterictic on the other hand; Said SOC(system on a chip) comprises SOC(system on a chip) functional module and clock control device, wherein, and said clock control device; Comprise frequency unit and gating unit
Said frequency unit is used to receive a plurality of clock zone signals, and said a plurality of clock zone signals of SOC(system on a chip) are carried out frequency division, obtains the required clock frequency of said functional module of SOC(system on a chip);
Said gating unit; Be used for the signal of said frequency unit output is carried out gating; Said gating unit forms bypass circuit; Said bypass circuit is used for when the test enable signal port is low level or high level, and said bypass circuit is exported the required clock frequency of said functional module through said gating unit; When the test enable signal port was high level or low level, the clock signal of said bypass circuit output was a preset signals.
The such scheme that the present invention proposes through multi-clock zone being carried out the control of frequency division and gating, provides the signal of multiple frequency thereafter to a plurality of functional modules of SOC(system on a chip).Simultaneously, clock signal needs the controlled requirement of the overall situation carry out the bypass circuit design when testing to SOC(system on a chip), the overall controllability of clock signal when guaranteeing the SOC(system on a chip) operate as normal with test.In addition, the such scheme that the present invention proposes, very little to the change of existing system, can not influence the compatibility of system, and realize simple, efficient.
Aspect that the present invention adds and advantage part in the following description provide, and these will become obviously from the following description, or recognize through practice of the present invention.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously with easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1 is an embodiment of the invention clock control device functional schematic;
Fig. 2 is a kind of SOC(system on a chip) sketch map of the embodiment of the invention;
Fig. 3 is the another kind of SOC(system on a chip) sketch map of the embodiment of the invention;
Fig. 4 is embedded central processing unit master clock and system bus clock sketch map.
Embodiment
Describe embodiments of the invention below in detail, the example of said embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Be exemplary through the embodiment that is described with reference to the drawings below, only be used to explain the present invention, and can not be interpreted as limitation of the present invention.
In order to realize the present invention's purpose, the embodiment of the invention has proposed a kind of clock control device, comprises frequency unit and gating unit.
Particularly, frequency unit is used to receive a plurality of clock zone signals, and said a plurality of clock zone signals of SOC(system on a chip) are carried out frequency division, obtains the required clock frequency of functional module of SOC(system on a chip); Gating unit is used for the signal of said frequency unit output is carried out gating.As embodiments of the invention, the SOC(system on a chip) functional module includes but not limited to functional modules such as embedded central processing unit, communication module, peripheral module and/or signal processing module.Said gating unit forms bypass circuit, and said bypass circuit is used for when test enable signal TM port is low level or high level, and said bypass circuit is exported the required clock frequency of said functional module through said gating unit; When test enable signal TM port is high level or low level; Said bypass circuit output preset signals, and for SOC(system on a chip), when the gating unit is the clock signal gating unit; Preset signals provides through the external crystal-controlled oscillation of SOC(system on a chip) usually; And when the gating unit was clock enable signal gating unit, preset signals was generally high level, to satisfy test controllability demand.Furthermore, clock control device comprises that also clock zone is provided with the unit, and said clock zone is provided with the unit and receives the SOC(system on a chip) external signal, produces frequency doubling clock and forms said a plurality of clock zone signal and said a plurality of clock zone signals are imported said frequency unit.Clock zone is provided with the unit and for example realizes through phase-locked loop pll (Phase Locked Loop, phase-locked loop), utilizes the input of external crystal-controlled oscillation clock to produce the needed multi-clock zone signal of said SOC(system on a chip) through phase-locked loop.
As embodiments of the invention, shown in Figure 1, be the circuit diagram of the clock control device of concrete SOC(system on a chip) of the present invention.
For example; Clock control device of the present invention further segments; Comprise central processing clock submodule, Digital Signal Processing clock submodule, communication clock submodule and bus clock submodule, realize comprising the clock control of embedded central processing unit, digital signal processor and communication module and bus slave module and peripheral module through above-mentioned submodule respectively.
Obviously, should be appreciated that can many as required branches or be divided into several period of the day from 11 p.m. to 1 a.m clock modules less, and concrete condition should be decided according to the needs of SOC(system on a chip).
In the above-described embodiments, clock control device carries out frequency division for 3 clock zones provides a plurality of clock frequencies with the control back to a plurality of functional modules.Be specially; After being provided with the unit through clock zone, the signal that is produced by the on-chip system chip external crystal-controlled oscillation is divided into three clock zones; Clock zone is provided with the unit and for example can realizes through phase-locked loop pll; Clock entering frequency unit and gating unit that clock zone is provided with unit output carry out frequency division and bypass circuit design, obtain the clock frequency that each functional module needs.
For achieving the above object, as shown in Figure 1, clock control device for example comprises 6 frequency units and 11 gates.The output clock of 6 frequency units is respectively the bus clock hclk1 of embedded central processing unit, bus clock pclk1, the first communication clock clk_4x, the second communication clock clk_2x, the 3rd communication clock clk_1x and the four-way news clock clk_1x_div2 of peripheral module.The two divided-frequency of in above-mentioned clock control device, using and two kinds of frequency dividing circuits of four frequency divisions all adopt counter to realize.For two divided-frequency, adopt 1 digit counter count, this counter adds 1 at the input clock rising edge, two divided-frequency output clock o_clk=count [0], promptly the output clock is a high level when count is 1, count is that 0 o'clock output clock is a low level.Two divided-frequency output clock enable signal is sampled to count [0] at the input clock rising edge and is exported.For four frequency divisions; Adopt 2 digit counter count [1:0], this counter adds 1, four frequency division output clock o_clk=count [1] at the input clock rising edge; Promptly the output clock is a high level when count [1:0] is 2 or 3, and the output clock is a low level when count [1:0] is 0 or 1.Four frequency divisions output clock enable signal is judged count [1] at the input clock rising edge | count [0] expression formula, four frequency divisions output clock enable signal is effective when this expression formula is 0, can invalidating signal when four frequency divisions are exported clock when this expression formula is 1.
Along with the raising of integrated circuit technology level and the development of the market demand, the scale of chip is increasing, so need test to reject defective chip at tester table after the monster chip production.The SOC(system on a chip) test is made up of scan chain technique, boundary scan technique, built-in self-test technology and functional test, and these measuring technologies have all proposed " controllability " requirement to clock signal.In order to satisfy the top layer controllability requirement of all clocks under test pattern, as illustrating, 11 gates are accomplished the bypass circuit design of clock control device output signal.11 clock signals exporting among Fig. 1 are exported to SoC (System On a Chip through behind the gating unit; SOC(system on a chip)) functional module is used; When test enable signal TM port was low level, the clock signal of all bypass circuit outputs was the required clock frequency of each functional module; When test enable signal TM port is high level; The output of clock signal gating unit is the crystal oscillator input of chip exterior; Clock enable signal gating unit; For example the output of hclklen gate and pclklen gate is always high level, and this clock signal that has just guaranteed chip internal on board can both be controlled by the chip exterior pin.
The required signal of said functional module comprises clock signal and/or the clock enable signal that said functional module work is required; Adopt same frequency unit to produce required clock signal of each functional module work and clock enable signal; Can save circuit area, guarantee that again circuit design satisfies the sequential demand of embedded central processing unit and/or APB bridge module.
Based on embodiments of the invention, frequency unit includes but not limited to frequency-halving circuit and/or divide by four circuit, and frequency dividing circuit for example adopts counter to realize.
Based on embodiments of the invention, when signal processing module does not possess the clock division function, obtain the bus clock of said signal processing module through the output of frequency unit frequency division.
As the embodiment of the invention, the invention allows for a kind of SOC(system on a chip), comprise SOC(system on a chip) functional module and clock control device, wherein, said clock control device comprises frequency unit and gating unit.
Particularly, said frequency unit is used to receive a plurality of clock zone signals, and said a plurality of clock zone signals of SOC(system on a chip) are carried out frequency division, obtains the required signal of functional module of SOC(system on a chip); Said gating unit is used for the signal of said frequency unit output is carried out gating.As embodiments of the invention, the SOC(system on a chip) functional module includes but not limited to functional modules such as embedded central processing unit, communication module, peripheral module and signal processing module.Said gating unit forms bypass circuit, and said bypass circuit is used for when test enable signal TM port is low level or high level, and said bypass circuit is exported the required clock frequency of said functional module through said gating unit; When test enable signal TM port is high level or low level, said bypass circuit output preset signals, said preset signals is provided by the on-chip system chip external crystal-controlled oscillation.
Furthermore, also comprise ahb bus, AHB equipment, APB bridge module and peripheral module in the SOC(system on a chip), ahb bus, AHB equipment, APB bridge module and peripheral module provide clock signal through said clock control device.
Like Fig. 2; Be the sketch map of a kind of SOC(system on a chip) of the embodiment of the invention, comprise the digital signal processor and the clock control device of embedded central processing unit, ahb bus, AHB equipment, APB bridge module, peripheral module, communication module, clock frequency unit.
Embedded central processing unit and peripheral module need come the rising edge of difference sensory perceptual system bus clock (HCLK) and peripheral bus clock (PCLK) respectively through system bus clock enable signal (HCLKEN) and peripheral bus clock enable signal (PCLKEN); Therefore clock control device needs to produce system bus clock enable signal hclklen and peripheral bus clock enable signal pclklen when producing hclk1 and pclk1.
Wherein, Said clock zone is provided with the unit and receives the SOC(system on a chip) external signal; Producing frequency doubling clock forms said a plurality of clock zone signal and said a plurality of clock zone signals is imported said frequency unit; Clock zone is provided with the unit and can adopts a plurality of phase-locked loops (PLL) to realize, utilizes the low-frequency clock (XIN) of chip exterior input to produce the needed medium-high frequency clock of chip internal.Chips of the present invention needs 3 clock frequencies, is respectively 220MHz, 165MHz and 89.6MHz, and the output reference clock frequency of embodiment of the invention PLL is that 25MHz is to 600MHz.Said 3 clock zones are respectively the master clock of embedded central processing unit; The master clock of digital signal processor; The master clock of communication function module, wherein, the master clock cpu_clk of embedded central processing unit is 220MHz; The two divided-frequency of the central processing clock submodule of master clock cpu_clk process forms the bus clock hclk1 of embedded central processing unit, and master clock cpu_clk forms peripheral bus clock pclk1 through eight frequency divisions of peripheral clock submodule; The master clock clk_8x of communication function module is 89.6MHz, carries out the two divided-frequency clk_1x_div2 that frequency division forms three frequency-dividing clock clk_1x, clk_2x, clk_4x and clk_1x through the communication clock submodule.The digital signal processor that the present invention adopts adopts the clock frequency unit, so the present technique scheme do not carry out to the bus clock dsp_clk of digital signal processor that frequency-dividing clock produces and control, accomplishes frequency division and control by digital signal processor.
As another embodiment of the present invention; When not having the digital signal processor of clock frequency unit for other models of employing; Digital signal processor master clock dsp_clk (165MHz); Digital Signal Processing clock submodule via clock control device carries out the bus clock hclk2 that two divided-frequency forms digital signal processor to it, and digital signal processor master clock dsp_clk forms peripheral bus clock pclk2 through eight frequency divisions, and sketch map is for example shown in Figure 3.
Particularly, as shown in Figure 4, be the sketch map that concerns of embedded central processing unit master clock and system bus clock.Embedded central processing unit does not have the bus clock input; Can only come sensory perceptual system bus clock (HCLK) rising edge whether to arrive through high level at master clock (CLK) rising edge detection system bus clock enable signal (HCLKEN); Thereby correct output bus signal is given system bus, and the input signal of system bus is correctly sampled.
The SoC system control method that the above embodiment of the present invention proposes; With the Clock management of the SoC system that accomplishes integrated embedded central processing unit, digital signal processor, wireless communication module etc., comprise under the mode of operation that frequency-dividing clock produces and test pattern under test clock produce.Adopt system control module design provided by the present invention; Can satisfy among the multi-clock zone SoC of integrated a plurality of IP (Intellectual Property, intellectual property) nuclear clock division circuits designing requirement, embedded central processing unit and/or peripheral bus bridge module to the sequential relationship requirement of bus master clock and enable signal and clock test pattern under overall controllability requirement.
The such scheme that the present invention proposes carries out frequency division and control through utilizing clock control device to a plurality of clock zones, to a plurality of functional modules a plurality of clock frequencies is provided thereafter.Be specially; After being provided with the unit through clock zone, the signal that is produced by the chip exterior crystal oscillator is divided into a plurality of clock zones; Clock zone is provided with the unit and for example realizes through phase-locked loop pll; Clock entering frequency unit and gating unit that clock zone is provided with unit output carry out frequency division and bypass circuit design; Obtain the clock frequency that each functional module needs, clock signal needs the controlled requirement of the overall situation carry out the bypass circuit design when test to SOC(system on a chip), the overall controllability of clock signal when guaranteeing the SOC(system on a chip) operate as normal and testing.In addition, the such scheme that the present invention proposes, very little to the change of existing system, can not influence the compatibility of system, and realize simple, efficient.
Though specify about example embodiment and advantage thereof, be to be understood that under the situation of the protection range that does not break away from the qualification of spirit of the present invention and accompanying claims, can carry out various variations, replacement and modification to these embodiment.For other examples, when those of ordinary skill in the art should understand easily in keeping protection range of the present invention, the order of processing step can change.
In addition, range of application of the present invention is not limited to technology, mechanism, manufacturing, material composition, means, method and the step of the specific embodiment of describing in the specification.From disclosure of the present invention; To easily understand as those of ordinary skill in the art; For the technology, mechanism, manufacturing, material composition, means, method or the step that have existed or be about to later on develop at present; Wherein they are carried out the corresponding embodiment cardinal principle identical functions of describing with the present invention or obtain identical substantially result, can use them according to the present invention.
Therefore, accompanying claims of the present invention is intended to these technology, mechanism, manufacturing, material composition, means, method or step are included in its protection range.Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention, can also make some improvement and retouching, these improvement and retouching also should be regarded as protection scope of the present invention.
Claims (12)
1. a clock control device is characterized in that, comprises frequency unit and gating unit,
Said frequency unit is used to receive a plurality of clock zone signals, and said a plurality of clock zone signals of SOC(system on a chip) are carried out frequency division, obtains the required signal of functional module of SOC(system on a chip);
Said gating unit; Be used for the signal of said frequency unit output is carried out gating; Said gating unit forms bypass circuit; Said bypass circuit is used for when the test enable signal port is low level or high level, and said bypass circuit is exported the required clock frequency of said functional module through said gating unit; When the test enable signal port is high level or low level, said bypass circuit output preset signals.
2. clock control device as claimed in claim 1 is characterized in that, the required signal of said functional module comprises clock signal and/or the clock enable signal that said functional module work is required.
3. clock control device as claimed in claim 1 is characterized in that, comprises that also clock zone is provided with the unit,
Said clock zone is provided with the unit and receives the SOC(system on a chip) external signal, produces frequency doubling clock and forms said a plurality of clock zone signal and said a plurality of clock zone signals are imported said frequency unit, and said clock zone is provided with the unit and realizes through phase-locked loop.
4. clock control device as claimed in claim 1 is characterized in that said frequency unit comprises frequency-halving circuit and/or divide by four circuit, and said frequency dividing circuit adopts counter to realize.
5. clock control device as claimed in claim 1 is characterized in that, said SOC(system on a chip) functional module comprises: embedded central processing unit, communication module, peripheral module and/or signal processing module.
6. clock control device as claimed in claim 5 is characterized in that, when said signal processing module does not possess the clock division function, obtains the bus clock of said signal processing module through said frequency unit frequency division output.
7. a SOC(system on a chip) is characterized in that, comprises SOC(system on a chip) functional module and clock control device, and wherein, said clock control device comprises frequency unit and gating unit,
Said frequency unit is used to receive a plurality of clock zone signals, and said a plurality of clock zone signals of SOC(system on a chip) are carried out frequency division, obtains the required signal of functional module of SOC(system on a chip);
Said gating unit; Be used for the signal of said frequency unit output is carried out gating; Said gating unit forms bypass circuit; Said bypass circuit is used for when the test enable signal port is low level or high level, and said bypass circuit is exported the required clock frequency of said functional module through said gating unit; When the test enable signal port is high level or low level, said bypass circuit output preset signals.
8. SOC(system on a chip) as claimed in claim 7 is characterized in that, the required signal of said functional module comprises clock signal and/or the clock enable signal that said functional module work is required.
9. SOC(system on a chip) as claimed in claim 7 is characterized in that, comprises that also clock zone is provided with the unit,
Said clock zone is provided with the unit and receives the SOC(system on a chip) external signal, produces frequency doubling clock and forms said a plurality of clock zone signal and said a plurality of clock zone signals are imported said frequency unit, and said clock zone is provided with the unit and realizes through phase-locked loop.
10. SOC(system on a chip) as claimed in claim 7 is characterized in that said frequency unit comprises frequency-halving circuit and/or divide by four circuit, and said frequency dividing circuit adopts counter to realize.
11. SOC(system on a chip) as claimed in claim 7 is characterized in that, said SOC(system on a chip) functional module comprises: embedded central processing unit, communication module, peripheral module and/or signal processing module.
12. SOC(system on a chip) as claimed in claim 11 is characterized in that, when said signal processing module does not possess the clock division function, obtains the bus clock of said signal processing module through said frequency unit frequency division output.
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| CN109283833A (en) * | 2018-10-26 | 2019-01-29 | 北京无线电测量研究所 | A kind of time statistical system and method |
| CN112214450A (en) * | 2020-10-12 | 2021-01-12 | 湃方科技(天津)有限责任公司 | Edge intelligent SOC processor and electronic equipment |
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