CN1889364A - Clock generating device based on lock-phase ring - Google Patents
Clock generating device based on lock-phase ring Download PDFInfo
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- CN1889364A CN1889364A CNA2006100888742A CN200610088874A CN1889364A CN 1889364 A CN1889364 A CN 1889364A CN A2006100888742 A CNA2006100888742 A CN A2006100888742A CN 200610088874 A CN200610088874 A CN 200610088874A CN 1889364 A CN1889364 A CN 1889364A
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Abstract
This invention discloses a clock generation device based on a phase-locking ring including a crystal oscillator, a first phase-lock ring and a digital clock frequency divider characterizing in also including a clock frequency process unit, the clock signals output by said crystal oscillator pass through the first phase locking ring to be input into said clock frequency process unit, which regulates the frequency sphere of the clock signals output by the first phase-locking ring based on said clock frequency, then multiple digital dividers divide the output signals of the first phase-locking ring and the clock signals to get the clock of necessary frequencies.
Description
Technical field
The present invention relates to the clock circuit design field.
Background technology
Along with the increase of chip integration, complexity and functional requirement, in a lot of digital circuitries, all needing provides different frequency and clock signals for each functional module of chip internal and ancillary equipment.The clock generating of multi-clock zone and clock trees structure Design are the problems that each chip design engineer must solve.
In order to satisfy chip internal and outside existing a lot of design of electronic products adopt a plurality of crystal oscillators with the requirement on devices of the different clock frequencies operation of large span very, a plurality of phase-locked loops and digital frequency divider realize that its implementation as shown in Figure 1.As can be seen from Figure 1, be the Generation of Clock Signal of integral multiple frequency division for operating frequency, can utilize single crystal oscillator and phase-locked loop circuit, and several digital frequency dividers are realized.If adopt programmable digital frequency divider and phase-locked loop, just can satisfy the requirement of more different clock frequencies, but the clock frequency that produces can only be the frequency of the integral frequency divisioil of clock source behind frequency multiplication of phase locked loop, and wherein frequency multiplication can be that integral multiple also can be the branch several times.
With existing a kind of phase-locked loop is example, and its output frequency can calculate by following formula:
F
output＝F
ref*2N；F
ref＝F
input/r
Wherein, r and N are integer, and so for the fixing phase-locked loop of incoming frequency, the output frequency that its scalable goes out is some discrete points, can not cover each point in the reference frequency output.Therefore, for the frequency that needing to obtain, prior art has adopted a plurality of different oscillators, obtains the clock of different frequency, imports in the phase-locked loop respectively again.Like this, in case after the systematic function complexity increases, just can't only utilize single crystal oscillator to obtain needed clock frequency.
Summary of the invention
Technical problem to be solved by this invention provides a kind of clock generating device based on phase-locked loop, adopts single crystal oscillator just can satisfy the requirement of complication system, with respect to prior art, has increased the flexibility of the coverage rate and the system of clock frequency.
For solving the problems of the technologies described above, the invention provides a kind of clock generating device based on phase-locked loop, comprise a crystal oscillator, first phase-locked loop and digital dock frequency divider, it is characterized in that, also comprise a clock frequency processing unit, the clock signal of described crystal oscillator output is input to described clock frequency processing unit through first phase-locked loop, described clock frequency processing unit is regulated the frequency range of the clock signal of first phase-locked loop output according to required clock frequency, by one or more digital dock frequency dividers the output signal of described first phase-locked loop and clock frequency processing unit is carried out frequency division again, obtain the clock of required frequency.
Further, said apparatus also can have following characteristics: described clock frequency processing unit comprises the frequency unit and second phase-locked loop, input clock signal is imported described second phase-locked loop behind described frequency unit frequency division, the output signal of described second phase-locked loop is the output signal of clock frequency processing unit.
Further, said apparatus also can have following characteristics: described clock frequency processing unit comprises first frequency unit of serial connection and second frequency unit and the 3rd phase-locked loop of second phase-locked loop and serial connection, input clock signal is imported first frequency unit and second frequency unit simultaneously, and the output signal while of second phase-locked loop and the 3rd phase-locked loop is as the output signal of clock frequency processing unit.
Further, said apparatus also can have following characteristics: also comprise selector, the output signal of described first phase-locked loop and clock frequency processing unit is input to one or more selectors earlier, and the output signal of described selector is input to one or more digital dock frequency dividers again and carries out frequency division.
Further, said apparatus also can have following characteristics: described frequency unit is the digital dock frequency divider.
Further, said apparatus also can have following characteristics: an output is the clock signal of integer multiple frequency in described first phase-locked loop and second phase-locked loop, another output be the fractional frequency clock signal.
Adopt device of the present invention, following advantage arranged:
(1) utilize the two phase-locked loop cascade can produce the very big frequency of distribution;
(2) utilize the parameter of the phase-locked loop combination different, satisfy the requirement of all clock frequencies with the digital dock divider configuration;
(3) software programmable logic makes the switching of different time domain very flexible.
Description of drawings
Fig. 1 is that prior art produces the implementation method of clock frequency for a long time;
Fig. 2 is the clock generating device that the present invention is based on two phase-locked loop;
Fig. 3 is the clock generating device of secondary phase-locked loop of the present invention parallel connection.
Embodiment
In the present embodiment, also produce the clock signal of different complicated clock zones in the chip simultaneously according to same reference signal in order only to utilize single crystal oscillator, we have adopted programmable two phase-locked loop and programmable digital dock frequency divider.Come to satisfy the clock request of chip internal and outside different sophisticated functions and application to the phase-locked loop parameter different and combination thereof with the digital dock divider configuration by software programming.
Its implementation as shown in Figure 2.One crystal oscillator links to each other with phase-locked loop 1, the output signal of phase-locked loop 1 through a digital dock frequency divider frequency division after the input phase-locked loop 2, the output signal of phase-locked loop 1 and phase-locked loop 2 can be connected one or more groups selector and digital dock frequency divider, the output signal of phase-locked loop 1 and phase-locked loop 2 is imported one or more selectors, and the output signal of selector is imported one or more digital dock frequency dividers again.
Phase-locked loop is the unit that can realize multi-functional, and in this circuit, phase-locked loop plays frequency multiplication and synchronous effect simultaneously.The cascade of adopting phase-locked loop is for the coverage rate that increases clock frequency and the flexibility of system.If output to two phase-locked loops (promptly two phase-locked loops directly in parallel), the then not tangible variation of the output frequency coverage of these two phase-locked loops with a crystal oscillator.The Clock Multiplier Factor of phase-locked loop has certain scope, and the input clock to phase-locked loop has certain frequency requirement, digital dock frequency divider between two phase-locked loops, both having played adjusting phase-locked loop input clock frequency makes it satisfy required frequency requirement, also increased the flexibility of system, be equivalent to increase an adjustable parameter, thereby make phase-locked loop 2 can access the output frequency value that some original accent do not come out, thereby make the output clock frequency of phase-locked loop 1 and the output clock frequency of phase-locked loop 2 more kinds of combinations can occur.
Utilize the cascade of two phase-locked loops and the configuration of digital dock frequency divider between them, can produce the bigger frequency of distribution, more exported clock frequency, make clock system satisfy the demand of more application modules.In another embodiment, the digital dock frequency divider that also can replace above-mentioned phase-locked loop 2 and input thereof to connect with the frequency multiplier circuit of other form, also can reach basic effect of the present invention, but flexibility is not as the foregoing description, and adopting phase-locked loop and digital dock frequency divider still is the preferably selection of low-cost and high-performance.
The output of two phase-locked loops is selected with selector, and making each road on the clock trees that the phase-locked loop 1 of selection can be arranged still be the freedom of phase-locked loop 2, and the user can select dynamically according to the needs of self and module.Certainly, the present invention does not get rid of the mode that the output of two phase-locked loops is directly connected to one or more digital dock frequency dividers.
Be example with above phase-locked loop still, its output frequency can calculate by following formula:
F
output＝F
ref*2N；F
ref＝F
input/r
Suppose F
RefBe reference frequency, 0.2Mhz＜F
RefBetween＜the 6Mhz, F
InputBe incoming frequency, 2＜r＜63,2＜N＜2047,500Mhz＜F
Output＜900Mhz, r, N are integer.
The output frequency of supposing crystal oscillator is 12Mhz.After the frequency multiplication of phase-locked loop 1, be output as 768Mhz.This output clock by behind the frequency division of a digital dock frequency divider coefficient as the incoming frequency of phase-locked loop 2.The parameter of phase-locked loop 2 can dispose the coefficient of frequency multiplication by software programming.Phase-locked loop 1 and 2 output frequency select 1 selector to select one of them input as the digital dock frequency divider by 2.If the selector behind the phase-locked loop is selected the output of phase-locked loop 1 so, behind digital dock frequency divider frequency division, can satisfy the clock request of the integer multiple frequency division of any 768Mhz, as 96Mhz, 48Mhz, 24Mhz, 12Mhz.
Satisfy the requirement of some fractional frequency clocks if desired, as 24.576Mhz, 22.576Mhz, the various combination of coefficient that then can be by the configuration parameter of phase-locked loop 2 and output and input digit Clock dividers is finished.For example dispose phase-locked loop 2 and be output as 614.4Mhz, import a divide ratio so again and be 25 digital dock frequency divider and just can obtain the clock that frequency is 614.4Mhz/25=24.576Mhz; Perhaps dispose phase-locked loop 2 and be output as 564.4Mhz, import a divide ratio so again and be 25 digital dock frequency divider and just can obtain the clock that frequency is 564.4Mhz/25=22.576Mhz.
Say that for another example working as the external crystal-controlled oscillation frequency is 4.2M, frequency 768M that need reach and 564.4M, can pass through to phase-locked loop 1 distribution coefficient R=7 so, N=640 obtains 768M, and crystal oscillator directly can not be joined 564.4M by phase-locked loop 2, adopt the described structure of present embodiment, 768M assigns to 12M by digital frequency divider earlier, joins R=60 for phase-locked loop 2 again, N=1411 just can obtain 564.4M.
The present invention can do multiple conversion on this basis.
For example, can also adopt the simulated clock simulation clock frequency dividing circuit to replace the digital dock frequency divider to realize clock division, but digital dock frequency divider ratio being easier to realization, and can dynamically being configured, is preferable selection.
And for example, can amplify the circuit of more phase-locked loop cascades from the present invention, as adopting the phase-locked loop parallel-connection structure of secondary, as shown in Figure 3, one crystal oscillator links to each other with phase-locked loop 1, the output signal of phase-locked loop 1 through a digital dock frequency divider frequency division after the input phase-locked loop 2, simultaneously, the output signal of this phase-locked loop 1 is through input phase-locked loop 3 behind another digital dock frequency divider frequency division, phase-locked loop 1, the output signal of phase-locked loop 2 and phase-locked loop 3 can be connected many group selectors and digital dock frequency divider, phase-locked loop 1, the output signal of phase-locked loop 2 and phase-locked loop 3 is imported one or more selectors, and the output signal of selector is imported one or more digital dock frequency dividers again.Selector is used to select the output of phase-locked loop, and same, the present invention does not get rid of the mode that the output of three phase-locked loops is directly connected to one or more digital dock frequency dividers yet.
In sum, the phase-locked loop parallel-connection structure of employing secondary can satisfy the requirement of more complicated system, obtains the more clock frequency of large coverage.
Claims (6)
1, a kind of clock generating device based on phase-locked loop, comprise a crystal oscillator, first phase-locked loop and digital dock frequency divider, it is characterized in that, also comprise a clock frequency processing unit, the clock signal of described crystal oscillator output is input to described clock frequency processing unit through first phase-locked loop, described clock frequency processing unit is regulated the frequency range of the clock signal of first phase-locked loop output according to required clock frequency, by one or more digital dock frequency dividers the output signal of described first phase-locked loop and clock frequency processing unit is carried out frequency division again, obtain the clock of required frequency.
2, device as claimed in claim 1, it is characterized in that, described clock frequency processing unit comprises the frequency unit and second phase-locked loop, input clock signal is imported described second phase-locked loop behind described frequency unit frequency division, the output signal of described second phase-locked loop is the output signal of clock frequency processing unit.
3, device as claimed in claim 1, it is characterized in that, described clock frequency processing unit comprises first frequency unit of serial connection and second frequency unit and the 3rd phase-locked loop of second phase-locked loop and serial connection, input clock signal is imported first frequency unit and second frequency unit simultaneously, and the output signal while of second phase-locked loop and the 3rd phase-locked loop is as the output signal of clock frequency processing unit.
4, as claim 1 or 2 or 3 described devices, it is characterized in that, also comprise selector, the output signal of described first phase-locked loop and clock frequency processing unit is input to one or more selectors earlier, and the output signal of described selector is input to one or more digital dock frequency dividers again and carries out frequency division.
As claim 2 or 3 described devices, it is characterized in that 5, described frequency unit is the digital dock frequency divider.
6, device as claimed in claim 2 is characterized in that, an output is the clock signal of integer multiple frequency in described first phase-locked loop and second phase-locked loop, another output be the fractional frequency clock signal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100888742A CN100508397C (en) | 2006-07-21 | 2006-07-21 | Clock generating device based on lock-phase ring |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100888742A CN100508397C (en) | 2006-07-21 | 2006-07-21 | Clock generating device based on lock-phase ring |
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| CN1889364A true CN1889364A (en) | 2007-01-03 |
| CN100508397C CN100508397C (en) | 2009-07-01 |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101944912A (en) * | 2010-07-30 | 2011-01-12 | 炬力集成电路设计有限公司 | Monocrystal oscillator electronic device and method for determining frequency division coefficient |
| CN102497206A (en) * | 2011-11-29 | 2012-06-13 | 中国科学院微电子研究所 | Clock control device and system-on-chip comprising same |
| CN103269221A (en) * | 2013-04-23 | 2013-08-28 | 深圳雅图数字视频技术有限公司 | Play circuit and play system based on multiple players |
| CN104579318A (en) * | 2013-10-21 | 2015-04-29 | 安凯(广州)微电子技术有限公司 | Multichannel clock buffer |
| CN106788339A (en) * | 2016-11-25 | 2017-05-31 | 西安烽火电子科技有限责任公司 | The generating means and generation method of high frequency clock signal |
| CN110113048A (en) * | 2019-05-17 | 2019-08-09 | 芯翼信息科技(南京)有限公司 | Clock calibration circuit and clock correcting method based on phaselocked loop |
| CN111092618A (en) * | 2019-12-23 | 2020-05-01 | 珠海全志科技股份有限公司 | Frequency adjusting method and device of system-on-chip frequency modulation equipment |
-
2006
- 2006-07-21 CN CNB2006100888742A patent/CN100508397C/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101944912A (en) * | 2010-07-30 | 2011-01-12 | 炬力集成电路设计有限公司 | Monocrystal oscillator electronic device and method for determining frequency division coefficient |
| CN101944912B (en) * | 2010-07-30 | 2012-07-25 | 炬力集成电路设计有限公司 | Monocrystal oscillator electronic device and method for determining frequency division coefficient |
| CN102497206A (en) * | 2011-11-29 | 2012-06-13 | 中国科学院微电子研究所 | Clock control device and system-on-chip comprising same |
| CN103269221A (en) * | 2013-04-23 | 2013-08-28 | 深圳雅图数字视频技术有限公司 | Play circuit and play system based on multiple players |
| CN104579318A (en) * | 2013-10-21 | 2015-04-29 | 安凯(广州)微电子技术有限公司 | Multichannel clock buffer |
| CN104579318B (en) * | 2013-10-21 | 2018-05-29 | 安凯(广州)微电子技术有限公司 | A kind of multipath clock buffer |
| CN106788339A (en) * | 2016-11-25 | 2017-05-31 | 西安烽火电子科技有限责任公司 | The generating means and generation method of high frequency clock signal |
| CN110113048A (en) * | 2019-05-17 | 2019-08-09 | 芯翼信息科技(南京)有限公司 | Clock calibration circuit and clock correcting method based on phaselocked loop |
| CN111092618A (en) * | 2019-12-23 | 2020-05-01 | 珠海全志科技股份有限公司 | Frequency adjusting method and device of system-on-chip frequency modulation equipment |
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| Publication number | Publication date |
|---|---|
| CN100508397C (en) | 2009-07-01 |
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