CN104579318A - Multichannel clock buffer - Google Patents
Multichannel clock buffer Download PDFInfo
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- CN104579318A CN104579318A CN201310495994.4A CN201310495994A CN104579318A CN 104579318 A CN104579318 A CN 104579318A CN 201310495994 A CN201310495994 A CN 201310495994A CN 104579318 A CN104579318 A CN 104579318A
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Abstract
The invention belongs to the technical field of clock circuits, and provides a multichannel clock buffer which comprises a main buffer unit and n clock frequency dividing circuits, wherein one clock frequency dividing circuit is only used for buffering a clock signal and outputting the buffered clock signal; frequency dividing units of the other (n-1) clock frequency dividing circuits perform frequency dividing on clock signals according preset frequency dividing coefficients; each clock frequency dividing circuit comprises a switch unit and a buffer unit; each switch unit can be utilized for controlling the connection and disconnection of the corresponding clock frequency dividing circuit according to switch control signals, so that the multichannel clock buffer can drive a plurality of loads simultaneously, gate one or more clock frequency dividing circuits according to the switch control signals to ensure that the frequency dividing is performed on the corresponding clock signals, and provide the frequency-divided clock signals for one or more loads which have different requirements on clock frequency.
Description
Technical field
The invention belongs to clock circuit technical field, particularly relate to a kind of multipath clock buffer.
Background technology
In existing clock buffer framework, export after generally adopting single clock buffer circuit to carry out buffered to the clock signal that clock generator exports, to reach the effect of the driving force improving clock generator.But, above-mentioned existing clock buffer can only export a road clock signal, multiple load cannot be driven simultaneously, if and multiple load is different to the frequency requirement of clock signal, then existing clock buffer cannot carry out scaling down processing and variable connector gating with the object of the clock signal being reached for multiple load and providing frequency different to clock signal again.Therefore, existing clock buffer exists cannot drive multiple load simultaneously, and cannot carry out the problem of scaling down processing and the output of variable connector gating to clock signal.
Summary of the invention
The object of the present invention is to provide a kind of multipath clock buffer, be intended to solve existing clock buffer and exist cannot drive multiple load simultaneously, and the problem of scaling down processing and the output of variable connector gating cannot be carried out clock signal.
The present invention is achieved in that a kind of multipath clock buffer, and described multipath clock buffer comprises host buffer unit and n clock division circuits;
The input incoming clock signal of described host buffer unit, power supply termination DC power supply, earth terminal ground connection, described host buffer unit exports after described clock signal is carried out buffered;
A described n clock division circuits comprises the 1st clock division circuits to the n-th clock division circuits, described 1st clock division circuits to described n-th clock division circuits obtains described clock signal from the output of described host buffer unit, described 1st clock division circuits exports the 1st clock signal with described clock signal same frequency, 2nd clock division circuits exports the 2nd clock signal to the n-th clock signal after described n-th clock division circuits carries out scaling down processing according to the divide ratio preset to described clock signal respectively, n be greater than 1 positive integer,
Each clock division circuits in a described n clock division circuits includes a switch element and a buffer cell, each clock division circuits in described 2nd clock division circuits to described n-th clock division circuits includes frequency unit, described 2nd clock division circuits comprises a frequency unit, and the quantity of the frequency unit that the n-th clock division circuits comprises is 2 times of the quantity of the frequency unit that (n-1)th clock division circuits comprises;
The input of described switch element connects the output of described host buffer unit, the control end access switch controlling signal of described switch element, and described switch element controls the break-make of each clock division circuits according to described switch controlling signal;
Described frequency unit is used for carrying out scaling down processing to clock signal;
Described buffer cell is used for carrying out buffered to clock signal and exporting;
In described 1st clock division circuits, the output of the input connecting valve unit of buffer cell; In described 2nd clock division circuits to described n-th clock division circuits, one or more frequency units that each clock division circuits comprises are connected between the output of switch element and the input of buffer cell;
In described 2nd clock division circuits, the input of frequency unit and output be the output of connecting valve unit and the input of buffer cell respectively;
In described n-th clock division circuits, from the output of switch element, multiple frequency unit is sequentially connected in series the input to buffer cell;
In described 2nd clock division circuits to described n-th clock division circuits, the power end of the power end of the switch element in each clock division circuits, the power end of buffer cell and frequency unit all connects described DC power supply, the equal ground connection of earth terminal of the earth terminal of switch element, the earth terminal of buffer cell and frequency unit.
The invention provides a kind of multipath clock buffer, it comprises host buffer unit and n clock division circuits, and one of them clock division circuits exports after only carrying out buffered to clock signal, the frequency unit that all the other n-1 clock division circuits is comprised by it carries out scaling down processing according to different divide ratios to clock signal respectively, and each clock division circuits in n clock division circuits all includes switch element and buffer cell, switch element can control the break-make of each clock division circuits according to switch controlling signal, thus enable multipath clock buffer drive multiple load simultaneously, and can according to the one or more clock division circuits of switch controlling signal gating, and scaling down processing is carried out to clock signal, one or more clock frequency is required that different loads provides clock signal to be embodied as, solve existing clock buffer to exist cannot drive multiple load simultaneously, and the problem of scaling down processing and the output of variable connector gating cannot be carried out to clock signal.
Accompanying drawing explanation
Fig. 1 is the structure chart of the multipath clock buffer that the embodiment of the present invention provides;
Fig. 2 is the structure chart of the multipath clock buffer that another embodiment of the present invention provides;
Fig. 3 is the exemplary circuit structure chart of the host buffer unit involved by multipath clock buffer that the embodiment of the present invention provides;
Fig. 4 is the exemplary circuit structure chart of the switch element involved by multipath clock buffer that the embodiment of the present invention provides;
Fig. 5 is the exemplary circuit structure chart of the buffer cell involved by multipath clock buffer that the embodiment of the present invention provides;
Fig. 6 is the exemplary circuit structure chart of the frequency unit involved by multipath clock buffer that the embodiment of the present invention provides;
Fig. 7 is the exemplary construction schematic diagram of the multipath clock buffer shown in corresponding diagram 1;
Fig. 8 is the exemplary construction schematic diagram of the multipath clock buffer shown in corresponding diagram 2.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
Fig. 1 shows the structure of the multipath clock buffer that the embodiment of the present invention provides, and for convenience of explanation, illustrate only part related to the present invention, details are as follows:
The multipath clock buffer that the embodiment of the present invention provides comprises host buffer unit 100 and n clock division circuits.
The input incoming clock signal CLK_IN of host buffer unit 100, power supply termination DC power supply VDD, earth terminal ground connection VSS, host buffer unit 100 exports after clock signal clk _ IN is carried out buffered.
N clock division circuits (C
1~ C
n) comprise the 1st clock division circuits C1 to the n-th clock division circuits C
n, the 1st clock division circuits C
1to the n-th clock division circuits C
nclock signal clk _ IN, the 1st clock division circuits C is obtained from the output of host buffer unit 100
1export the 1st clock signal clk _ OUT1 with clock signal clk _ IN same frequency, the 2nd clock division circuits C
2to the n-th clock division circuits C
nexport after scaling down processing being carried out to clock signal clk _ IN according to the divide ratio preset respectively the 2nd clock signal clk _ OUT2 to the n-th clock signal CLK_OUTn, n be greater than 1 positive integer.
N clock division circuits (C
1~ C
n) in each clock division circuits include a switch element 200 and a buffer cell the 300,2nd clock division circuits C
2to the n-th clock division circuits C
nin each clock division circuits include frequency unit 400, the 2nd clock division circuits C
2comprise a frequency unit 400, n-th clock division circuits C
nthe quantity of the frequency unit comprised is 2 times of the quantity of the frequency unit that (n-1)th clock division circuits comprises.
The input of switch element 200 connects the output of host buffer unit 100, and the control end access switch controlling signal EN of switch element 200, switch element 200 controls the break-make of each clock division circuits according to switch controlling signal.
Frequency unit 400 is for carrying out scaling down processing to clock signal.
Buffer cell 300 is for carrying out buffered to clock signal and exporting.
At the 1st clock division circuits C
1in, the output of the input connecting valve unit 200 of buffer cell 300; At the 2nd clock division circuits C
2to the n-th clock division circuits C
nin, one or more frequency units 400 that each clock division circuits comprises are connected between the output of switch element 200 and buffer cell 300 input.
At the 2nd clock division circuits C
2in, the input of frequency unit 400 and output be the output of connecting valve unit 200 and the input of buffer cell 300 respectively.
At the n-th clock division circuits C
nin, from the output of switch element 200, multiple frequency unit 400 is sequentially connected in series the input to buffer cell 300.
In n clock division circuits, the control end access switch controlling signal of switch element 200, and the switch controlling signal that the switch element 200 in each clock division circuits accesses may be the same or different, the load number that whether switch controlling signal identical can drive according to specific needs and frequency needs type are determined.
At the 2nd clock division circuits C
2to the n-th clock division circuits C
nin, the power end of the power end of the switch element 200 in each clock division circuits, the power end of buffer cell 300 and frequency unit 400 all connects DC power supply VDD, the equal ground connection VSS of earth terminal of the earth terminal of switch element 200, the earth terminal of buffer cell 300 and frequency unit 400.
In addition, in an alternative embodiment of the invention, as shown in Figure 2, when n is not less than 3, at the 3rd clock division circuits C of multipath clock buffer
3to the n-th clock division circuits C
nin, for the clock division circuits including multiple frequency unit 400, when the quantity of multiple frequency unit 400 is m, and m is when being the positive integer being greater than 1, often also be serially connected with a switch element 200 between adjacent two frequency units 400, input and the output of this switch element 200 are connected the output of previous frequency unit 400 in every adjacent two frequency units 400 and the input of a rear frequency unit 400 respectively, and at the 1st frequency unit 400 in m-1 frequency unit 400, a switch element 200 is all connected with between the output of each frequency unit 400 and the input of buffer cell 300, input and the output of this switch element 200 are connected the output of described each frequency unit 400 and the input of buffer cell 300 respectively, power end and the earth terminal of this switch element 200 are connected DC power supply VDD and ground VSS respectively, the control end access switch controlling signal EN of this switch element.
Further, as shown in Figure 3, host buffer unit 100 comprises:
First PMOS P1, the second PMOS P2, the 3rd PMOS P3, resistance R1, the first NMOS tube N1, the second NMOS tube N2 and the 3rd NMOS tube N3;
The common contact of the grid of the grid of the first PMOS P1 and the first end of resistance R1 and the first NMOS tube N1 is as the input of host buffer unit 100, the common contact of the source electrode of the source electrode of the first PMOS P1 and the source electrode of the second PMOS P2 and the 3rd PMOS P3 is as the power end of host buffer unit 100, the drain electrode of the first PMOS P1 and the grid of the second PMOS P2, the drain electrode of the first NMOS tube N1 and the grid of the second NMOS tube N2 are connected to second end of resistance R1 altogether, the drain electrode of the second PMOS P2 is connected the common contact of the grid of the 3rd PMOS P3 and the grid of the 3rd NMOS tube N3 with the common contact of the drain electrode of the second NMOS tube N2, the common contact of the source electrode of the source electrode of the first NMOS tube N1 and the source electrode of the second NMOS tube N2 and the 3rd NMOS tube N3 is as the earth terminal of host buffer unit 100, the common contact of the drain electrode of the 3rd PMOS P3 and the drain electrode of the 3rd NMOS tube N3 is as the output of host buffer unit 100.
Further, as shown in Figure 4, switch element 200 comprises:
4th PMOS P4, the 4th NMOS tube N4, the 5th PMOS P5 and the 5th NMOS tube N5;
The common contact of the drain electrode of the 4th PMOS P4 and the drain electrode of the 4th NMOS tube N4 is as the input of switch element 200, the common contact of the source electrode of the 4th PMOS P4 and the source electrode of the 4th NMOS tube N4 is as the output of switch element 200, the grid of the 4th NMOS tube N4 is the control end of switch element 200, the grid of the 5th PMOS P5 and the grid of the 5th NMOS tube N5 are connected to the grid of the 4th NMOS tube N4 altogether, the source electrode of the 5th PMOS P5 is the power end of switch element 200, the drain electrode of the 5th PMOS P5 and the drain electrode of the 5th NMOS tube N5 are connected to the grid of the 4th PMOS P4 altogether, the source electrode of the 5th NMOS tube N5 is the power end of switch element 200.In switch element 200, when the 4th NMOS tube N4 grid received by switch controlling signal be high level time, 4th NMOS tube N4 conducting, and Simultaneous Switching control signal is carried out output low level after anti-phase process by the inverter be made up of the 5th PMOS P5 and the 5th NMOS tube N5 and is controlled the 4th PMOS P4 also conducting, so switch element 200 is conductings when switch controlling signal is high level, and turn off when switch controlling signal is low level.
Further, as shown in Figure 5, buffer cell 300 comprises:
6th PMOS P6, the 7th PMOS P7, the 6th NMOS tube N6 and the 7th NMOS tube N7;
The common contact of the grid of the 6th PMOS P6 and the grid of the 6th NMOS tube N6 is as the input of buffer cell 300, the common contact of the source electrode of the 6th PMOS P6 and the source electrode of the 7th PMOS P7 is as the power end of buffer cell 300, the drain electrode of the 6th PMOS P6 is connected the common contact of the grid of the 7th PMOS P7 and the grid of the 7th NMOS tube N7 with the common contact of the drain electrode of the 6th NMOS tube N6, the common contact of the source electrode of the 6th NMOS tube N6 and the source electrode of the 7th NMOS tube N7 is as the earth terminal of buffer cell 300, the common contact of the drain electrode of the 7th PMOS P7 and the drain electrode of the 7th NMOS tube N7 is as the output of buffer cell 300.
Further, a frequency unit 400 can carry out 1/2 scaling down processing to clock signal, and namely divide ratio is 1/2, and the frequency of the clock signal of frequency unit 400 is 1/2 of the frequency of input clock signal.As shown in Figure 6, frequency unit 400 comprises:
8th PMOS P8, the 9th PMOS P9, the 8th NMOS tube N8, the tenth PMOS P10, the 9th NMOS tube N9, the tenth NMOS tube N10, the 11 PMOS P11, the 11 NMOS tube N11, the 12 NMOS tube N12, the 12 PMOS P12, the 13 NMOS tube N13, the 13 PMOS P13 and the 14 NMOS tube N14;
The source electrode of the 8th PMOS P8 and the source electrode of the tenth PMOS P10, the source electrode of the 11 PMOS P11, the common contact of the source electrode of the 12 PMOS P12 and the source electrode of the 13 PMOS P13 is as the power end of frequency unit 400, the grid of the 8th PMOS P8 and the grid of the 8th NMOS tube N8, the drain electrode of the 11 PMOS P11, the drain electrode of the 11 NMOS tube N11, the grid of the 12 PMOS P12 and the grid of the 13 NMOS tube N13 connect altogether, the drain electrode of the 8th PMOS P8 connects the source electrode of the 9th PMOS P9, the grid of the 9th PMOS P9 and the grid of the tenth PMOS P10, the common contact of the grid of the tenth NMOS tube N10 and the grid of the 11 NMOS tube N11 is as the input of frequency unit 400, the drain electrode of the 9th PMOS P9 and the grid of the 9th NMOS tube N9 are connected to the drain electrode of the 8th NMOS tube N8 altogether, the drain electrode of the tenth PMOS P10 and the drain electrode of the 9th NMOS tube N9, the grid of the 11 PMOS P11 and the grid of the 12 NMOS tube N12 connect altogether, the source electrode of the 9th NMOS tube N9 connects the drain electrode of the tenth NMOS tube N10, the source electrode of the 11 NMOS tube N11 connects the drain electrode of the 12 NMOS tube N12, the drain electrode of the 12 PMOS P12 is connected the common contact of the grid of the 13 PMOS P13 and the grid of the 14 NMOS tube N14 with the common contact of the drain electrode of the 13 NMOS tube N13, the source electrode of the 8th NMOS tube N8 and the source electrode of the tenth NMOS tube N10, the source electrode of the 12 NMOS tube N12, the common contact of the source electrode of the 13 NMOS tube N13 and the source electrode of the 14 NMOS tube N14 is as the earth terminal of frequency unit 400, the common contact of the drain electrode of the 13 PMOS P13 and the drain electrode of the 14 NMOS tube N14 is as the output of frequency unit 400.
Below in conjunction with example, the multipath clock buffer shown in Fig. 1 is described further:
Suppose in multipath clock buffer, there are 3 clock division circuitss, i.e. n=3, the frequency of clock signal clk _ IN is 100Hz, as shown in Figure 7, and need to drive load 1, load 2 and load 3, needed for load 1, the frequency of clock signal is 100Hz, and needed for load 2, the frequency of clock signal is 50Hz, needed for load 3, the frequency of clock signal is 25Hz, then can by the 1st clock division circuits C
1, the 2nd clock division circuits C
2and the 3rd clock division circuits C
3export the 1st clock signal clk _ OUT1, the 2nd clock signal clk _ OUT2 and the 3rd clock signal clk _ OUT3 to load 1, load 2 and load 3 respectively, namely the frequency of CLK_OUT1, CLK_OUT2 and CLK_OUT3 is respectively 100Hz, 50Hz and 25Hz.When multipath clock buffer inputs is to clock signal CLK_IN, first carrying out buffered Hou Fen tri-tunnel by host buffer unit 100 couples of CLK_IN exports the 1st clock division circuits C to
1, the 2nd clock division circuits C
2and the 3rd clock division circuits C
3because these three clock division circuitss all need to drive load, so switch controlling signal EN1, EN2 and EN3 are high level, then the clock signal that exports of host buffer unit 100 exports CLK_OUT1 to load 1 after exporting buffer cell 300 after switch element 200 to and carrying out secondary buffer process; At the 2nd clock division circuits C
2in, then that the clock signal that host buffer unit 100 exports carries out 1/2 scaling down processing by exporting frequency unit 400 after switch element 200 to, to obtain the clock signal that frequency is 50Hz, this clock signal exports CLK_OUT2 to load 2 after carrying out secondary buffer process by buffer cell 300; At the 3rd clock division circuits C
3in, then 1/2 scaling down processing (namely divide ratio be 1/4) of clock signal by being carried out 2 times after switch element 200 continuously by 2 frequency units 400 that host buffer unit 100 exports, to obtain the clock signal that frequency is 25Hz, this clock signal exports CLK_OUT3 to load 3 after carrying out secondary buffer process by buffer cell 300 again.If need the load driven to only have load 1 and load 2, then switch controlling signal EN3 can be become low level to make the 3rd clock division circuits C
3in switch element 200 turn off, then the 3rd clock division circuits C
3export without clock signal.Therefore, multipath clock buffer can drive quantity and clock signal frequency demand according to the load of reality, and the one or more clock division circuits of gating is to reach the object driving one or more load neatly.
Owing to providing another implementation (namely shown in Fig. 2) of multipath clock buffer in another embodiment of the present invention, in conjunction with example, the multipath clock buffer shown in Fig. 2 is described further again then: suppose in multipath clock buffer, there are 3 clock division circuitss, i.e. n=3, the frequency of clock signal clk _ IN is 100Hz, as shown in Figure 8, and need load 1, load 2 and load 3 drive, needed for load 1, the frequency of clock signal is 100Hz, needed for load 2, the frequency of clock signal is 50Hz, needed for load 3, the frequency of clock signal is 25Hz, then can by the 1st clock division circuits C
1, the 2nd clock division circuits C
2and the 3rd clock division circuits C
3export the 1st clock signal clk _ OUT1, the 2nd clock signal clk _ OUT2 and the 3rd clock signal clk _ OUT3 to load 1, load 2 and load 3 respectively, namely the frequency of CLK_OUT1, CLK_OUT2 and CLK_OUT3 is respectively 100Hz, 50Hz and 25Hz.When multipath clock buffer inputs is to clock signal CLK_IN, first carrying out buffered Hou Fen tri-tunnel by host buffer unit 100 couples of CLK_IN exports the 1st clock division circuits C to
1, the 2nd clock division circuits C
2and the 3rd clock division circuits C
3, because these three clock division circuitss all need to drive load, so switch controlling signal EN1, EN2, EN3 and EN3' are high level, switch controlling signal EN3'' is low level, then at the 1st clock division circuits C
1in, the clock signal that host buffer unit 100 exports exports CLK_OUT1 to load 1 after exporting buffer cell 300 after switch element 200 to and carrying out secondary buffer process; At the 2nd clock division circuits C
2in, then that the clock signal that host buffer unit 100 exports carries out 1/2 scaling down processing by exporting frequency unit 400 after switch element 200 to, to obtain the clock signal that frequency is 50Hz, this clock signal exports CLK_OUT2 to load 2 after carrying out secondary buffer process by buffer cell 300; At the 3rd clock division circuits C
3in (the quantity m=2 of frequency unit), then the clock signal that exports of host buffer unit 100 by after carrying out 1/2 scaling down processing by frequency unit 401 after switch element 201, by carrying out 1/2 scaling down processing again by frequency unit 402 after switch element 202, to obtain the clock signal that frequency is 25Hz, this clock signal exports CLK_OUT3 to load 3 after carrying out secondary buffer process by buffer cell 300 again, and now switch element 203 turns off.
In addition, if the frequency of clock signal is 50Hz needed for load 2 and load 3, and need to drive load 1, load 2 and load 3 simultaneously, on the basis of above-mentioned operation principle, switch controlling signal EN3' is needed to become low level, and switch controlling signal EN3'' becomes high level, the 3rd clock division circuits C so just can be made
3the frequency of the 3rd the clock signal clk _ OUT3 exported is 50Hz.
If only need load 1 and the load 2 of driving, then switch controlling signal EN3 can be become low level to make the 3rd clock division circuits C
3in switch element 201 turn off, then the 3rd clock division circuits C
3export without clock signal.
In sum, multipath clock buffer shown in Fig. 2 can drive quantity and clock signal frequency demand according to the load of reality equally, the one or more clock division circuits of gating is to reach the object driving one or more load neatly, and can export the identical clock signal of multiple frequency with the multiple equally loaded demand of satisfied driving simultaneously.
The multipath clock buffer that the embodiment of the present invention provides comprises host buffer unit and n clock division circuits, and one of them clock division circuits exports after only carrying out buffered to clock signal, the frequency unit that all the other n-1 clock division circuits is comprised by it carries out scaling down processing according to different divide ratios to clock signal respectively, and each clock division circuits in n clock division circuits all includes switch element and buffer cell, switch element can control the break-make of each clock division circuits according to switch controlling signal, thus enable multipath clock buffer drive multiple load simultaneously, and can according to the one or more clock division circuits of switch controlling signal gating, and scaling down processing is carried out to clock signal, one or more clock frequency is required that different loads provides clock signal to be embodied as, solve existing clock buffer to exist cannot drive multiple load simultaneously, and the problem of scaling down processing and the output of variable connector gating cannot be carried out to clock signal.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. a multipath clock buffer, is characterized in that, described multipath clock buffer comprises host buffer unit and n clock division circuits;
The input incoming clock signal of described host buffer unit, power supply termination DC power supply, earth terminal ground connection, described host buffer unit exports after described clock signal is carried out buffered;
A described n clock division circuits comprises the 1st clock division circuits to the n-th clock division circuits, described 1st clock division circuits to described n-th clock division circuits obtains described clock signal from the output of described host buffer unit, described 1st clock division circuits exports the 1st clock signal with described clock signal same frequency, 2nd clock division circuits exports the 2nd clock signal to the n-th clock signal after described n-th clock division circuits carries out scaling down processing according to the divide ratio preset to described clock signal respectively, n be greater than 1 positive integer,
Each clock division circuits in a described n clock division circuits includes a switch element and a buffer cell, each clock division circuits in described 2nd clock division circuits to described n-th clock division circuits includes frequency unit, described 2nd clock division circuits comprises a frequency unit, and the quantity of the frequency unit that the n-th clock division circuits comprises is 2 times of the quantity of the frequency unit that (n-1)th clock division circuits comprises;
The input of described switch element connects the output of described host buffer unit, the control end access switch controlling signal of described switch element, and described switch element controls the break-make of each clock division circuits according to described switch controlling signal;
Described frequency unit is used for carrying out scaling down processing to clock signal;
Described buffer cell is used for carrying out buffered to clock signal and exporting;
In described 1st clock division circuits, the output of the input connecting valve unit of buffer cell; In described 2nd clock division circuits to described n-th clock division circuits, one or more frequency units that each clock division circuits comprises are connected between the output of switch element and the input of buffer cell;
In described 2nd clock division circuits, the input of frequency unit and output be the output of connecting valve unit and the input of buffer cell respectively;
In described n-th clock division circuits, from the output of switch element, multiple frequency unit is sequentially connected in series the input to buffer cell;
In described 2nd clock division circuits to described n-th clock division circuits, the power end of the power end of the switch element in each clock division circuits, the power end of buffer cell and frequency unit all connects described DC power supply, the equal ground connection of earth terminal of the earth terminal of switch element, the earth terminal of buffer cell and frequency unit.
2. multipath clock buffer as claimed in claim 1, it is characterized in that, when n is not less than 3, in described 3rd clock division circuits to described n-th clock division circuits, for the clock division circuits including multiple frequency unit, when the quantity of multiple frequency unit is m, and m is when being the positive integer being greater than 1, often also be serially connected with a switch element between adjacent two frequency units, input and the output of this switch element are connected the output of previous frequency unit in every adjacent two frequency units and the input of a rear frequency unit respectively, and at the 1st frequency unit in m-1 frequency unit, a switch element is all connected with between the output of each frequency unit and the input of buffer cell, input and the output of this switch element are connected the described output of each frequency unit and the input of buffer cell respectively, power end and the earth terminal of this switch element are connected described DC power supply and ground respectively, the control end access switch controlling signal of this switch element.
3. multipath clock buffer as claimed in claim 1 or 2, it is characterized in that, described host buffer unit comprises:
First PMOS, the second PMOS, the 3rd PMOS, resistance R1, the first NMOS tube, the second NMOS tube and the 3rd NMOS tube;
The common contact of the grid of the grid of described first PMOS and the first end of described resistance R1 and described first NMOS tube is as the input of described host buffer unit, the common contact of the source electrode of the source electrode of described first PMOS and the source electrode of described second PMOS and described 3rd PMOS is as the power end of described host buffer unit, the drain electrode of described first PMOS and the grid of described second PMOS, the drain electrode of described first NMOS tube and the grid of described second NMOS tube are connected to second end of described resistance R1 altogether, the drain electrode of described second PMOS is connected the common contact of the grid of described 3rd PMOS and the grid of described 3rd NMOS tube with the common contact of the drain electrode of described second NMOS tube, the common contact of the source electrode of the source electrode of described first NMOS tube and the source electrode of described second NMOS tube and described 3rd NMOS tube is as the earth terminal of described host buffer unit, the common contact of the drain electrode of described 3rd PMOS and the drain electrode of described 3rd NMOS tube is as the output of described host buffer unit.
4. multipath clock buffer as claimed in claim 1 or 2, it is characterized in that, described switch element comprises:
4th PMOS, the 4th NMOS tube, the 5th PMOS and the 5th NMOS tube;
The common contact of the drain electrode of described 4th PMOS and the drain electrode of described 4th NMOS tube is as the input of described switch element, the common contact of the source electrode of described 4th PMOS and the source electrode of described 4th NMOS tube is as the output of described switch element, the grid of described 4th NMOS tube is the control end of described switch element, the grid of described 5th PMOS and the grid of described 5th NMOS tube are connected to the grid of described 4th NMOS tube altogether, the source electrode of described 5th PMOS is the power end of described switch element, the drain electrode of described 5th PMOS and the drain electrode of described 5th NMOS tube are connected to the grid of described 4th PMOS altogether, the source electrode of described 5th NMOS tube is the power end of described switch element.
5. multipath clock buffer as claimed in claim 1 or 2, it is characterized in that, described buffer cell comprises:
6th PMOS, the 7th PMOS, the 6th NMOS tube and the 7th NMOS tube;
The common contact of the grid of described 6th PMOS and the grid of described 6th NMOS tube is as the input of described buffer cell, the common contact of the source electrode of described 6th PMOS and the source electrode of described 7th PMOS is as the power end of described buffer cell, the drain electrode of described 6th PMOS is connected the common contact of the grid of described 7th PMOS and the grid of described 7th NMOS tube with the common contact of the drain electrode of described 6th NMOS tube, the common contact of the source electrode of described 6th NMOS tube and the source electrode of described 7th NMOS tube is as the earth terminal of described buffer cell, the common contact of the drain electrode of described 7th PMOS and the drain electrode of described 7th NMOS tube is as the output of described buffer cell.
6. multipath clock buffer as claimed in claim 1 or 2, it is characterized in that, a described frequency unit carries out 1/2 scaling down processing to clock signal, and the divide ratio of a described frequency unit is 1/2;
Described frequency unit comprises:
8th PMOS, the 9th PMOS, the 8th NMOS tube, the tenth PMOS, the 9th NMOS tube, the tenth NMOS tube, the 11 PMOS, the 11 NMOS tube, the 12 NMOS tube, the 12 PMOS, the 13 NMOS tube, the 13 PMOS and the 14 NMOS tube;
The source electrode of described 8th PMOS and the source electrode of described tenth PMOS, the source electrode of described 11 PMOS, the common contact of the source electrode of described 12 PMOS and the source electrode of described 13 PMOS is as the power end of described frequency unit, the grid of described 8th PMOS and the grid of described 8th NMOS tube, the drain electrode of described 11 PMOS, the drain electrode of described 11 NMOS tube, the grid of described 12 PMOS and the grid of described 13 NMOS tube connect altogether, the drain electrode of described 8th PMOS connects the source electrode of described 9th PMOS, the grid of described 9th PMOS and the grid of described tenth PMOS, the common contact of the grid of described tenth NMOS tube and the grid of described 11 NMOS tube is as the input of described frequency unit, the drain electrode of described 9th PMOS and the grid of described 9th NMOS tube are connected to the drain electrode of described 8th NMOS tube altogether, the drain electrode of described tenth PMOS and the drain electrode of described 9th NMOS tube, the grid of described 11 PMOS and the grid of described 12 NMOS tube connect altogether, the source electrode of described 9th NMOS tube connects the drain electrode of described tenth NMOS tube, the source electrode of described 11 NMOS tube connects the drain electrode of described 12 NMOS tube, the drain electrode of described 12 PMOS is connected the common contact of the grid of described 13 PMOS and the grid of described 14 NMOS tube with the common contact of the drain electrode of described 13 NMOS tube, the source electrode of described 8th NMOS tube and the source electrode of described tenth NMOS tube, the source electrode of described 12 NMOS tube, the common contact of the source electrode of described 13 NMOS tube and the source electrode of described 14 NMOS tube is as the earth terminal of described frequency unit, the common contact of the drain electrode of described 13 PMOS and the drain electrode of described 14 NMOS tube is as the output of described frequency unit.
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| CN201310495994.4A CN104579318B (en) | 2013-10-21 | 2013-10-21 | A kind of multipath clock buffer |
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| CN114489220A (en) * | 2022-01-04 | 2022-05-13 | 电子科技大学 | Low-power-consumption over-temperature protection circuit without operational amplifier and reference |
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| CN104579318B (en) | 2018-05-29 |
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