CN1945671A - Display device - Google Patents

Abstract

The present invention provided a display device, using the current drive control circuit to prevent the alteration of the a-Si TFTs vale value voltage of the gate driver. A display device includes a gate driver for driving pixels (PX), a drive control circuit for outputting a predetermined control signal to the gate driver, and a frequency division circuit. The pixels, the gate driver, and the frequency division circuit are formed using amorphous silicon thin film transistors (a-Si TFTs) formed on an insulating substrate. The control signal output from the drive control circuit includes a start signal for a start of a frame period of an image signal, and the frequency division circuit generates a frequency division signal whose period corresponds to a frequency which is obtained by dividing a frequency of the start signal.

Description

Display device

Technical field

The present invention relates to possess the display device of the gate drivers that constitutes by thin film transistor (TFT) (TFT).

Background technology

Display device such as LCD or OLED display possesses and is rectangular gate line (sweep trace) that is provided in pixel on the dielectric substrate such as glass, is provided with by this each pixel column (pixel line) and the gate drivers of selecting these gate lines to drive successively.Gate drivers can be made of shift register, and still, for simplified manufacturing technique, the shift register that gate drivers uses preferably only is made of the field effect transistor of same conduction type.Therefore, various shift registers that are made of N channel-type or P channel type field effect transistors and the scheme that the display device of this shift register is housed have been proposed.

In addition, use the display device easy large tracts of landization of amorphous silicon film transistor (a-Si TFT), and the production efficiency height, be widely used in the screen of notebook type PC for example or the large screen display device etc. as the field effect transistor that constitutes gate drivers.

We know that a-Si TFT the big phenomenon of threshold voltage shift can occur when grid continues (direct current) biasing.This phenomenon is the main cause of delaying work that causes the gate drivers that uses a-Si TFT, becomes problem.In addition, we also know, are not only a-Si TFT, and also there is same problem in organic tft.

As its countermeasure, a kind of scheme of gate driver circuit has been proposed, be set up in parallel the a-Si TFT of 2 outputs drop-down (pull down) usefulness in the output stage of gate drivers, by making both by every frame alternation/stop, make a grid of exporting the a-Si TFT of drop-down usefulness not continue biasing (for example, non-patent literature 1).

" Highly Stable IntegratedGate Driver Circuit using a-Si TFT with Dual Pull-down Structure " such as [non-patent literature 1] Soon Young Yoon SID05 DIGEST P.348

But, do not export such control signal (switching signal) that is used for making 2 drop-down work of output/stop and switch with a-Si TFT by every frame from the general driving control circuit LSI that uses in the past always.Therefore, in order to adopt the technology of non-patent literature 1, need newly be provided with the circuit that generates switching signal Drive and Control Circuit.But, when such circuit is set, become the different special requirement of a kind of and existing Drive and Control Circuit, make the manufacturing cost of Drive and Control Circuit rise the rising that brings the display device cost thus.

Summary of the invention

The present invention makes in order to solve above problem, and its purpose is to provide a kind of display device, and it uses general Drive and Control Circuit, can prevent the change of threshold voltage of the TFT of gate drivers.

Display device of the present invention possesses: dielectric substrate, be provided in a plurality of pixels on the above-mentioned dielectric substrate, drive the gate drivers of above-mentioned pixel, to the Drive and Control Circuit of the control signal of above-mentioned gate drivers output regulation with signal frequency is carried out the frequency dividing circuit of frequency division, wherein, above-mentioned pixel, above-mentioned gate drivers and above-mentioned frequency dividing circuit use the thin film transistor (TFT) (TFT) that forms on above-mentioned dielectric substrate to constitute, the above-mentioned control signal of above-mentioned Drive and Control Circuit output comprises the corresponding start signal of beginning with image duration of picture signal, and above-mentioned frequency dividing circuit generates the fractional frequency signal that has the cycle behind the above-mentioned start signal frequency division.

According to display device of the present invention, the TFT of 2 drop-down usefulness of output that can possess gate drivers according to fractional frequency signal carries out the switching by every frame.Fractional frequency signal is the signal that obtains behind 2 start signal frequency divisions with general driving control circuit output.That is, can use the general driving control circuit that gate drivers is worked alternately to switch 2 drop-down modes with TFT of output by every frame.Therefore, can suppress the rising of display device cost, what can prevent simultaneously that change by the threshold voltage of the TFT of gate drivers from causing delays work.In addition,, use the TFT formation that on dielectric substrate, forms because frequency dividing circuit is identical with pixel and gate drivers, so, the complicated of the manufacturing process brought along with in display device, frequency dividing circuit being set can be suppressed.

Description of drawings

Fig. 1 is the block scheme that the summary of the existing display device of expression constitutes.

Fig. 2 is the circuit diagram of structure example of the pixel of expression display device.

Fig. 3 is the timing diagram of the work of the existing gate drivers of expression (odd gates driver and even number gate drivers).

Fig. 4 is the block scheme that the summary of expression display device of the present invention constitutes.

Fig. 5 is the circuit diagram of the basic comprising of expression frequency dividing circuit of the present invention.

Fig. 6 is the timing diagram of the groundwork of expression frequency dividing circuit of the present invention.

Fig. 7 is the circuit diagram of the frequency dividing circuit of embodiment 1.

Fig. 8 is the timing diagram of work of the frequency dividing circuit of expression embodiment 1.

Fig. 9 is the timing diagram of work of the frequency dividing circuit of expression embodiment 1.

Figure 10 is the block scheme of the variation of expression display device of the present invention.

Figure 11 is the timing diagram of work of the variation of expression display device of the present invention.

Figure 12 is the figure that the circuit of the frequency dividing circuit of expression embodiment 2 constitutes.

Figure 13 is the timing diagram of work of the frequency dividing circuit of expression embodiment 2.

Figure 14 is the figure that the circuit of the frequency dividing circuit of expression embodiment 3 constitutes.

Figure 15 is the figure that the circuit of the frequency dividing circuit of expression embodiment 4 constitutes.

Figure 16 is the circuit diagram of existing single-place shift register.

Figure 17 is the figure of the formation of the existing gate drivers of expression.

Figure 18 is the timing diagram of the work of the existing gate drivers of expression.

Figure 19 is the circuit diagram of the single-place shift register of expression embodiment 5.

Figure 20 is the block scheme that the summary of the display device of expression embodiment 6 constitutes.

Figure 21 is the timing diagram of work of the frequency dividing circuit of expression embodiment 6.

Figure 22 is the figure that the circuit of the frequency dividing circuit of expression embodiment 7 constitutes.

Figure 23 is the timing diagram of work of the frequency dividing circuit of expression embodiment 7.

Figure 24 is the block scheme that the summary of the display device of expression embodiment 8 constitutes.

Figure 25 is the timing diagram of work of the frequency dividing circuit of expression embodiment 8.

Embodiment

Below, with reference to the description of drawings embodiments of the present invention.Have again, become tediously long, in each figure, the key element with same or suitable function is added prosign for fear of repeat specification.

＜embodiment 1 〉

Below, the specific embodiment of the present invention is described, in order to understand the present invention easily, at first, existing general driving control circuit and gate drivers are illustrated.Fig. 1 is the block scheme of the structure example of the existing display device of expression.

In the display device of Fig. 1, the pixel PX that the a-Si TFT that use forms on dielectric substrate such as glass constitutes is rectangular and sets.As pixel PX, for example can enumerate the pixel of using liquid crystal cell or use the pixel etc. of organic EL electroluminescent cells such as (electroluminescences).

Fig. 2 (a) has been to use the structure example of the liquid crystal pixel of a-Si TFT.The grid of active component 121 (a-Si TFT) is connected with gate line, and the drain electrode of active component 121 is connected with data line.In addition, keep electric capacity 122 to be connected with the source electrode of liquid crystal cell 123 with active component 121.Keep electric capacity 122 to be connected with public electrode with liquid crystal cell 123 other end separately.Therefore, when gate line activates (H (height) level), active component 121 conductings, the data of data line at this moment (current potential) remain on and keep in the electric capacity 122.The orientation of the liquid crystal in the liquid crystal cell 123 and the data that remain in this maintenance electric capacity 122 are to change, and the display brightness of this pixel changes.

In addition, Fig. 2 (b) has been to use the structure example of the organic electroluminescence pixel of a-Si TFT.The grid of active component 125 (a-Si TFT) is connected with gate line, and the drain electrode of active component 125 is connected with data line.Keep electric capacity 126 to be connected with the source electrode of active component 125 with the grid that drives with TFT127 (a-Si TFT).EL element 128 is connected with the drain electrode that drives with TFT127.Keep the other end of electric capacity 126 to be connected with the power lead of regulation with the source electrode that drives with TFT127, the other end of EL element 128 is connected with negative supply.Therefore, when gate line activates (H level), active component 125 conductings, the data of data line at this moment (current potential) remain on and keep in the electric capacity 126.And, drive with the corresponding conduction and cut-off that switches to of TFT127 with the data that remain in this maintenance electric capacity 126, when driving with the TFT127 conducting, electric current flows into EL element 128, and this pixel is luminous.

Each pixel PX is driven by the gate drivers 101,102 and the Drive and Control Circuit 110 of following explanation.In conventional example shown in Figure 1, in the both sides of the matrix (picture element matrix) of pixel PX, set with this pixel PX 2 gate drivers 101,102 that the a-Si TFT that forms on the dielectric substrate constitutes that coexist mutually.The gate drivers 101 in picture element matrix left side be drive the gate lines G 1 corresponding, G3, G5 with the odd number of pixels row ... driver, the gate drivers 102 on right side be drive the gate lines G 2 corresponding, G4, G6 with the even number pixel column ... driver.By this mode, can tackle the situation of the pitch smaller on the direction of scanning of pixel PX, and can realize that the densification of pixel PX is the high resolving powerization of picture.In the following description, gate drivers 101 is called " odd gates driver 101 ", gate drivers 102 is called " even number gate drivers 102 ".

The general LSI that Drive and Control Circuit 110 is to use monocrystalline silicon to form.Drive and Control Circuit 110 by to data line (DR1, DG1, DB1, DR2, DG2, DB2 ...) output write pixel PX video data source electrode drive circuit, driving grid driver 101,102 needed drive control signal (start signal and clock signal) generative circuit and generate the formations such as power circuit of supply voltage.

Comprise in the drive control signal of Drive and Control Circuit 110 output: the initial pulse corresponding and stipulate the clock signal of its work timing in gate drivers 101,102 with the beginning of 1 frame of picture signal.When driving picture element matrixs with 2 gate drivers 101,102, Drive and Control Circuit 110 is to 101 outputs of odd gates driver: make start signal STYO that the scanning of odd gates line begins, regulation odd gates driver 101 work timing clock signal clk YO and with the clock signal/CLKYO of its counter-rotating.

In addition, Drive and Control Circuit 110 is exported to even number gate drivers 102: the clock signal clk YE of the work timing of the start signal STYE of even number gate line, regulation even number gate drivers 102 and the clock signal/CLKYE anti-phase with it.

Fig. 3 illustrates the waveform of these drive control signal.As shown in Figure 3, clock signal clk YO ,/CLKYO is the periodic pulse signal of 4 horizontal period (4H) of display device, both phase places 2 horizontal period (2H) that stagger mutually.Equally, clock signal clk YE ,/CLKYE is the periodic pulse signal of 4 horizontal period (4H) of display device, both phase places 2 horizontal period (2H) that stagger mutually.In addition, phase shifting 1 horizontal period (1H) of clock signal clk YO and clock signal clk YE.That is, these 4 clock signal clk YO, CLKYE ,/CLKYO ,/CLKYE constitutes 4 phase clocks that phase place respectively differs 1 horizontal period.

Drive and Control Circuit 110 is being exported start signal STYO with the corresponding moment t0 of the beginning of image duration to odd gates driver 101.Then, at the moment t1 of 1 horizontal period (1H) that lags behind than moment t0, to odd gates driver 101 input clock signal CLKYO, and then, at the moment t3 input clock signal/CLKYO of 2 horizontal period (2H) that lag behind than moment t1.

Constitute the shift register of odd gates driver 101 and clock signal clk YO ,/CLKYO synchronously make start signal STYO successively to odd number bar gate lines G 1, G3, G5 ... displacement.Thus, as shown in Figure 3, odd number bar gate lines G 1, G3, G5 ... with clock signal clk YO ,/synchronously per 2 horizontal period of CLKYO activate (H level) successively.

On the other hand, the moment t1 in 1 horizontal period (1H) that lags behind than moment t0 imports start signal STYE to even number gate drivers 102.Then, at the moment t2 input clock signal CLKYE of 1 horizontal period (1H) that lags behind than moment t1, and at the moment t4 input clock signal/CLKYE of 2 horizontal period (2H) that lag behind than moment t2.

Constitute the shift register of even number gate drivers 102 and clock signal clk YE ,/CLKYE synchronously make start signal STYE successively to even number bar gate lines G 2, G4, G6 ... displacement.Thus, as shown in Figure 3, even number bar gate lines G 2, G4, G6 ... with clock signal clk YE ,/synchronously per 2 horizontal period of CLKYE activate (H level) successively.

The clock signal clk YO of input odd gates driver 101 ,/the clock signal clk YE of CLKYO and input even number gate drivers 102 ,/phase place of CLKYE 1 horizontal period that staggers mutually, so odd number gate line and even number gate line alternately activate.

The result who more than works is, as shown in Figure 3, all gate lines G 1, G2, G3, G4 ... according to this order, selected by per 1 horizontal period.

Have again, when the density of pixel PX is low, also have gate drivers only to be configured in a side of picture element matrix, drive the situation (omit and illustrate) of picture element matrix with this 1 gate drivers here.At this moment, needn't distinguish the gate line of even number and odd number, so Drive and Control Circuit is exported 2 phase clock signals and exported 1 start signal in per 1 image duration, 1 gate drivers is selected all gate lines successively according to these signals.

In addition, general driving control circuit (LSI) constitutes any situation that can tackle 1 and 2 gate drivers, and can export the drive control signal under the both of these case.That is, such general driving control circuit constitutes and can export the 4 phase clock signals that are used for driving 2 gate drivers and 2 start signal and being used for 2 phase clocks that drive 1 gate drivers and 1 start signal mutually mutually.

Below, display device of the present invention is described.Fig. 4 is the block scheme that the summary of expression display device of the present invention constitutes.

As shown in the drawing, in the present embodiment, be formed at the both sides of the matrix (picture element matrix) of the pixel PX that the a-SiTFT on the dielectric substrate constitutes in use, set use and be formed at 2 gate drivers 11,12 that the a-Si TFT on the dielectric substrate constitutes equally.The odd gates driver 11 in picture element matrix left side be drive the gate lines G 1 corresponding, G3, G5 with the odd number of pixels row ... driver, the even number gate drivers 12 on right side be drive the gate lines G 2 corresponding, G4, G6 with the even number pixel column ... driver.

The groundwork of gate drivers 11,12 is the same with existing gate drivers shown in Figure 1 101,102.But for the drift of the threshold voltage that prevents a-Si TFT, the gate drivers 11,12 of present embodiment adopts the modes (for example, the mode of above-mentioned non-patent literature 1) of alternately switching the a-SiTFT of 2 drop-down usefulness of output by every frame.That is,, need be used for switching 2 control signals (switching signal) of exporting the a-Si TFT of drop-down usefulness in order to make this gate drivers 11,12 operate as normal.

In addition, Drive and Control Circuit 110 shown in Figure 4 is the same with circuit shown in Figure 1, the general LSI that is to use monocrystalline silicon to form.That is, as drive control signal, Drive and Control Circuit 110 to the odd gates driver 101 above-mentioned start signal STYO of output and clock signal clk YO ,/CLKYO.In addition, as drive control signal, to the even number gate drivers 102 above-mentioned start signal STYE of output and clock signal clk YE ,/CLKYE.

The display device of present embodiment has utilizes that the a-Si TFT be formed on the dielectric substrate constitutes, as the frequency of signal to be carried out frequency division frequency dividing circuit 20.To frequency dividing circuit 20 input 2 start signal STYO, STYE shown in Figure 4 and 2 clock signal clk YE ,/CLKYO.This frequency dividing circuit 20 is driven by these 4 signals, and output has 2 times to (after promptly frequency being carried out 1/2 frequency division) the fractional frequency signal VFR in cycle in cycle of start signal STYO, STYE and anti-phase fractional frequency signal/VFR thereof.

Start signal STYO, STYE are the signals regularly corresponding with the beginning of each image duration of picture signal, so, the fractional frequency signal VFR of its 2 doubling time ,/VFR becomes the signal that reverses per 1 image duration of picture signal.This fractional frequency signal VFR ,/VFR together imported gate drivers 11,12, and therefore, can be used as the switching signal of the a-Si TFT that is used to switch 2 drop-down usefulness of output and use.

According to present embodiment, use existing general driving control circuit 110, can obtain being used for switching the drop-down switching signal of each 2 outputs of gate drivers 11,12 with a-Si TFT.That is, use general Drive and Control Circuit, can obtain sup.G driver 11,12 a-SiTFT threshold voltage change, prevent the effect of delaying work.

Secondly, the frequency dividing circuit 20 to present embodiment describes.Fig. 5 is the circuit diagram of the basic comprising of expression frequency dividing circuit 20, and Fig. 6 is the timing diagram of its work of expression.At first, according to these figure the principle of work of frequency dividing circuit 20 is described.

As shown in Figure 5, frequency dividing circuit 20 constitutes by switch SW 1, SW2, transducer (inverter) IV1, IV2, IV3 (the 1st, the 2nd and the 3rd transducer) with as maintenance capacitor C H1, the CH2 of holding circuit.Keep capacitor C H1 to be connected, keep capacitor C H2 to be connected with the input node NB of transducer IV2 with the input node NA of transducer IV1.Have, keeping capacitor C H1, CH2 also can be stray capacitance again.

In addition, in Fig. 5, input signal IN1, IN2 are the signals that the mutual cycle equates, phase place is different.Switch SW 1, SW2 respectively input signal IN1, IN2 be H (height) level during, working is conducting.

With reference to Fig. 6, be located at t0 constantly, node NE is the H level.At this moment, if become the H level at moment t0 input signal IN1, switch SW 1 conducting, then node NA becomes the H level, and the output node NB of transducer IV1 becomes L (low) level.That is, transducer IV1 and input signal IN1 synchronously make the output counter-rotating of transducer IV3.Subsequently, when when moment t1 input signal IN1 gets back to the L level, switch SW 1 is ended, but because of keeping the effect of capacitor C H1, node NA remains on the H level, so node NB remains on the L level.

Then, when when moment t2 input signal IN2 becomes the H level, switch SW 2 conductings, the level of node NC becomes the L level identical with node NB.As a result, the output node ND of transducer IV2 becomes the H level, and the output node NE of transducer IV3 becomes the L level.That is, transducer IV2 and input signal IN2 synchronously make the output counter-rotating of transducer IV1.Subsequently, when when moment t3 input signal IN2 gets back to the L level, switch SW 2 is ended, but because of keeping the effect of capacitor C H2, node NC remains on the L level, so node ND remains on the H level, node NE remains on the L level.

Thereafter, the level relationship of each node is opposite, carries out the same work with above-mentioned moment t0～t3.That is, when when moment t4 input signal IN1 becomes H level, switch SW 1 conducting again, node NA becomes the L level, and node NB becomes the H level.Then, even get back to the L level at moment t5 input signal IN1, switch SW 1 is ended, keep the L level of node NA because of keeping capacitor C H1, so node NB also remains on the H level.

Then, when when moment t6 input signal IN2 becomes the H level, switch SW 2 conductings, node NC becomes the H level, and node ND becomes the L level, and node NE becomes the H level.Then, even get back to the L level at moment t7 input signal IN2, switch SW 2 is ended, make node NC remain on the H level because of keeping capacitor C H2, so node ND, NE also keep L level and H level respectively.

After the t7, repeat and the identical work of above-mentioned moment t0～t7 constantly.

Like this, by the circuit of Fig. 5, when the level of input signal IN1 became the H level, the level of node NA, NB is counter-rotating respectively just, and when the level of input signal IN2 became the H level, the level of node ND, NE is counter-rotating respectively just.That is the signal that, on node NA～NE, occurs 2 doubling times of input signal IN1, IN2 respectively.Its phase place of signal that particularly appears on node NA, the NB is consistent with input signal IN1, and its phase place of signal that appears on node NC, the NE is consistent with input signal IN2.

Fig. 7 is the figure of the example that constitutes of the physical circuit of expression frequency dividing circuit 20.As shown in the drawing, frequency dividing circuit 20 uses the a-Si TFT of single conduction type (being the n channel-type) to constitute here.

A-Si TFT (hereinafter referred to as " the transistor ") function separately that constitutes frequency dividing circuit 20 is described.Transistor Q1 is corresponding with the switch SW 1 of Fig. 5, according to the start signal STYO (the 1st start signal) from Drive and Control Circuit 110 input, sends the level of node N8 to node N1.

Transistor Q2～Q6 constitutes and latchs transducer 21, this latch transducer 21 comprise make node N1 the level counter-rotating again to the transducer of node N2 output with keep the latch of the level of node N1, N2.In more detail, transistor Q5, Q6 play transducer, and transistor Q2～Q5 plays latch.The transducer that is made of transistor Q5, Q6 is corresponding with the transducer IV1 (the 1st transducer) of Fig. 5, and the latch that is made of transistor Q2～Q6 plays the identical holding circuit of maintenance capacitor C H1 with Fig. 5.In the frequency dividing circuit 20 of Fig. 7, holding circuit is not capacity cell but latch, even this is also can keep for the work period of frequency dividing circuit 20 is long and the level of stable node N1, N2.Transistor Q7, Q8 are located at the output stage of the transducer that is formed by transistor Q5, Q6, are configured to improve the impact damper 22 of the driving force (flowing through the ability of electric current) of this transducer.

Transistor Q9 is corresponding with the switch SW 2 of Fig. 5, according to the start signal STYE (the 2nd start signal) from Drive and Control Circuit 110, sends the level of node N3 to node N4.

Transistor Q10～Q13 constitutes and latchs transducer 23, this latch transducer 23 comprise make node N4 the level counter-rotating again to the transducer of node N5 output with keep the latch of the level of node N4, N5.In more detail, transistor Q12, Q13 play transducer, and transistor Q10～Q13 plays latch.Transducer that is made of transistor Q12, Q13 and transducer IV2 (the 2nd transducer) correspondence of Fig. 5, the latch that is made of transistor Q10～Q13 is the same with the maintenance capacitor C H2 of Fig. 5, plays holding circuit.Here, holding circuit is not capacity cell but latch, even this is also can keep for the work period of frequency dividing circuit 20 is long and the level of stable node N4, N5.In addition, transistor Q14, Q15 constitute the impact damper 24 of the output stage that is located at the transducer that is formed by transistor Q12, Q13.This impact damper 24 plays the driving force of the transducer that raising is made of transistor Q12, Q13.

On the other hand, transistor Q22, Q23 also constitute the impact damper 28 of the output stage that is located at the transducer that is formed by transistor Q12, Q13, be used for improving the driving force of this transducer, but, also play the effect of output buffer especially, be used for exporting the fractional frequency signal VFR (below, impact damper 28 is called " output buffer 28 ") of self frequency-dividing circuit 20.

Transistor Q16, Q17 play make node N6 level counter-rotating again to the effect of the transducer 25 of node N7 output.Transducer 25 works as the transducer IV3 (the 3rd transducer) of Fig. 5.In addition, transistor Q18, Q19 constitute impact damper 26, and the output stage that is located at transducer 25 is to improve its driving force.

On the other hand, transistor Q20, Q21 also constitute impact damper 27, the output stage that is located at transducer 25 is to improve its driving force, but, also play output buffer especially, be used for exporting the fractional frequency signal/VFR (below, impact damper 27 is called " output buffer 27 ") of self frequency-dividing circuit 20.

Be connected the input terminal of clock signal/CLKYO and the capacity cell C1 between the node N7 (grid of transistor Q18, Q20), be used for accepting clock signal/CLKYO, and make grid (output node of the transducer 25) boost in voltage of transistor Q18, Q20 respectively.Equally, be connected the input terminal of clock signal/CLKYO and the capacity cell C2 between the node N5 (grid of transistor Q14, Q22), be used for accepting clock signal/CLKYO, and make grid (latching the output node of the transducer 23) boost in voltage (below, capacity cell C1, C2 are called " boost capacitor " respectively) of transistor Q14, Q22 respectively.

In addition, transistor Q24, Q25 are the clamp elements that the level of node N5, N7 after utilizing boost capacitor C1, C2 to boost is separately fixed at VDD+Vth (VDD: supply voltage, the threshold voltage of Vth:a-Si TFT).Be no more than the drift that VDD+Vth suppresses these transistorized threshold voltages by the grid voltage that makes transistor Q14, Q18, Q20, Q22.

Fig. 8 and Fig. 9 are the timing diagrams of work of the frequency dividing circuit 20 of presentation graphs 7.Below, the work of frequency dividing circuit 20 is described according to these figure.For convenience of explanation, will be made as 0, the power supply potential of hot side will be made as VDD as the power supply potential (VSS) of the low potential side of reference potential.In addition, with start signal STYO, STYE and clock signal clk YO ,/CLKYO, CLKYE ,/each L level of CLKYE and the current potential of H level be made as 0 and VDD respectively.Have again, when practical application, because of the corresponding reference potential of setting with the level of the data that write pixel, thus the current potential of low potential side power supply and hot side power supply for example be set at respectively-12V ,+17V etc.

At first, with reference to Fig. 8, just suppose that before moment t10, fractional frequency signal VFR is the L level, fractional frequency signal/VFR is the H level.At this moment, node N8 is H level (VDD-Vth), and node N1 is L level (0).At moment t10, when start signal STYO became H level (VDD), transistor Q1 conducting was to the level of node N1 transmission node N8.Because of the conducting resistance of transistor Q3 is set enough highlyer than the conducting resistance of transistor Q1, Q18, so node N1 becomes H level (VDD-Vth).Thus, transistor Q5 conducting, still, because of the conducting resistance of transistor Q5 is set enough lowlyer than the conducting resistance of transistor Q4, Q6, so node N2 changes to the L level from H level (VDD-Vth).As a result, transistor Q7 ends, transistor Q8 conducting, and the output node N3 of impact damper 22 becomes L level (0).

At moment t11, when start signal STY0 became L level (0), transistor Q1 ended, but the effect of the latch that reason transistor Q2～Q5 constitutes, the level of each node N1, N2, N3 is kept intact.

At moment t12, when start signal STYE became H level (VDD), transistor Q9 conducting was to the level of node N4 transmission node N3.Because of the conducting resistance of transistor Q10 is set enough highlyer than the conducting resistance of transistor Q8, Q9, so node N4 changes to the L level from H level (VDD-Vth), transistor Q13 ends.But, at this constantly, because of clock signal clk YE is L level (0), so the output node N5 maintenance L level (0) of the transducer that is made of transistor Q12, Q13 is constant.

Then, at moment t13, when start signal STYE became L level (0), transistor Q9 ended, still, as mentioned above, because of the conducting resistance of transistor Q10 is enough high, driving force is low, so the level of node N4 can only slowly rise, before next clock signal clk YE became the moment t14 of H level, node N4 maintained the L level.

At moment t14, when clock signal CLKYE becomes H level (VDD), transistor Q12 conducting, the output node N5 of the transducer that is made of transistor Q12, Q13 becomes H level (VDD-Vth).Meanwhile, because of transistor Q11 conducting, so utilize the effect of the latch that is made of transistor Q10～Q13, the L level of node N4, the H level of node N5 keep respectively remaining untouched.As a result, become the state that transistor Q14 conducting, transistor Q15 end, so the output node N6 of impact damper 24 becomes H level (VDD-2 * Vth).

When node N6 becomes the H level, transistor Q17, Q19, Q21 conducting.At this moment, because of clock signal clk YE is the H level, so also conducting of transistor Q16, still, the conducting resistance of transistor Q17 is set enough lowlyer than the conducting resistance of transistor Q16, and the output node N7 of transducer 25 becomes L level (≈ 0).

When node N7 became the L level, transistor Q18 ended, and transistor Q19 conducting is so the output node N8 of impact damper 26 becomes L level (0).Meanwhile, transistor Q20 ends, transistor Q21 conducting, so, the level of the output node N9 of output buffer 27, be that the level of fractional frequency signal/VFR becomes L level (0).

In addition, when node N8 becomes the L level, transistor Q22 conducting, transistor Q23 ends, so, the level of the output node 10 of output buffer 28, be that the level of fractional frequency signal/VFR becomes H level (VDD-2 * Vth).

The grid of fractional frequency signal VFR input transistors Q2.Therefore, during fractional frequency signal VFR was the H level, transistor Q2 conducting can prevent the level due to leakage current of node N1 and reduces.In addition, at moment t15, when clock signal CLKYE became L level (0), transistor Q12, Q16 ended.When transistor Q16 ended, to node N7 supplying electric current, the level of node N7 did not become 0 to transistor Q16.

And then in the frequency dividing circuit 20 of Fig. 7, at moment t16, when clock signal/CLKYO became H level (VDD), by the capacitive coupling of boost capacitor C2, node N5 (grid of transistor Q14, Q22) was boosted.Thus, when the level of node N5 becomes VDD+Vth, be not equivalent to the loss of the threshold voltage of transistor Q22, fractional frequency signal VFR (node N10) rises to VDD.

At this moment, be connected the drift of the threshold voltage of transistor Q25 inhibition transistor Q14, Q22 between node N5 and the hot side power supply (VDD), the level of node N5 can excessively not uprised.Transistor Q25 is that diode connects, and negative electrode is connected with hot side power supply (VDD), and as shown in Figure 8, the level of node N5 can not surpass VDD+Vth.Equally, the transistor Q24 that is connected between node N7 and the hot side power supply (VDD) makes the level of node N7 be no more than VDD+Vth (with reference to Fig. 9).Have again, at moment t16, though because of the capacity coupled effect of boost capacitor C1 can make the level of node N7 also rise,, because of transistor Q17 conducting event can remain on the L level.

Then, at moment t17, when clock signal/CLKYO becomes L level (0), because of the capacitive coupling of boost capacitor C2, the level of node N5 reduces the voltage Δ V of regulation, still, because of the load of fractional frequency signal VFR normally capacitive, even so the grid voltage of transistor Q22 descends, the level of node N10 also can be kept getting off by this load, the level of fractional frequency signal VFR can not change.

In addition, at moment t17, descend even node N5 produces the level of voltage Δ V, when clock signal/CLKYE became H level (VDD), node N5 just was charged to level as the VDD-Vth of Fig. 8 by transistor Q12.In addition, when clock signal/CLKYO became the H level, and boosted to VDD+Vth, the level of fractional frequency signal VFR (node N10) maintained VDD to node N5 with regard to the capacitive coupling by boost capacitor C2.

Have again, when clock signal CLKYE becomes the H level, also conducting of transistor Q16, also to node N7 supplying electric current, still, because of transistor Q17 conducting at this moment, so node N7 remains on L level (≈ 0), the level of fractional frequency signal/VFR (node N9) remains on 0.

Then, fractional frequency signal VFR is that H level, fractional frequency signal/VFR are the states of L level, is maintained to start signal STYO, STYE and becomes before the H level next time.

Secondly, to being that H level, fractional frequency signal/VFR are that the work of state (node N8 is the L level, and node N1 is the H level) when start signal STYO becomes the H level again of L level describes from fractional frequency signal VFR.

With reference to Fig. 9, at moment t20, when start signal STYO becomes H level (VDD), transistor Q1 conducting, the level of node N8 sends node N1 to, and node N1 becomes L level (0).Thus, transistor Q5 ends, and then transistor Q6 conducting at this moment is so node N2 becomes H level (VDD-Vth).As a result, transistor Q7 conducting, transistor Q8 ends, and the output node N3 of impact damper 22 becomes H level (VDD-2 * Vth).

At moment t21, when start signal STYO became L level (0), transistor Q1, Q6 ended, the effect of the latch that reason transistor Q2～Q5 constitutes, and each level of node N1, N2, N3 remains unchanged.

At moment t22, when start signal STYE becomes H level (VDD), transistor Q9 conducting, the level of node N3 sends node N4 to.That is, node N4 becomes the H level, transistor Q13 conducting.At this moment, because of clock signal clk YE is the L level, so transistor Q12 ends, node N5 becomes L level (0).Thus, transistor Q11 ends, and the level of node N4 becomes VDD-Vth.

Like this, when node N4 become the H level, when node N5 becomes the L level, transistor Q14 ends, transistor Q15 conducting, node N6 becomes L level (0).Have, when node N5 became the L level, transistor Q22 also ended again, and still, as mentioned above, because of the load of fractional frequency signal VFR is capacitive, so the level of node N10 is kept getting off by this load, at this constantly, the level of fractional frequency signal VFR is constant.In addition, when node N6 became the L level, transistor Q17, Q19, Q21 ended, still, at this constantly, because of clock signal clk YE ,/CLKYO is the L level, so the level of node N7, N8, N9 is also constant.

Then, at moment t23, though start signal STYE becomes L level (0),, the effect of the latch that reason transistor Q10～Q13 constitutes, each level of node N4, N5, N6 remains unchanged.

At moment t24, when clock signal CLKYE becomes H level (VDD), transistor Q16 conducting, node N7 becomes H level (VDD-Vth).Thus, because of transistor Q18 conducting, transistor Q19 ends, so node N8 becomes H level (VDD-2 * Vth).Meanwhile, transistor Q20 conducting, transistor Q21 ends, so the level of fractional frequency signal/VFR (node N9) also becomes H level (VDD-2 * Vth).

The grid of fractional frequency signal/VFR input transistors Q4, Q10.Therefore, during fractional frequency signal/VFR was the H level, transistor Q4, Q10 conducting can prevent node N2, N4 due to leakage current and level is reduced.

On the other hand, when node N8 became the H level, transistor Q22 ended, and transistor Q23 conducting is so the level of fractional frequency signal VFR (node N10) becomes L level (0).

Have again, at moment t24, when clock signal CLKYE becomes the H level, transistor Q12 conducting, so, to node N5 supplying electric current, electrical level rising some, still, because of transistor Q13 conducting at this moment, so node N5 remains on L level (≈ 0).In addition, at moment t25, when clock signal CLKYE becomes L level (0), because of transistor Q12, Q16 end, so the level of node N5 becomes 0.

And then in the frequency dividing circuit 20 of Fig. 7, at moment t26, when clock signal/CLKYO became H level (VDD), because of the capacitive coupling of boost capacitor C1, node N7 (grid of transistor Q14, Q20) boosted.Thus, when the level of node N7 becomes VDD+Vth, be not equivalent to the loss of the threshold voltage of transistor Q20, fractional frequency signal/VFR (level of node N8) rises to VDD.

At this moment, because of being connected the effect of the transistor Q24 between node N7 and the hot side power supply (VDD), the level of node N7 can not surpass VDD+Vth as shown in Figure 9.Have again, at moment t26, though because of the capacity coupled effect of boost capacitor C2 can make the level of node N5 also rise,, because of transistor Q13 conducting event can remain on the L level.

Then, at moment t27, when clock signal/CLKYO becomes L level (0), because of the capacitive coupling of boost capacitor C1, the level of node N7 reduces the voltage Δ V of regulation, still, because of the current potential of fractional frequency signal/VFR is kept by capacity load, so the level of fractional frequency signal/VFR can not change.

In addition, at moment t27, descend even produce the level of voltage Δ V at node N7 place, when clock signal clk YE became H level (VDD), node N7 just was charged to the level of VDD-Vth as shown in Figure 9 by transistor Q16.And then when clock signal/CLKYO became the H level, node N7 just boosted to VDD+Vth because of the capacitive coupling of boost capacitor C1, and the level of fractional frequency signal/VFR (node N9) remains on VDD.

This fractional frequency signal VFR is that L level, fractional frequency signal/VFR are the states of H level, is maintained to start signal STYO, STYE and becomes before the H level next time.

By the work of Fig. 8, Fig. 9 as can be known, fractional frequency signal VFR ,/VFR reverses by each cycle of start signal STYO, STYE (that is, by each image duration of the picture signal).That is, fractional frequency signal VFR ,/VFR is the signal of 2 doubling times of start signal STYO, STYE.Therefore, can with this fractional frequency signal VFR ,/VFR uses as switching signal, is used for switching by each frame the a-Si TFT of 2 drop-down usefulness of output that each shift register had of gate drivers 11,12.

Work from the above description as can be known, this switching signal (fractional frequency signal VFR ,/VFR) only use the drive control signal (start signal, clock signal) of general Drive and Control Circuit output to generate.Therefore, can use general Drive and Control Circuit, make gate drivers 11,12 come work alternately to switch 2 modes (for example mode of non-patent literature 1) of exporting the a-Si TFT of drop-down usefulness by each frame.That is, can suppress the rising of display device cost, simultaneously, what can prevent that change because of the threshold voltage of the a-Si TFT of gate drivers from causing delays work.

And then as shown in Figure 7,20 a-Si TFT by same conduction type of frequency dividing circuit constitute, so, can use and picture element matrix or gate drivers 11,12 same manufacturing process on glass substrate, form.Therefore, can suppress the increase of the complicated and manufacturing cost of manufacturing process.

In addition, by above explanation as can be known, in the frequency dividing circuit 20 of Fig. 7, whenever fractional frequency signal VFR ,/VFR when counter-rotating, the grid level counter-rotating of all a-Si TFT.That is, the grid of each a-Si TFT is with the periodic reversal of 1 image duration, rather than lasting biasing.Therefore, the drift of threshold voltage is inhibited among the a-Si TFT in the frequency dividing circuit 20.

Have again, in the frequency dividing circuit 20 of Fig. 7,, then also can not want transistor Q24, Q25 if can suitably select capacitance and the suitable boost level of setting node N5, N7 of boost capacitor C1, C2.In addition, if VFR ,/the H level of VFR can be original VDD-2 * Vth, then also can not need the input of boost capacitor C1, C2 and clock signal/CLKYO.That is, the frequency dividing circuit 20 of Fig. 7 can be driven by 2 phase start signals and the 1 phase clock signal from Drive and Control Circuit output at least.

In addition, in the frequency dividing circuit 20 of Fig. 7, clock signal clk YE is used for node N5, N7 are recharged (refreshing), if but become the signal of H level repeatedly, then also can be other clock signals.In addition, even big and carry out according to 1 phase clock signal can using 2 above mutually clock signals that node N5, N7 are refreshed under the situation that the level of refresh node N5, N7 also may reduce at leakage current.For example, when using 2 phase clocks that node N5 is refreshed, can be set up in parallel other transistor, drive two transistors by the mutually different clock signal of phase place with transistor Q12.Equally, when using 2 phase clocks that node N7 is refreshed, can be set up in parallel other transistor, drive two transistors by the mutually different clock signal of phase place with transistor Q16.

In Fig. 4, show the display device of the mode of the gate line that uses odd gates driver 11 and even number gate drivers 12 to drive picture element matrix, but the present invention also goes for the display device with the mode of 1 gate driver drive.Figure 10 illustrates this example.

As shown in figure 10, when with 1 gate drivers, 13 driving grid line G1, G2 ... the time, from Drive and Control Circuit 110 to the start signal STY of gate drivers 13 input 1 phase with 2 mutually clock signal clk Y ,/CLKY.

As mentioned above, general driving control circuit (LSI) constitutes sometimes can export two kinds of drive control signal under the situation, so that can adapt to any situation that gate drivers is 1 and 2.The Drive and Control Circuit 110 of Figure 10 is exactly the circuit of this type, not only can export above-mentioned start signal STY, clock signal clk Y ,/CLKY, also can export the 2 phase start signal STYO, the STYE that in the formation of Fig. 4, use and the unshowned 4 phase clock signal CLKYO of Figure 10 ,/CLKYO, CLKYE ,/CLKYE.

Therefore, as shown in figure 10, if use 2 phase start signal STYO, STYE and 2 phase clock signal CLKY ,/CLKY drives frequency dividing circuit 20, then by and the same work of formation of Fig. 4, can obtain as shown in Figure 11 by the fractional frequency signal VFR that reverses each image duration ,/VFR.That is, even under the situation of the gate line that uses 1 gate drivers, 13 driving picture element matrixs, also can obtain and above-mentioned same effect.

In addition, in Figure 10, use 2 phase start signal STYO, STYE and 2 phase clock signal CLKY ,/CLKY drives frequency dividing circuit 20, still, also can use 2 phase clock signals of other array configurations go to replace clock signal clk Y ,/CLKY.For example, also can use clock signal clk YE ,/CLKYO.Certainly, in the formation of Fig. 4, also can use clock signal clk Y ,/CLKY replace clock signal clk YE ,/CLKYO.

In addition, as shown in Figure 11, start signal STYO and start signal STY are same signals, so, in Figure 10, also can use start signal STY to remove to replace start signal STYO.

Have again, in the present embodiment, the semiconductor layer that forms the thin film transistor (TFT) that constitutes pixel, gate drivers and frequency dividing circuit that display device of the present invention possessed is amorphous silicon (a-Si), if these thin film transistor (TFT)s are a-Si TFT and are illustrated, but, accommodation of the present invention is not limited thereto, and also goes for for example using situations such as organic tft.As previously mentioned, organic tft is the same with a-Si TFT, has the problem of threshold voltage shift, so, can obtain the effect same with the situation of a-Si TFT, be effective therefore.In addition, also be same in the embodiment that this situation illustrates below.

＜embodiment 2 〉

In embodiment 2, the circuit structure example of the frequency dividing circuit different with Fig. 7 20 is shown.

Figure 12 is the figure that the circuit of the frequency dividing circuit 20a of expression embodiment 2 constitutes.

In frequency dividing circuit 20a, between the input terminal of start signal STYE and node N5, be provided with transistor 26, different with the frequency dividing circuit 20 of Fig. 7 in this.That is, frequency dividing circuit 20a has between node N1 and N5 by what transistor Q10～Q13, Q26 constituted and latchs transducer 23a, latchs transducer 23 to replace Fig. 7's.

Figure 13 is the timing diagram of the work of expression frequency dividing circuit 20a, illustrating from fractional frequency signal VFR is that H level, fractional frequency signal/VFR are that the state transition of L level is that L level, fractional frequency signal/VFR are the work (that is, Figure 13 is corresponding with the Fig. 8 that illustrates above) of the state of H level to fractional frequency signal VFR.

As illustrated in fig. 8, in the frequency dividing circuit 20 of Fig. 7, become the moment t14 of H level at clock signal clk YE, node N5 carries out the work from the L electrical level transfer to the H level.Relative therewith, in the frequency dividing circuit 20a of Figure 13, because of in moment t12 transistor Q26 conducting when start signal STYE becomes the H level, thus this constantly node N5 to the H electrical level transfer.Thereupon, the level of node N6～N10 also switches at moment t12.Except the level switching timing of this node N5～N10, the work of the frequency dividing circuit 20 of all the other and Fig. 7 is identical, so, omit its detailed description here.

＜embodiment 3 〉

Embodiment 3 also illustrates the circuit structure example of the frequency dividing circuit different with Fig. 7 20.Figure 14 is the figure that the circuit of the frequency dividing circuit 20b of expression embodiment 3 constitutes.In the frequency dividing circuit 20b of Figure 14, be provided with the transistor Q1 of impact damper 29, and then be provided with impact damper 22a to replace impact damper 22 and the transistor Q9 of Fig. 7 with replacement Fig. 7.In addition formation is the same with Fig. 7.

Impact damper 29 by the buffer circuit that constitutes with transistor Q18a, Q19a, be connected the transistor Q1a between the input terminal of this buffer circuit and start signal STYO and be connected this buffer circuit and the low potential side power supply between transistor Q1b constitute.The grid of transistor Q18a is connected with the grid (node N7) of transistor Q18, and the grid of transistor Q19a is connected with the grid (node N6) of transistor Q19.In addition, the grid of transistor Q1a, Q1b all is connected with the input terminal of start signal STYO.

Therefore, start signal STYO become the H level during, transistor Q1a, Q1b conducting are so impact damper 29 is to the identical level of output level (level of node N8) of node N1 output and impact damper 26.In addition, start signal STYO be the L level during, transistor Q1a, Q1b end, so node N1 and node N6 and node N7 electricity is isolated.That is, impact damper 29 carries out the work same with the transistor Q1 of Fig. 7.

In addition, impact damper 22a by the buffer circuit that constitutes with transistor Q7a, Q8a, be connected the transistor Q9a between the input terminal of this buffer circuit and start signal STYE and be connected this buffer circuit and the low potential side power supply between transistor Q9b constitute.The transistor Q7 of transistor Q7a and Fig. 7 is the same, and its grid is connected with node N2, and the transistor Q8 of transistor Q8a and Fig. 7 is the same, and its grid is connected with node N1.In addition, the grid of transistor Q9a, Q9b all is connected with the input terminal of start signal STYE.

Therefore, start signal STYE become the H level during, transistor Q9a, Q9b conducting are so impact damper 22a is to the level of node N4 output node N2.In addition, start signal STYE be the L level during, transistor Q9a, Q9b end, so node N4 and node N1 and node N2 electricity is isolated.That is, this impact damper 29 carries out impact damper 22 and the same work of transistor Q9 with the circuit of Fig. 7.

As known from the above, the frequency dividing circuit 20b of Figure 14 carries out the work same with the frequency dividing circuit 20 of Fig. 7.In addition, about the whole work of frequency dividing circuit 20, because of with embodiment 1 in the explanation the same, so omit its explanation here.

＜embodiment 4 〉

In the frequency dividing circuit 20 of the Fig. 7 that as above illustrates, for example, node N5 is the L level during the half period of the work period of frequency dividing circuit 20.The grid input clock signal CLKYE of transistor Q12, still, node N5 be the L level during, when the grid of transistor Q12 becomes the H level, the relative source electrode of this grid (node N5) forward bias.On the contrary, node N5 be the H level during, when the grid of transistor Q12 becomes the L level, the biasing of the relative source electrode negative sense of this grid.In addition, when in whole work period, when the grid of transistor Q12 becomes the L level, drain relatively (VDD) negative sense biasing of this grid.

By above-mentioned grid just/negative sense biasing, the threshold voltage of transistor Q12 drifts about, but common, by the easier generation of drift that forward bias causes, therefore, the threshold voltage of transistor Q12 might be to positive excursion (rising).When the threshold voltage (Vth) of transistor Q12 rose, the current potential (VDD-Vth) of the H level of node N5 descended, result, the problem that exists the current potential of the H level of fractional frequency signal VFR (node N10) to descend.

Equally, the threshold voltage of transistor Q16 (Vth) also might be to positive excursion.At this moment, the current potential (VDD-Vth) of the H level of node N7 descends, the problem that exists the current potential of the H level of fractional frequency signal/VFR (node N9) to descend.

As mentioned above, in the frequency dividing circuit 20 of Fig. 7, the level that utilizes boost capacitor C1, C2 to compensate node N7, N5 respectively descends.If increase the electric capacity of boost capacitor C1, C2, then this compensation ability will improve, and still, on the contrary, occur postponing because of this electric capacity makes the electrical level rising of node N7, N5, so compensation has certain limit.

Figure 15 is the circuit diagram of the frequency dividing circuit 20c of embodiment 4, can address the above problem.In the frequency dividing circuit 20c of Figure 15, the transistor Q20 of resistive element R1 with replacement Fig. 7 is set, and then resistive element R2 is set to replace the transistor Q22 of Fig. 7.That is, resistive element R1 is connected between hot side power supply (VDD) and the node N9 and transistor Q21 constitutes output buffer 27 together, and resistive element R2 is connected between hot side power supply and the node N10 and transistor Q23 constitutes output buffer 28 together.Have, the work of the frequency dividing circuit 20 of the Fig. 7 that illustrates in the work of frequency dividing circuit 20c itself and the embodiment 1 is roughly the same again, so, omit its detailed description here.

In the frequency dividing circuit 20c of Figure 15, the H level of fractional frequency signal VFR can be set by resistive element R2, so if transistor Q23 ends, then the level of fractional frequency signal VFR (node N10) becomes VDD.That is, different with the situation of the frequency dividing circuit 20 of Fig. 7, the level of fractional frequency signal VFR is not subjected to the influence of the level of node N5, so, even the threshold voltage of transistor Q12 rises, can not produce the problems referred to above yet.

Equally, the H level of fractional frequency signal/VFR can be set by resistive element R1, so if transistor Q21 ends, then the level of fractional frequency signal/VFR (node N9) becomes VDD.That is, different with the situation of the frequency dividing circuit 20 of Fig. 7, the level of fractional frequency signal/VFR is not subjected to the influence of the level of node N7, so, even the threshold voltage of transistor Q16 rises, can not produce the problems referred to above yet.

As a result, also there is no need to be provided with compensation node N5, N7 level boost capacitor C1, C2 and as transistor Q24, the Q25 of clamp element.

Have again, the rising of the threshold voltage of transistor Q12 can cause that the current potential of the H level of node N6 descends, and is same, and the rising of the threshold voltage of transistor Q16 can cause that the current potential of the H level of node N8 descends, so, also can be respectively the conducting work of transistor Q21, Q23 be exerted an influence.As its countermeasure, can suitably set the resistance value of resistive element R1, R2 and the conduction resistance value of transistor Q21, Q23, so that transistor Q21, Q23 are operated in non-saturated region.So, the rising of the current potential of the L level of fractional frequency signal/VFR (node N9) and fractional frequency signal VFR (node N10) becomes little of negligible degree.

Usually, parallel to form the resistive element with specific resistance value very difficult with the manufacturing process of a-Si TFT, so, as resistive element R1, R2, can use the discrete resistors element.In addition, general, because of the discrete resistors element is cheap,, can not become problem so follow the rising of the caused installation cost of frequency dividing circuit 20c that adopts Figure 15 very little.

Have again, in the present embodiment, transistor Q20, the Q22 of the frequency dividing circuit 20 that replaces Fig. 7 has been described and the formation of resistive element R1, R2 has been set, but, clearly, in the frequency dividing circuit 20b of the frequency dividing circuit 20a of Figure 12 and Figure 14, also can adopt the formation that replaces transistor Q20, Q22 and resistive element R1, R2 are set, thereby obtain and above-mentioned same effect.

＜embodiment 5 〉

In embodiment 5, the object lesson of the shift register that constitutes the gate drivers (above-mentioned gate drivers 11,12,13) that is applicable to display device of the present invention is shown.Gate drivers constitutes (with reference to Figure 17) by a plurality of shift-register circuits that cascade connects (being connected in series), below, this each shift-register circuit is called " single-place shift register ".

For convenience of description, before beginning that present embodiment is described, employed shift register in the existing gate drivers of simple declaration.Figure 16 is the circuit diagram of employed single-place shift register SRA in the existing gate drivers.

This single-place shift register SRA all is made of n channel-type a-Si TFT (following title " transistor "), and it has input terminal IN, lead-out terminal OUT, the 1st clock terminal A and the 2nd clock terminal B.Lead-out terminal OUT is equivalent to the lead-out terminal of gate drivers.

In single-place shift register SRA, be used for output stage to gate lines G n output drive signal, by be connected the transistor T 1 between lead-out terminal OUT and the 1st clock terminal A and be connected lead-out terminal OUT and low potential side power supply (0) between output drop-downly constitute with transistor T 2.The gate node of transistor T 1 is defined as node ND1, the gate node of transistor T 2 is defined as node ND2.

Connect transistor T 3 between node ND1 and the hot side power supply (VDD), connect transistor T 4 between node ND1 and the low potential side power supply (0).The grid of transistor T 3 is connected with input terminal IN, and the grid of transistor T 4 is connected with node ND2.Be connected with the transistor T 5 that diode connects between node ND2 and the hot side power supply (VDD), connect transistor T 6 between node ND2 and the low potential side power supply.The grid of transistor T 6 is connected with node ND1.Transistor T 7 is connected between node ND1 and the low potential power source, and its grid is connected with the 2nd clock terminal B.

In addition, as shown in figure 17, gate drivers GD constitutes by a plurality of single-place shift register SRA that are connected in series.Single-place shift register SRA1, SRA2 shown in Figure 17 ... fully identical with the single-place shift register SRA of Figure 16.As shown in figure 17, the input terminal IN of constituent parts shift register SRA is connected with the lead-out terminal OUT of the single-place shift register SRA of its previous stage.But the input terminal IN of the 1st grade single-place shift register SRA is connected with driving control device CTL, and is transfused to the corresponding start signal ST of beginning with each image duration of picture signal.

In the formation of Figure 17,1 phase start signal ST of gate drivers GD use driving control device CTL output and 2 phase clock signal CLK ,/the CLK driving.At this moment, clock signal clk ,/the 1st clock terminal A of side input constituent parts shift register SRA among the CLK, so that the input clock signal of counter-rotating mutually among the adjacent single-place shift register SRA.In addition, the 2nd clock terminal B of constituent parts shift register SRA is connected with the lead-out terminal OUT (the gate lines G n+1 of next stage) of the single-place shift register SRA of its next stage.

The following describes the work of the single-place shift register of Figure 16.Be purposes of simplicity of explanation, the situation of the 1st clock terminal A input clock signal CLK of single-place shift register SRA is described.

At first, when gate lines G n was in nonselection mode, node ND1 was the L level, and node ND2 is the H level, and therefore, transistor T 1 ends, and transistor T 2 conductings are so lead-out terminal OUT (gate lines G n) is fixed on the L level.

When the lead-out terminal OUT of the single-place shift register SRA that becomes prime from this state (the gate lines G n-1 of prime) is the H level, with the sub-IN of its fan-in, transistor T 3 conductings.At this moment, node ND2 is the L level, so, also conducting of transistor T 4, still, the conducting resistance of transistor T 3 is set enough lowlyer than the conducting resistance of transistor T 4, and node ND1 changes to the H level.As a result, transistor T 1 conducting.

When node ND1 becomes the H level, transistor T 6 conductings.The conducting resistance of transistor T 6 is set enough lowlyer than the conducting resistance of transistor T 5, and node ND2 changes to the L level.As a result, transistor T 2 ends.

Like this, under the state that transistor T 1 conducting, transistor T 2 end, the level that the level of lead-out terminal OUT is followed clock signal clk changes.Therefore, clock signal clk become the H level during, lead-out terminal OUT (gate lines G n) also becomes the H level, gate lines G n is selected.

When gate lines G n becomes the H level, because of the input terminal IN of the single-place shift register SRA of next stage becomes the H level, so by and above-mentioned same work, transistor T 1 conducting, the transistor T 2 of the single-place shift register SRA of next stage end.And when clock signal/CLK became the H level, the gate lines G n+1 of next stage became the H level.

Because of the 2nd clock terminal B is connected with the gate lines G n+1 of next stage, thus when the gate lines G n+1 of next stage becomes the H level, transistor T 7 conductings, getting back to node ND1 is that L level, node ND2 are the state of H level, promptly gate lines G n gets back to nonselection mode.

More than work as shown in figure 17, according to the single-place shift register SRA1, the SRA2 that are connected in series ... order carry out.Thus, be input to the 1st grade the start signal ST of input terminal IN of single-place shift register SRA1 and clock signal clk ,/CLK synchronously is shifted, simultaneously, send to successively single-place shift register SRA2, SRA3 ...As a result, gate drivers GD timing diagram as shown in figure 18 is such, with clock signal clk ,/CLK synchronously make successively gate lines G L1, GL2, GL3 ... become the H level.

The voltage waveform of the node ND2 of the 1st grade of single-place shift register SRA1 is shown in the bottom of the timing diagram of Figure 18 here.Each gate line only selected 1 time in 1 image duration is so the node ND2 of constituent parts shift register SRA continues to remain on the H level outside this period.That is, the grid of transistor T 2 and transistor T 4 is almost all continued biasing during all.Therefore, the problem that has the threshold voltage shift of above-mentioned a-Si TFT.

Below, the single-place shift register of embodiment 5 is described.Figure 19 is the circuit diagram of the single-place shift register SRB of embodiment 5, is the circuit that constitutes the gate drivers that is applicable to display device of the present invention.As shown in the drawing, this single-place shift register SRB also all is made of n channel-type a-Si TFT (to call " transistor " in the following text).But, except input terminal IN, lead-out terminal OUT, the 1st clock terminal A and the 2nd clock terminal B, also have the input terminal S1 (to call " VFR terminal S1 " in the following text) of fractional frequency signal VFR and the input terminal S2 (to call "/VFR terminal S2 " in the following text) of fractional frequency signal/VFR.Lead-out terminal OUT is equivalent to the lead-out terminal of gate drivers.

In single-place shift register SRB, be used for output stage to gate lines G n output drive signal, by be connected the transistor T 1 between lead-out terminal OUT and the 1st clock terminal A and all be connected lead-out terminal OUT and the low potential side power supply between 2 outputs drop-downly constitute with transistor T 2a, T2b.Transistor T 2a, T2b connect mutually side by side.Here, the gate node of transistor T 1 is defined as node ND1, the gate node of transistor T 2a is defined as node ND2a, the gate node of transistor T 2b is defined as node ND2b.

Be connected with transistor T 3 between node ND1 and the hot side power supply (VDD).In addition, be connected with the transistor T 4b that transistor T 4a that grid is connected with node ND2a and grid are connected with node ND2b between node ND1 and the low potential side power supply.

Be connected with the transistor T 5a that diode connects between node ND2a and the VFR terminal S1, be connected with transistor T 6a between node ND2a and the low potential side power supply.Node ND2b and/be connected with the transistor T 5b that diode connects between the VFR terminal S2, be connected with transistor T 6b between node ND2b and the low potential side power supply.The grid of transistor T 6a, T6b all is connected with node ND1.

Transistor T 7 is connected between node ND1 and the low potential side power supply, and its grid is connected with the 2nd clock terminal B.

Be connected with the transistor T 8a that grid is connected with node ND2b between node ND2a and the VFR terminal S1.In addition, node ND2b and/be connected with the transistor T 8b that grid is connected with node ND2a between the VFR terminal S2.

Below, the work of this single-place shift register SRB is described.Consider that node ND1 is reset the state (that is the nonselection mode of gate lines G n) of L level by transistor T 7.

At this moment, if establishing fractional frequency signal VFR is that H level, fractional frequency signal/VFR are the L level, then node ND2a becomes the H level, transistor T 8b conducting.In addition, do not flow into node ND2b because of there being electric current through transistor T 5b, so node ND2b becomes L level (0).Therefore, the grid of transistor T 2b and transistor T 4b is not biased, and becomes dormant state.In addition, transistor T 5b, T6b do not work because of there being power supply to supply with yet.Promptly, during fractional frequency signal VFR H level, fractional frequency signal/VFR are the L level, this single-place shift register SRB is by the combination of transistor T 1, T2a, T3, T4a, T5a, T6a, T7, constitutes and the circuit of single-place shift register SRA equivalence shown in Figure 16.

On the contrary, be that L level, fractional frequency signal/VFR are under the situation of H level at fractional frequency signal VFR, node ND2b becomes the H level, transistor T 8a conducting.In addition, do not flow into node ND2a because of there being electric current through transistor T 5a, so node ND2a becomes L level (0).Therefore at this moment, the grid of transistor T 2a and transistor T 4a is not biased, and becomes dormant state.In addition, transistor T 5a, T6a do not work yet.Promptly, during fractional frequency signal VFR L level, fractional frequency signal/VFR are the H level, this single-place shift register SRB is by the combination of transistor T 1, T2b, T3, T4b, T5b, T6b, T7, constitutes and the circuit of single-place shift register SRA equivalence shown in Figure 16.

Therefore, the same with Figure 17, a plurality of single-place shift register SRB are connected in series, constitute gate drivers GD, thus, can carry out the work same with Figure 18.And, whenever fractional frequency signal VFR ,/VFR when counter-rotating (per 1 image duration), make pair of transistor T2a, T4a and pair of transistor T2b, T4b alternately be in dormant state, thus, can prevent that their grid from being continued biasing.That is, if gate drivers GD by being made of single-place shift register SRB, what just can prevent that threshold drift because of a-Si TFT from causing delays work, and improves the reliability of display device.

＜embodiment 6 〉

Above embodiment is that can to tackle gate drivers be that 1 and 2 s' the Drive and Control Circuit 110 of any situation is as prerequisite to use.But, in general Drive and Control Circuit, great majority can only tackle 1 gate drivers situation (can only export 1 phase start signal STY and 2 phase clock signal CLKY ,/CLKY).If both are compared, the circuit of situation that can only tackle 1 gate drivers is few because of the output circuit of control signal, certainly low price.Therefore, in the present embodiment, a kind of method of using such Drive and Control Circuit 110 to drive frequency dividing circuit 20 is proposed.

Figure 20 is the block scheme that the summary of the display device of expression embodiment 6 constitutes.As shown in figure 20, the display device of present embodiment have m root gate lines G 1, G2 ... Gm, these gate lines are all driven by 1 gate drivers 13.From Drive and Control Circuit 110 to gate drivers 13 input 1 phase start signal STY and 2 phase clock signal CLKY ,/CLKY.In addition, these signals also are imported into frequency dividing circuit 20.

Gate drivers 13 is made of a plurality of single-place shift registers that cascade connects.The same with above-mentioned embodiment, these single-place shift registers adopt according to fractional frequency signal VFR ,/VFR replace the mode (for example, the single-place shift register SRB of Figure 19) of switching to the a-Si TFT of 2 drop-down usefulness of output.The gate line that gate drivers 13 drives is the m root, but, the gate drivers 13 of present embodiment also has single-place shift register SRm+1 at the next stage of its afterbody (m level) except having m the single-place shift register that drives this m root gate line.Though this single-place shift register SRm+1 can have 2 a-Si TFT that export drop-down usefulness by image pattern 19 like that, also can use existing single-place shift register like that by image pattern 16.The continue single-place shift register output signal of afterbody of single-place shift register SRm+1.This signal is not the signal of driving grid line, but for convenience of explanation following, is called " drive signal GSm+1 ".

In addition, gate drivers 13 and then have virtual single-place shift register SRD at the next stage of single-place shift register SRm+1.The single-place shift register SRD single-place shift register SRm+1 output signal that continues, this signal are used for making single-place shift register SRm+1 reset (if the example of Figure 19 makes transistor T 7 conductings, node ND1 is the L level).

Have again, be equivalent to virtual single-place shift register that afterbody single-place shift register single-place shift register SRD, that cascade is connected of Figure 20 resets and also be arranged on usually among Fig. 1, Fig. 4 and the gate drivers 101,102,11,12,13 shown in Figure 10 etc., these all have been omitted in the drawings.

In the present embodiment, as frequency dividing circuit 20, also can use the circuit shown in Fig. 7, Figure 12, Figure 14 and Figure 15.Promptly, to the frequency dividing circuit 20 among these each figure, can import start signal STY to replace start signal STYO, input drive signal GSm+1 is to replace start signal STYE, input clock signal CLKY is to replace clock signal clk YE, and input clock signal/CLKY is to replace clock signal/CLKYO.Figure 21 illustrates the work wave of frequency dividing circuit 20 at this moment.Drive signal GSm+1 and drive signal GSm+2 all have the cycle of 1 image duration, and be phase place one group of different signal mutually, so, according to the theory of using Fig. 5 explanation, the fractional frequency signal VFR of frequency dividing circuit 20 outputs ,/VFR repeats the counter-rotating of level respectively when being activated (becoming the H level) whenever drive signal GSm+1.That is, according to the formation of Figure 20, fractional frequency signal VFR ,/VFR has the cycle (that is, start signal STY being carried out cycle behind 1/2 frequency division) of 1 image duration.

Therefore, can with this fractional frequency signal VFR ,/VFR uses as being used for switching the drop-down switching signals with a-Si TFT of 2 outputs that the constituent parts shift register of gate drivers 13 had by each frame.

Like this, according to present embodiment, even employed 1 phase start signal STY and 2 phase clock signal CLKY when Drive and Control Circuit 110 can only be exported 1 gate drivers ,/CLKY, also can generate switching signal (fractional frequency signal VFR ,/VFR).Therefore, can further cut down cost among the present invention.

In the present embodiment, the output signal (drive signal GSm+1) that constitutes single-place shift register SRm+1 different with the single-place shift register that drives pixel in a plurality of single-place shift registers of gate drivers 13 is used for driving frequency dividing circuit 20.But, drive frequency dividing circuit 20 because can use the arbitrary signal different to replace this drive signal GSm+1 with the phase place of start signal STY, so, for example, the output signal of the single-place shift register of the regulation of driving grid line can be used for driving into frequency dividing circuit 20.So, have needn't setting unit shift register SRm+1 advantage.But, because of the load of the single-place shift register of the driving of carrying out frequency dividing circuit 20 increases, so should note the slack-off shortcoming of actuating speed of the gate line of its driving of the thing followed.

＜embodiment 7 〉

As previously mentioned, the frequency dividing circuit 20 as embodiment 6 can use the circuit shown in Fig. 7, Figure 12, Figure 14 and Figure 15.But, at this moment can bring following problem.

For example, consider the frequency dividing circuit 20 of Fig. 7 is used for the situation of embodiment 6.At this moment, start signal STY is transfused to the grid of the transistor Q1 of frequency dividing circuit 20, and drive signal GSm+1 is transfused to the grid of transistor Q9.Each image duration of start signal STY and picture signal corresponding ahead, on the other hand, the activation of drive signal GSm+1 is after the activation of m root gate lines G m, so, between the timing that timing that start signal STY activates and drive signal GSm+1 activate, vacate the interval of 1 image duration.Therefore, the interval between the timing of the timing of transistor Q1 conducting and transistor Q9 conducting, be the length that time span between the timing that changes of the level of the timing that changes of the level of node N1～N3 of Fig. 7 and node N4～N10 became for 1 image duration.

Therefore, even become the L level because of start signal STY makes transistor Q1 conducting, node N1 from the H level, fractional frequency signal VFR (node N10) can not become the L level immediately yet, keeps the H level constant in 1 image duration thereafter.Therefore, all conductings of transistor Q2, Q3 both sides during this, so, flow through perforation electric current, power consumption is increased.In addition, fractional frequency signal/VFR during this (node 9) is the L level, so transistor Q4, Q5 both sides end, should be that the current potential of the node N2 of H level descends because of the leakage current of transistor Q5, might produce and delay work.

On the contrary, when utilizing start signal STY to make node N1 when the L level changes to the H level, then, in 1 image duration, fractional frequency signal VFR (node N10) keeps the L level constant, therebetween, transistor Q2, Q3 both end, so, the current potential of node N1 is descended.Therebetween, because of fractional frequency signal/VFR (node N9) is the H level, so transistor Q4, Q5 both conductings flows through perforation electric current.This problem can take place in the circuit of Figure 12, Figure 14 and Figure 15 equally.

Like this, when the circuit that uses Fig. 7, Figure 12, Figure 14 and Figure 15 during, can bring the problem of delaying work that power consumption increases and due to leakage current causes as the frequency dividing circuit 20 of embodiment 6 (Figure 20).Therefore, in embodiment 7, proposition is applicable to the frequency dividing circuit 20 of the display device of embodiment 6.

Figure 22 is the figure that the circuit of the frequency dividing circuit 20d of expression embodiment 7 constitutes.In the figure, because of the key element that has an identical function with circuit shown in Figure 7 is added prosign, so below the component part different with Fig. 7 mainly is described.

As shown in figure 22, start signal STY is transfused to the grid of transistor Q1, and drive signal GSm+1 is transfused to the grid of transistor Q9.Have again, in the present embodiment, start signal STY with and the synchronous timing of clock signal/CLKY be activated (promptly, gate lines G 1 synchronously is activated with clock signal clk Y), drive signal GSm+1 and clock signal clk Y synchronously be activated (that is, gate lines G m and clock signal/CLKY synchronously are activated).

This frequency dividing circuit 20d is characterised in that to have the transducer 30 that is connected with the output node of impact damper 22.This transducer 30 is the key elements that do not comprise in the basic comprising of frequency dividing circuit shown in Figure 5, does not directly influence the logic working of frequency dividing circuit 20d.Transducer 30 is made of transistor Q27 and transistor Q28, makes the signal after the output counter-rotating of impact damper 22 to node N11 output.In Fig. 7, the grid of transistor Q2 is connected with node N10 as the lead-out terminal of fractional frequency signal VFR, but is connected with this node N11 in the present embodiment.

The grid that latchs the transistor Q27 of the grid of transistor Q4 of transducer 21 and transducer 30 is connected on the input terminal of clock signal/CLK.In addition, the grid that latchs the transistor Q16 of the grid of transistor Q12 of transducer 23 and transducer 25 is connected on the input terminal of clock signal clk Y.And then the grid that latchs the transistor Q10 of transducer 23 is connected on the output node of transducer 25 (node N7).

Be connected with boost capacitor C3 between the input terminal of clock signal clk Y and the node N2 (latching the output node of transducer 21), be connected with boost capacitor C4 between the input terminal of clock signal clk Y and the node N11 (output node of transducer 30).In addition, between node N2 (end of boost capacitor C3) and hot side power supply (VDD), be connected with the transistor Q29 that diode connects, equally, between node N11 (end of boost capacitor C4) and hot side power supply (VDD), be connected with the transistor Q30 that diode connects.These transistors Q29, Q30 are the clamp elements that the level of node N2, N11 after boosting by boost capacitor C3, C4 is separately fixed at VDD+Vth (VDD: supply voltage, the threshold voltage of Vth:a-Si TFT).Transistor Q29, Q30 surpass the drift that VDD+Vth suppresses each transistorized threshold voltage by the grid voltage that does not make transistor Q2, Q3, Q7.

Figure 23 is the timing diagram of work that is used for illustrating the frequency dividing circuit 20d of embodiment 7.Below, describe the work of frequency dividing circuit 20d in detail with reference to this figure.Here, just suppose that before moment t30, frequency dividing circuit VFR (node N10) is the L level, fractional frequency signal/VFR (node N9) is the H level.At this moment, node N8 is H level (VDD), and node N1 is L level (0).

For convenience of explanation, at first, illustrate that the level of node N1～N3, N11 changes.At moment t30, when and clock signal/CLKY when start signal STY becomes H level (VDD) when becoming the H level, transistor Q1 conducting is to the H level of node N1 transmission node N8.Thus, the level of node N1 becomes the VDD-Vth that is equivalent to threshold voltage (Vth) size of transistor Q1 than the level decline of node N8.When node N1 becomes the H level, transistor Q5 conducting.At this moment, because of clock signal/CLKY becomes H level event transistor Q4 conducting, still, because of the conducting resistance of this transistor Q4 is set enough highlyer than the conducting resistance of transistor Q5, so node N2 becomes the L level.That is, the level of node N2 becomes than low potential side power supply potential (0) and exceeds by the conducting resistance of transistor Q4 and the transistor Q5 L level than the voltage Δ V1 (with reference to Figure 23) of decision.

Like this, when node N1 be the H level, when node N2 is the L level, transistor Q7, Q3 end, transistor Q8 conducting.Therefore, node N3 becomes L level (0), and transistor Q28 is corresponding to be ended.At this moment, because of clock signal/CLKY is the H level, so transistor Q27 conducting, node N11 becomes H level (VDD-Vth), transistor Q2 conducting.As a result, by constituting the transistor Q2～Q4 of trigger (latch), node N1, N2 are remained on H level and the L level respectively.

Then, at moment t31, when start signal STY and clock signal/CLKY got back to the L level, transistor Q1 ended, and node N8 separates with node N1.But because of transistor Q3 keeps VDD-Vth constant by the level of event node N1.In addition, Q4 ends because of transistor, so node N2 does not have the rising of voltage Δ V1 part, current potential becomes 0V.The level of node N3 is constant, keeps the L level.In addition, though transistor Q27 ends, Q28 also ends because of transistor, so node N11 is kept by its stray capacitance, becomes the H level (VDD-Vth) under the floating state.

At moment t32, when clock signal CLKY became the H level, node N11 boosted by the capacitive coupling of boost capacitor C4.But because of the effect as the transistor Q30 of clamp element, the level of node N11 is fixed on the VDD+Vth.As a result, transistor Q2 is operated in non-saturated region (unsaturation work), and the current potential of the H level of node N1 rises to VDD.

Equally, node N2 boosts by the capacitive coupling of boost capacitor C34, and transistor Q5 conducting so this rises just little by little (Δ V2 shown in Figure 23), in addition, when clock signal CLKY rises fully, is just returned 0V.That is, node N2 maintains the L level, so node N3 keeps L level (0).

At moment t33, when clock signal CLKY becomes the L level, the voltage Δ V3 that the capacitive coupling of node N11 by boost capacitor C4 descends specific, transistor Q2 ends.But the level of node N1 is kept by the stray capacitance that is attached to this node N1, so the level of node N1 is kept VDD.The voltage Δ V4 that node N2 also descends specific because of the capacitive coupling of boost capacitor C3, still, here, because of transistor Q5 conducting, so when clock signal CLKY descends fully, turn back to 0V.That is, because of node N2 maintains the L level, so node N3 keeps L level (0).

Then, at moment t34, when clock signal/CLKY became the H level once more, transistor Q4 conducting was so node N2 becomes than low potential side power supply potential (0) and exceeds the state of voltage Δ V1, but still keeps the L level.In addition, also conducting of transistor Q27, the level of node N11 becomes VDD-Vth.

Then, at moment t35, when clock signal/CLKY got back to the H level, transistor Q4 ended, so node N2 does not have the rising of voltage Δ V1 part, current potential becomes 0V.In addition, transistor Q27 also ends, and node N11 becomes the H level (VDD-Vth) under the floating state.

After this, before start signal STY is activated once more during, on node N1～N3, N11, whenever clock signal clk Y ,/CLKY when input, repeat the work of above-mentioned moment t32～t35.That is, during this period, node N1～N3, N11 keep its logical value (H level or L level).

On the other hand, on node N4～N10, the logical value (H level or L level) between t30～t35 does not change constantly.As mentioned above, just before moment t30, node N10 is the L level, and node N8, N9 are the H level, but as shown in figure 23, at this moment, node N4, N7 are the H level, and node N5, N6 are the L level.

Become the moment t30 of H level at clock signal/CLKY, become the node N7 of the H level of floating, capacitive coupling by boost capacitor C1 boost (level that becomes VDD+Vth because of effect) as the transistor Q24 of clamp element, transistor Q10 carries out unsaturation work, and node N4 is maintained at H level (VDD).In addition, the node N5 of L level (0) boosts by the capacitive coupling of boost capacitor C2, because of transistor Q13 conducting, so this rises just little by little (Δ V5 shown in Figure 23), when clock signal/CLKY rises fully, just returns 0V.Therefore, transistor Q14 ends because of keeping, transistor Q15 conducting, so node N6 keeps L level (0).Therefore, transistor Q19, Q21 remain on and end, and the level of this exterior node N7 becomes VDD+Vth, so, transistor Q18, Q20 conducting, node N8, N9 maintain H level (VDD).In addition, because of transistor Q22 at this moment by, transistor Q23 conducting, so node N10 also maintains L level (0).

In addition, get back to the moment t31 of L level at clock signal/CLKY, the level of node N7 because of the capacitive coupling of boost capacitor C1 from the descend voltage Δ V6 of regulation of VDD+Vth, transistor Q10 ends, but the stray capacitance that the level of node N4 (VDD) is attached to this node N4 keeps.Equally, though transistor Q18, Q20 also end the effect of the stray capacitance of the level of node N8, N9 by being attached to these nodes and remain on VDD respectively.In addition, the level of node N5 changes the voltage Δ V7 that stipulates because of the capacitive coupling of boost capacitor C2 to negative direction, still, and because of transistor Q13 conducting, so when clock signal/CLKY descends fully, just get back to 0V.Like this, because of node N5 keeps the L level, node N8 keeps the H level, so node N10 maintains L level (0).

Become the moment t32 of H level at clock signal clk Y, because of transistor Q12 conducting, exceed the state that compares the voltage Δ V8 of decision by the conducting resistance of transistor Q12 and transistor Q13 so node N5 becomes than low potential side power supply potential (0), but still maintain the L level.In addition, also conducting of transistor Q16, the level of node N7 is got back to VDD-Vth.The action of this node N5, N7 can not make the level of node N4, N8～N10 change.

Then, get back to the moment t33 of L level at clock signal clk Y, Q12 ends because of transistor, so node N5 does not have the rising of voltage Δ V8 part, current potential becomes 0V.In addition, transistor Q16 also ends, and node N7 becomes the H level (VDD-Vth) under the floating state.The action of this node N5, N7 can not make the level of node N4, N8～N10 change yet.

After moment t34, before drive signal GSm+1 is activated during, whenever clock signal clk Y ,/CLKY when input, node N4～N10 carries out the work of above-mentioned moment t30～t33 repeatedly.That is, the logical value (H level or L level) at node N4～N10 this period is maintained.

Then, from above-mentioned moment t30 to through the moment t40 after 1 image duration, drive signal GSm+1 becomes H level (VDD).Below, the work of frequency dividing circuit 20d is at this moment described.As previously mentioned, node N1～N3, N11 carried out the work of t32～t35 constantly, repeatedly so the logical value of node N1～N3, N11 (H level or L level) is maintained before next start signal STY is activated.On the other hand, after moment t40, node N4～N10 carries out following work.

When moment t40 drive signal GSm+1 becomes the H level, transistor Q9 conducting, to the L level of node N4 transmission node N3, transistor Q13, Q15 conducting.At this moment, because of clock signal clk Y becomes the H level, so transistor Q12, Q16 conducting.Therefore, node N5 becomes H level (VDD-Vth), transistor Q11 conducting.Simultaneously, transistor Q14 conducting, node N6 becomes H level (VDD-2 * Vth).At this moment, transistor Q16, Q17 are in conducting state, but the conducting resistance of transistor Q16 is set enough greatlyyer than the conducting resistance of transistor Q17, and node N7 becomes the L level.That is, node N7 at this moment becomes than low-pressure side power supply potential VSS (0) and exceeds by the conducting resistance of transistor Q16, the Q17 L level than the state of the assigned voltage Δ V9 of decision.

As a result, Q10 ends because of transistor, so node N4, N5 remain on respectively on L level (0) and the H level (VDD-Vth) by the transistor Q10～Q13 that constitutes trigger (latch).

And then because of node N6 is that H level, node N7 are the L level, so transistor Q19 conducting, transistor Q18 ends, and node N8 becomes the L level.Equally, because of transistor Q21 conducting, transistor Q20 ends, so node N9 (/VFR) also become the L level.In addition, because of node N5 is that H level, node N8 are the L level, so transistor Q22 conducting, transistor Q23 ends, and node N10 (VFR) becomes H level (VDD-2 * Vth).

Then, at moment t41, when drive signal GSm+1 and clock signal clk Y became L level (0) respectively, Q16 ended because of transistor, so node N7 does not have the rising of voltage Δ V9 part, current potential becomes 0V.Have, at this moment, the level of node N4～N6, N8～N10 is constant again.

Then, at moment t42, when clock signal/CLKY became the H level, the level of node N5 began to rise from VDD-Vth by the capacitive coupling of boost capacitor C2.At this moment, because of the effect as the transistor Q25 of clamp element, the level of node N5 is fixed on the VDD+Vth.As a result, transistor Q14, Q22 carry out unsaturation work, and the level of node N6 and node N10 (VFR) becomes VDD respectively.Equally, node N7 boosts by the capacitive coupling of boost capacitor C1, and transistor Q17 conducting so this rises just little by little (Δ V10 shown in Figure 23), in addition, when clock signal/CLKY rises fully, is just returned 0V.Like this, node N7 maintains the L level, so transistor Q10, Q18, Q20 keep and end, the L level (0) of node N4, N8, N9 is maintained.

At moment t43, when clock signal/CLKY becomes the L level, the voltage Δ V11 that the level of node N5 is stipulated from VDD+Vth decline because of the capacitive coupling of boost capacitor C2.Thus, transistor Q14, N22 end, and still, the level of node N6, N10 (VDD) is kept by the stray capacitance that is attached to each node, all remains on the H level.On the other hand, the level of node N7 still, just turns back to 0V because of the capacitive coupling of boost capacitor C1 changes the voltage Δ V12 that stipulates to negative direction when clock signal/CLKY descends fully.Like this, because of node N6 maintains the H level, node N7 maintains the L level, so node N9 maintains L level (0).

Then, at moment t44, when clock signal CLKY becomes the H level once more, transistor Q12 conducting, the level of node N5 is got back to VDD-Vth.In addition, also conducting of transistor Q16, node N7 becomes than low potential side power supply potential (0) and exceeds the state of voltage Δ V9, but still maintains the L level.At this moment, the level of node N4, N8～N10 does not change.

And at moment t45, when clock signal CLKY got back to the L level, transistor Q12 ended, so node N5 becomes the H level (VDD-Vth) under the floating state.In addition, transistor Q16 also ends, and node N7 does not have the rising of voltage Δ V9 part, and current potential becomes 0V.At this moment, the level of node N4, N8～N10 does not change.

After this, before drive signal GSm+1 is activated once more during, on node N4～N10, whenever clock signal clk Y ,/when CLKY is transfused to, repeat the work of above-mentioned moment t42～t45.That is, during this period, node N4～N10 keeps its logical value (H level or L level).

Secondly, when start signal STY became the H level, the level of node N8 became L level (0), so, impact damper 22d become with Figure 23 in moment t30～t35 shown in the waveform work opposite with level.Therefore, and then after this 1 image duration, when drive signal GSm+1 becomes the H level, become with Figure 23 in moment t40～t45 shown in the waveform work opposite with level.That is, when drive signal GSm+1 is activated, frequency dividing circuit 20d just make fractional frequency signal VFR ,/VFR reverses respectively.Therefore, fractional frequency signal VFR ,/VFR has the cycle of 1 image duration.

By above work as can be known, in the frequency dividing circuit 20d of present embodiment, for example, when node N1 when the L level becomes the H level, roughly meanwhile, transistor Q2 conducting, transistor Q4 ends.On the contrary, when node N1 when the H level becomes the L level, roughly meanwhile, transistor Q2 ends, transistor Q4 conducting.Therefore, the problem of delaying work that thereupon occurs producing during as the frequency dividing circuit 20 of embodiment 6 (Figure 20), power consumption increase and due to leakage current cause when the circuit that uses Fig. 7, Figure 12, Figure 14 and Figure 15.

In addition, because of the groundwork of the frequency dividing circuit 20d of present embodiment is identical with the work that utilizes Fig. 5 to illustrate, so this frequency dividing circuit 20d also goes for the display device of Fig. 4 and Figure 10.

And then, because of having, the frequency dividing circuit 20d of Figure 22 is used for corresponding boost capacitor C3, the C4 that node N2, N11 are boosted with clock signal clk Y, so can make transistor Q2, Q7 be operated in non-saturated region when each node N1, N3 charging, the H electrical level rising that can make these nodes N1, N3 is to VDD.Particularly, the grid of transistor Q2, Q4 is transfused to clock signal/CLKY and becomes the H level repeatedly, so its threshold voltage drifts about easily.Therefore, thus the current potential of the H level that the driving force of transistor Q2, Q4 is descended make node N1, N2 descends.But,, can address this problem by the effect of above-mentioned boost capacitor C3, C4.

In addition, when boost capacitor C3, C4 make node N2, when N11 boosts, utilize as the transistor Q29 of clamp element, the effect of Q30, can prevent that the level of this node N2, N11 from surpassing VDD+Vth.Therefore, utilize this work of boosting to prevent the increase of the threshold voltage shift of transistor Q2, Q4.

Have again, in the driving of the frequency dividing circuit 20d of present embodiment, also use output signal (drive signal GSm+1) different with the single-place shift register that drives pixel, the other single-place shift register SRm+1 that is provided with to be used for the driving of frequency dividing circuit 20, but the output signal of the single-place shift register of regulation that also can dual-purpose driving grid line drives frequency dividing circuit 20.This comes, and has the advantage that need not setting unit shift register SRm+1.But, because of the load of the single-place shift register of the driving of carrying out frequency dividing circuit 20 increases, so should attention can bring the slack-off shortcoming of actuating speed of the gate line that makes its driving.

＜embodiment 8 〉

Figure 24 is the block scheme that the summary of the display device of expression embodiment 8 constitutes.(Figure 20) is the same with embodiment 6, the display device of present embodiment also possess m root gate lines G 1, G2 ... Gm, they are driven by a gate drivers 13 entirely.But, in the present embodiment, and then 2 grades single-place shift register SRm+1, SRm+2 are set in the back of final stage (m level).Though this both signal is not the signal of driving grid line,, for convenience of description, respectively they are called " drive signal GSm+1 " and " drive signal GSm+2 ".In addition, be used for virtual single-place shift register SRD that this single-place shift register SRm+2 is resetted in the next stage setting of single-place shift register SRm+2.

In the present embodiment, use these drive signals GSm+1 and drive signal GSm+2 to drive frequency dividing circuit 20.That is,, the start signal STY that imports frequency dividing circuit 20 is replaced as drive signal GSm+2 to embodiment 6.Drive signal GSm+1 and drive signal GSm+2 have the cycle of 1 image duration, and, be the mutually different one group of signal of phase place.Therefore, in the present embodiment, by using the theory of Fig. 5 explanation, frequency dividing circuit 20 also can generate fractional frequency signal VFR with 1 cycle image duration ,/VFR.Figure 25 illustrates this work wave.The fractional frequency signal VFR of frequency dividing circuit 20 output ,/VFR is respectively in the counter-rotating of level repeatedly when drive signal GSm+1 is activated.

Have again, in the formation of Figure 24, for example, when the circuit that uses Fig. 7 during as frequency dividing circuit 20, to the grid input drive signal GSm+2 of transistor Q1, to the grid input drive signal GSm+1 of transistor Q9.Because of drive signal GSm+2 is the signal that is activated later at drive signal GSm+1, thus in other words, after drive signal GSm+2 activates to drive signal GSm+1 activate before during vacate the interval of 1 image duration.Therefore, exist in the problem of delaying work that power consumption increases and due to leakage current causes that the beginning of embodiment 7 had illustrated.Therefore, in the present embodiment, also preferably use the frequency dividing circuit 20d of embodiment 7 (Figure 22).

But, in the present embodiment, also can will import frequency dividing circuit 20 again after drive signal GSm+1 and the drive signal GSm+2 exchange.That is, for example, in the frequency dividing circuit 20 of Fig. 7, also can be to the grid input drive signal GSm+1 of transistor Q1, to the grid input drive signal GSm+2 of transistor Q9.At this moment, because of just conducting after transistor Q1 conducting of transistor Q9, so there are not the problems referred to above.Therefore, also can use any frequency dividing circuit among Fig. 7, Figure 12, Figure 14, Figure 15 and Figure 22.

In addition, in the present embodiment, also can replace the group of drive signal GSm+1, drive signal GSm+2, drive frequency dividing circuit 20 and the output signal of 2 single-place shift registers of the regulation of driving grid line is used for.This comes, and has the advantage that need not setting unit shift register SRm+1, SRm+2.But, because of the load of the single-place shift register of the driving of carrying out frequency dividing circuit 20 increases, so should attention can bring the slack-off shortcoming of actuating speed of the gate line that makes its driving.

Claims (22)

1. display device, possess: dielectric substrate, be provided in a plurality of pixels on the above-mentioned dielectric substrate, drive the gate drivers of above-mentioned pixel, to the Drive and Control Circuit of the control signal of above-mentioned gate drivers output regulation with signal frequency is carried out the frequency dividing circuit of frequency division, it is characterized in that

Above-mentioned pixel, above-mentioned gate drivers and above-mentioned frequency dividing circuit use the thin film transistor (TFT) (TFT) that forms on above-mentioned dielectric substrate to constitute,

The above-mentioned control signal of above-mentioned Drive and Control Circuit output comprises the corresponding start signal of beginning with image duration of picture signal,

Above-mentioned frequency dividing circuit generates the fractional frequency signal that has the cycle behind the above-mentioned start signal frequency division.

2. the display device of claim 1 record is characterized in that, the TFT that uses in above-mentioned pixel, above-mentioned gate drivers and the above-mentioned frequency dividing circuit is same conduction type.

3. the display device of claim 1 record is characterized in that, above-mentioned start signal comprises identical, phase place the mutually different the 1st of cycle and the 2nd start signal,

Above-mentioned frequency dividing circuit possesses the 1st, the 2nd and the 3rd transducer,

Above-mentioned the 1st transducer is accepted the output of above-mentioned the 3rd transducer, with above-mentioned the 1st start signal the output of above-mentioned the 3rd transducer is reversed,

Above-mentioned the 2nd transducer is accepted the output of above-mentioned the 1st transducer, with above-mentioned the 2nd start signal the output of above-mentioned the 1st transducer is reversed,

Above-mentioned the 3rd transducer is accepted the output of above-mentioned the 2nd transducer, makes the output counter-rotating of above-mentioned the 2nd transducer.

4. the display device of claim 1 record is characterized in that, above-mentioned gate drivers is made of a plurality of shift registers that cascade connects,

Above-mentioned frequency dividing circuit possesses the 1st, the 2nd and the 3rd transducer,

Above-mentioned the 1st transducer is accepted the output of above-mentioned the 3rd transducer, with above-mentioned start signal the output of above-mentioned the 3rd transducer is reversed,

Above-mentioned the 2nd transducer is accepted the output of above-mentioned the 1st transducer, synchronously makes the output counter-rotating of above-mentioned the 1st transducer with the output signal of 1 shift register of regulation in above-mentioned a plurality of shift registers,

Above-mentioned the 3rd transducer is accepted the output of above-mentioned the 2nd transducer, makes the output counter-rotating of above-mentioned the 2nd transducer.

5. the display device of claim 4 record is characterized in that 1 shift register of afore mentioned rules is the shift register that is not used in the driving of above-mentioned pixel in above-mentioned a plurality of shift register.

6. the display device of claim 1 record is characterized in that, above-mentioned gate drivers is made of a plurality of shift registers that cascade connects,

Above-mentioned frequency dividing circuit possesses the 1st, the 2nd and the 3rd transducer,

Above-mentioned the 1st transducer is accepted the output of above-mentioned the 3rd transducer, synchronously makes the output counter-rotating of above-mentioned the 3rd transducer with the output signal of the 1st shift register in above-mentioned a plurality of shift registers,

Above-mentioned the 2nd transducer is accepted the output of above-mentioned the 1st transducer, synchronously makes the output counter-rotating of above-mentioned the 1st transducer with the output signal of the 2nd shift register in above-mentioned a plurality of shift registers,

Above-mentioned the 3rd transducer is accepted the output of above-mentioned the 2nd transducer, makes the output counter-rotating of above-mentioned the 2nd transducer.

7. the display device of claim 6 record is characterized in that the above-mentioned the 1st and the 2nd shift register is the shift register that is not used in the driving of above-mentioned pixel in above-mentioned a plurality of shift register.

8. the display device of any one record in the claim 3 to 7 is characterized in that, above-mentioned frequency dividing circuit possesses: the 1st and the 2nd holding circuit makes the above-mentioned the 1st and the 2nd transducer keep its output level.

9. the display device of claim 8 record is characterized in that, the above-mentioned control signal of above-mentioned Drive and Control Circuit output comprises short clock signal image duration of the above-mentioned picture signal of period ratio,

The the above-mentioned the 1st and the 2nd holding circuit is respectively by keeping the above-mentioned the 1st and the incoming level of the 2nd transducer the 1st and the 2nd latch cicuit that its output level is kept,

At least one side of the above-mentioned the 1st and the 2nd latch cicuit possesses the 1TFT as load, and this 1TFT is connected the input node of corresponding transducer and the TFT between the hot side power supply,

Above-mentioned frequency dividing circuit also possesses: the 1st capacity cell, and an end is connected with the grid of above-mentioned 1TFT, and the other end is imported above-mentioned clock signal.

10. the display device of claim 9 record, it is characterized in that above-mentioned frequency dividing circuit also possesses: the 1st clamp element makes the grid potential of above-mentioned 1TFT be no more than specific value.

11. the display device of claim 10 record is characterized in that, above-mentioned the 1st clamp element is to be connected between the grid of above-mentioned 1TFT and the above-mentioned hot side power supply and TFT that diode connects.

12. the display device of any one record is characterized in that in the claim 3 to 7, the above-mentioned control signal of above-mentioned Drive and Control Circuit output comprises short clock signal image duration of the above-mentioned picture signal of period ratio,

Above-mentioned frequency dividing circuit also possesses: the 2nd capacity cell, and an end is connected with any one output node in above-mentioned the 1st to the 3rd transducer, and its other end is imported above-mentioned clock signal.

13. the display device of claim 12 record is characterized in that above-mentioned frequency dividing circuit also possesses: the 2nd clamp element makes the current potential of an above-mentioned end of above-mentioned the 2nd capacity cell be no more than specific value.

14. the display device of claim 13 record is characterized in that, above-mentioned the 2nd clamp element is to be connected between the above-mentioned end of above-mentioned the 2nd capacity cell and the above-mentioned hot side power supply and TFT that diode connects.

15. the display device of any one record is characterized in that in the claim 1 to 7, above-mentioned frequency dividing circuit constitutes: when making the level counter-rotating of above-mentioned fractional frequency signal, the level of the grid of all TFT in this frequency dividing circuit is counter-rotating just.

16. the display device of any one record is characterized in that in the claim 1 to 7, the above-mentioned control signal of above-mentioned Drive and Control Circuit output comprises short clock signal image duration of the above-mentioned picture signal of period ratio,

Above-mentioned frequency dividing circuit also possesses: 2TFT is to be connected the output node of above-mentioned fractional frequency signal and the TFT between the hot side power supply; And the 3rd capacity cell, an end is connected with the grid of above-mentioned 2TFT, and the other end is imported above-mentioned clock signal.

17. the display device of claim 16 record is characterized in that above-mentioned frequency dividing circuit also possesses: the 3rd clamp element makes the current potential of grid of above-mentioned 2TFT be no more than specific value.

18. the display device of claim 17 record is characterized in that, above-mentioned the 3rd clamp element be the grid that is connected above-mentioned 2TFT with above-mentioned hot side power supply between the TFT that is connected of diode also.

19. the display device of any one record is characterized in that in the claim 1 to 7, the above-mentioned control signal of above-mentioned Drive and Control Circuit output comprises short clock signal image duration of the above-mentioned picture signal of period ratio,

Above-mentioned frequency dividing circuit also possesses: resistive element is connected between the output node and hot side power supply of above-mentioned fractional frequency signal.

20. the display device of any one record is characterized in that in the claim 1 to 7, above-mentioned gate drivers possesses: the 3rd and 4TFT, and be 2 TFT that are connected parallel with one another between the lead-out terminal of this gate drivers and low potential side power supply,

The above-mentioned the 3rd and 4TFT become the state that alternately stops according to the above-mentioned fractional frequency signal of above-mentioned frequency dividing circuit output.

21. the display device of any one record is characterized in that in the claim 1 to 7, the display element that constitutes above-mentioned pixel is a liquid crystal cell.

22. the display device of any one record is characterized in that in the claim 1 to 7, the display element that constitutes above-mentioned pixel is an electroluminescent cell.

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