CN1417953A - Frequency converter circuit - Google Patents
Frequency converter circuit Download PDFInfo
- Publication number
- CN1417953A CN1417953A CN02150403A CN02150403A CN1417953A CN 1417953 A CN1417953 A CN 1417953A CN 02150403 A CN02150403 A CN 02150403A CN 02150403 A CN02150403 A CN 02150403A CN 1417953 A CN1417953 A CN 1417953A
- Authority
- CN
- China
- Prior art keywords
- frequency
- mentioned
- local
- local oscillation
- mixer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims abstract description 46
- 238000006243 chemical reaction Methods 0.000 claims abstract description 19
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002146 bilateral effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/16—Multiple-frequency-changing
- H03D7/161—Multiple-frequency-changing all the frequency changers being connected in cascade
- H03D7/163—Multiple-frequency-changing all the frequency changers being connected in cascade the local oscillations of at least two of the frequency changers being derived from a single oscillator
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J1/00—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general
- H03J1/0008—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general using a central processing unit, e.g. a microprocessor
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Superheterodyne Receivers (AREA)
- Transmitters (AREA)
Abstract
The present inventive frequency conversion circuit reduces phase noise at frequency conversion, by providing each stage with a mixer, a local oscillator and PLL circuit. The frequency conversion circuit is provided with several mixers 1, 4 and 8, which are cascaded and several local oscillators 2, 6 and 10 which are set in response to the mixers 1, 4 and 8 and which supply local oscillation signals. Several PLL circuits 3, 7 and 11 for controlling the local oscillation frequency of the local oscillators 2, 6 and 10 are provided, in response to the local oscillators 2, 6 and 10. The local oscillators 2, 6 and 10 are made to oscillate at intervals of step frequencies set for the PLL circuits 3, 7 and 11 and the order to the size of the local oscillation frequencies and the order of the size of the step frequencies are made the same.
Description
Technical field
The present invention relates to frequency-conversion circuit, particularly as the transmitter equifrequent translation circuit of the transmission signal of the bilateral system that is used to utilize digital terrestrial broadcasting.
Background technology
According to Fig. 2 existing frequency-conversion circuit is described.This frequency-conversion circuit constitutes by three sections, at the signal of the 1st section frequency mixer 21 input 10MHz with from the local oscillation signal of the 1st local oscillator 22.The 10MHz signal of input is looked the hearer and is sent.(phase-locked loop: Phase Locked Loop) the frequency of oscillation Be Controlled of circuit 23, the 1 local oscillators 22 is fixed on 40MHz by 1PLL.In addition, be transformed into the signal of 50MHz from 21 outputs of the 1st section frequency mixer.
The 2nd section frequency mixer 24 is connected with the 1st section frequency mixer 21 by band pass filter 25.Be transformed into the signal of 50MHz and from the local oscillation signal of the 2nd local oscillator 26 in the 2nd section frequency mixer 24 input.Frequency of oscillation by 2PLL circuit 27, the 2 local oscillators 26 is controlled in fixing 1000MHz.In addition, be transformed into the signal of 950MHz from 24 outputs of the 2nd section frequency mixer.
Final stage i.e. the 3rd section frequency mixer 28 is connected with the 2nd section frequency mixer 24 by band pass filter 29.The 950MHz signal that is transformed in the 3rd section frequency mixer 28 input and from the local oscillation signal of the 3rd local oscillator 30.The frequency of oscillation of the 3rd local oscillator 30 is controlled in the scope of 1350MHz～1850MHz by 3PLL circuit 31 and step (STEP) is 0.125MHz.Output signal frequency is spaced apart the step frequency 0.125MHz of 3PLL circuit 28.
Each PLL circuit 23,27,31 is by microprocessor 32 control, from the frequency of the signal of the 3rd section frequency mixer 28 outputs data setting by input microprocessor 32.
Aforesaid frequency-conversion circuit is to use with interval 0.125MHz arbitrary signal that arrange, 400MHZ～900MHz to send, so cause the major issue of phase noise because of frequency interval is narrow and small.Phase noise is by the relation between the step frequency of local oscillation frequency and PLL circuit decision, is represented by the logarithm of the ratio (F/S) of local oscillation frequency F and step frequency S.And phase noise becomes with this value and worsens greatly.Frequency by above-mentioned the 3rd local oscillator that constitutes is the highest, but because the step frequency of its pairing PLL circuit will become the step frequency of output signal, so even the minimum value of above-mentioned ratio 10800 (=1350/0.125) is still very big, phase noise worsens.
Summary of the invention
Phase noise when the objective of the invention is to be respectively each section design frequency mixer, local oscillator and PLL circuit with the reduction frequency translation.
Solution to the problems described above of the present invention is, the a plurality of frequency mixers and the corresponding above-mentioned frequency mixer that frequency-conversion circuit of the present invention are had be connected in series are set to a plurality of local oscillators that it provides local oscillation signal respectively, and corresponding above-mentioned local oscillator is provided with a plurality of PLL circuit of the local oscillation frequency of above-mentioned each local oscillator of control, make of the interval vibration of above-mentioned local oscillator, and the size order of above-mentioned local oscillation frequency is identical with the size order of above-mentioned step frequency with the step frequency of above-mentioned each PLL circuit setting.
And, in the above-mentioned PLL circuit, the above-mentioned oscillator corresponding with the PLL circuit that is configured to minimum step frequency vibrated in predetermined frequency range.
And, set the step frequency interval that is spaced apart above-mentioned minimum of the step frequency of PLL circuit corresponding in the above-mentioned PLL circuit with above-mentioned the 1st section frequency mixer.
Description of drawings
Fig. 1 is the block diagram that expression frequency-conversion circuit of the present invention constitutes.
Fig. 2 is the block diagram that the existing frequency-conversion circuit of expression constitutes.
The figure number explanation
1 the 1st section frequency mixer
2 the 1st local oscillators
3 1PLL circuit
4 the 2nd frequency mixers
5 the 1st band pass filters
6 the 2nd local oscillators
7 2PLL circuit
8 final stage frequency mixers (the 3rd section local oscillator)
9 the 2nd band pass filters
10 the 3rd local oscillators
11 3PLL circuit
12 microprocessors
Embodiment
Describe according to Fig. 1 and table 1 pair of frequency-conversion circuit of the present invention.Frequency-conversion circuit of the present invention constitutes by three sections.In the 1st section frequency mixer 1 input from looking 10MHz signal that the hearer replys and from the local oscillation signal of the 1st local oscillator 2.The 1st local oscillator 2 is controlled so as in 40MHz～40.875MHz frequency range by 1PLL circuit 3 and vibrates with the step of 0.125MHz.And, be transformed into the signal that is roughly 50MHz, 0.125MHz optional frequency at interval from 21 outputs of the 1st section frequency mixer.
The 2nd section frequency mixer 4 is connected with the 1st section frequency mixer 1 by the 1st band pass filter 5.Be transformed the signal of the optional frequency that is roughly 50MHz～50.875MHz and from the local oscillation signal of the 2nd local oscillator 6 in the 2nd section frequency mixer 4 input.Frequency of oscillation by 2PLL circuit 7, the 2 local oscillators 6 is controlled as 999MHz or 1000MHz.And, export the signal that is about 950MHz, 0.125MHz optional frequency at interval through conversion from the 2nd section frequency mixer 4.
Final stage i.e. the 3rd section frequency mixer 8 is connected with the 2nd section frequency mixer 4 by the 2nd band pass filter 9.In the 3rd section frequency mixer 8 input through the signal of the about 950MHz of conversion with from the local oscillation signal of the 3rd local oscillator 10.Frequency of oscillation by 3PLL circuit 11, the 3 local oscillators 10 is controlled so as in 1350MHz～1850MHz scope the step vibration with 2MHz.And, export the signal that is for conversion into 400MHz～900MHz scope from the 3rd section frequency mixer 8.Output signal frequency is spaced apart 0.125MHz.
Each PLL circuit 3,7,11 is by microprocessor 12 control, from the signal frequency of the 3rd section frequency mixer 8 outputs data setting by input microprocessor 32.
Below by table 1, the relation of the frequency of oscillation (the 3rd local oscillation frequency OSC3) of the frequency of oscillation (the 2nd local oscillation frequency OSC2) of frequency of oscillation (the 1st local oscillation frequency OSC1), the 2nd local oscillator 6 of the 1st local oscillator 2 of the 3rd section mixer output signal frequency of correspondence (output frequency OUT) and the 3rd local oscillator 10 be described.
Table 1
At first, if output frequency (OUT) is 400MHz, then the 1st local oscillation frequency (OSC1) to the 3rd local oscillation frequency (OSC3) is respectively 40MHz, 100MHz, 1350MHz.In addition, increasing the 1st local oscillation frequency (OSC1) with output frequency (OUT) also increases with the interval of 0.125MHz, and when output frequency (OUT) increase 1MHz became 401MHz, the 1st local frequencies (OSC1) resetted and gets back to 40MHz.Simultaneously, the 2nd local oscillation frequency (OSC2) reduction is set to 999MHz.
Equally, (OUT) becomes 401.875MHz up to output frequency, and the 1st local oscillation frequency (OSC1) increases with the 0.125MHz step.In addition, when being increased to 402MHz, the 1st local oscillation frequency (OSC1) resets when getting back to 40MHz, and the 2nd local oscillation frequency (OSC2) also resets and gets back to 1000MHz.Simultaneously, the 3rd local oscillation frequency (OSC3) increase 2MHz is set to 1352MHz.
Below similarly, the every increase 1MHz of output frequency (OUT), the 1st local oscillation frequency (OSC1) just resets and turns back to initial value, and the 2nd local oscillation frequency (OSC2) is reciprocal at 1000MHz and 999MHz.And the 2nd local oscillation frequency (OSC3) also increases 2MHz with the every increase 2MHz of output frequency (OUT).
According to the relation of above each local oscillation frequency, output frequency (OUT) is set to the arbitrary value of 0.125MHz step between 400MHz～900MHz.
In addition, in the present invention, the ratio of the frequency of oscillation of 320 (=40/0.125), the 2nd local oscillator 6 and step frequency is about the frequency of oscillation of 1000 (=1000/1), the 3rd local oscillator 10 and the ratio of step frequency is about 800 (=1600/2) because the ratio of the frequency of oscillation of the 1st local oscillator 2 and step frequency is about, so all the summation of ratios is shown as 2120.This value is about 1/5 of prior art.Therefore, phase noise can be improved greatly.
The invention effect
In sum, the present invention has following effect. Because the present invention has be connected in series many Individual frequency mixer and corresponding above-mentioned frequency mixer are set to respectively it provides the many of local oscillation signal Individual local oscillator, and corresponding above-mentioned local oscillator arranges above-mentioned each local oscillator of control A plurality of PLL circuit of local oscillation frequency make above-mentioned local oscillator with above-mentioned each PLL electricity The interval vibration of the step frequency that the road is set, and the size order of above-mentioned local oscillation frequency and upper The size order of stating the step frequency is identical, so the level of phase noise is lower.
And, in the PLL circuit, make and the PLL circuit that is configured to minimum step frequency Corresponding oscillator vibrates in predetermined frequency range, so can be from the final stage frequency mixer Output is with the continuous signal of minimum step frequency interval.
And, with the interval of the step frequency of the PLL circuit of corresponding the 1st section above-mentioned frequency mixer Be set at minimum step frequency interval, so from the frequency of final stage mixer output signal Frequency height than the signal of importing the 1st section frequency mixer.
Claims (3)
1. a frequency-conversion circuit comprises: a plurality of frequency mixers that are connected in series; And corresponding above-mentioned each frequency mixer is provided with and provides a plurality of local oscillators of local oscillation signal; It is characterized in that: corresponding above-mentioned local oscillator is provided with the PLL circuit of the local oscillation frequency of above-mentioned each local oscillator of a plurality of controls, above-mentioned local oscillator is vibrated with the interval of the step frequency of above-mentioned each PLL circuit setting, and the size order of above-mentioned local oscillation frequency is identical with the size order of above-mentioned step frequency.
2. according to the frequency-conversion circuit of claim 1, it is characterized in that: in the above-mentioned PLL circuit, make the above-mentioned oscillator corresponding, in predetermined frequency range, vibrate with the PLL circuit that is configured to minimum step frequency.
3. according to the frequency-conversion circuit of claim 2, it is characterized in that: the interval of the step frequency of the PLL circuit of corresponding the 1st section above-mentioned frequency mixer is set to the interval of the step frequency of above-mentioned minimum.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001343802 | 2001-11-08 | ||
| JP2001343802A JP2003152561A (en) | 2001-11-08 | 2001-11-08 | Frequency conversion circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1417953A true CN1417953A (en) | 2003-05-14 |
Family
ID=19157423
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN02150403A Pending CN1417953A (en) | 2001-11-08 | 2002-11-08 | Frequency converter circuit |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US20030087619A1 (en) |
| EP (1) | EP1335488A3 (en) |
| JP (1) | JP2003152561A (en) |
| CN (1) | CN1417953A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102611441A (en) * | 2012-03-07 | 2012-07-25 | 北京无线电计量测试研究所 | Ultralow phase noise reference signal generating device for frequency synthesizer |
| CN105162464A (en) * | 2013-09-03 | 2015-12-16 | 联发科技（新加坡）私人有限公司 | Frequency and phase conversion circuit, wireless communication unit, integrated circuit and method therefor |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060176944A1 (en) * | 2005-02-10 | 2006-08-10 | Avo Multi-Amp Corporation D/B/A Megger | Synthesizer design for network testing device |
| FR2894737B1 (en) * | 2005-12-13 | 2008-03-14 | Cnes Epic | TEST BENCH, SIMULATOR AND METHOD FOR SIMULATING PHASE NOISE. |
| US8027656B2 (en) * | 2007-09-24 | 2011-09-27 | Broadcom Corporation | Method and system for a distributed transceiver for high frequency applications |
| US8019313B2 (en) * | 2007-09-24 | 2011-09-13 | Broadcom Corporation | Method and system for distributed transceivers based on notch filters and passive mixers |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54139316A (en) * | 1978-04-20 | 1979-10-29 | Matsushita Electric Ind Co Ltd | Am ssb transmitter/receiver |
| US5390346A (en) * | 1994-01-21 | 1995-02-14 | General Instrument Corporation Of Delaware | Small frequency step up or down converters using large frequency step synthesizers |
| US5572264A (en) * | 1994-02-14 | 1996-11-05 | Hitachi, Ltd. | High definition TV signal receiver |
| CN1082301C (en) * | 1994-09-10 | 2002-04-03 | 三星电子株式会社 | Digital radio transmission-reception apparatus |
| US6177964B1 (en) * | 1997-08-01 | 2001-01-23 | Microtune, Inc. | Broadband integrated television tuner |
| GB2320632B (en) * | 1996-12-23 | 2001-09-05 | Nokia Mobile Phones Ltd | Method and apparatus for transmitting and receiving signals |
| US6725463B1 (en) * | 1997-08-01 | 2004-04-20 | Microtune (Texas), L.P. | Dual mode tuner for co-existing digital and analog television signals |
| JP3250796B2 (en) * | 1998-05-26 | 2002-01-28 | 松下電器産業株式会社 | Receiving machine |
| DE19852676A1 (en) * | 1998-11-16 | 2000-05-25 | Bosch Gmbh Robert | Device for frequency synchronization in a communication system |
| JP2001044873A (en) * | 1999-07-29 | 2001-02-16 | Alps Electric Co Ltd | Double frequency converter |
| KR20010059868A (en) * | 1999-12-30 | 2001-07-06 | 윤종용 | Method for generating frequency in dual phase locked loop |
| GB0020528D0 (en) * | 2000-08-22 | 2000-10-11 | Mitel Semiconductor Ltd | Multiple conversion tuner |
-
2001
- 2001-11-08 JP JP2001343802A patent/JP2003152561A/en not_active Withdrawn
-
2002
- 2002-10-17 EP EP02257205A patent/EP1335488A3/en not_active Withdrawn
- 2002-11-07 US US10/289,625 patent/US20030087619A1/en not_active Abandoned
- 2002-11-08 CN CN02150403A patent/CN1417953A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102611441A (en) * | 2012-03-07 | 2012-07-25 | 北京无线电计量测试研究所 | Ultralow phase noise reference signal generating device for frequency synthesizer |
| CN105162464A (en) * | 2013-09-03 | 2015-12-16 | 联发科技（新加坡）私人有限公司 | Frequency and phase conversion circuit, wireless communication unit, integrated circuit and method therefor |
| CN105162464B (en) * | 2013-09-03 | 2018-06-22 | 联发科技（新加坡）私人有限公司 | Frequency and phase conversion circuit, wireless communication unit, integrated circuit and method |
Also Published As
| Publication number | Publication date |
|---|---|
| US20030087619A1 (en) | 2003-05-08 |
| EP1335488A3 (en) | 2003-09-17 |
| JP2003152561A (en) | 2003-05-23 |
| EP1335488A2 (en) | 2003-08-13 |
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| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| AD01 | Patent right deemed abandoned | ||
| C20 | Patent right or utility model deemed to be abandoned or is abandoned |