CN102707083A - Motor speed calculating method - Google Patents
Motor speed calculating method Download PDFInfo
- Publication number
- CN102707083A CN102707083A CN2012102242595A CN201210224259A CN102707083A CN 102707083 A CN102707083 A CN 102707083A CN 2012102242595 A CN2012102242595 A CN 2012102242595A CN 201210224259 A CN201210224259 A CN 201210224259A CN 102707083 A CN102707083 A CN 102707083A
- Authority
- CN
- China
- Prior art keywords
- pulse
- signal
- pulse input
- input
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Control Of Electric Motors In General (AREA)
Abstract
The invention discloses a motor speed calculating method, which carries out low-pass filter treatment on pulse input A and pulse input B. Each one of the filtered pulse input A and pulse input B is output in two paths for pulse selection and direction judgment. In the direction judgment, a current speed direction is judged according to a phase difference of the pulse input A and the pulse input B, and a direction signal is output. In the pulse selection, one pulse suitable for calculation is selected from the pulse input A and the pulse input B and is output by dividing into three paths for frequency calculation, zero-speed judgment and duty ratio calculation. In the zero-speed judgment, a zero-speed identifier is output when a current speed sensor has no output pulse. In the frequency calculation, a pulse frequency is processed, calculated and output. In the duty ratio calculation, a duty ratio signal under the current pulse is processed, calculated and output.. With the adoption of the motor speed calculating method provided by the invention, the technical problems that the motor speed calculating method in the prior art has low instantaneity, accuracy and stability, and is not suitable for multipath input signal treatment and parallel calculation function can be solved.
Description
Technical field
The present invention relates to a kind of control method of motor, especially relate to a kind of speed calculation method of multifunctional modular motor.
Background technology
The speed pickup of main flow all is a pulsed at present, promptly characterizes current velocity of rotation and direction with a set of pulses, and the user need calculate the frequency and the phase relation of pulse, to draw actual speed and direction.For present most controllers, rate signal is important key parameter, as long as there be the inaccurate of short time will cause significant trouble.And in actual application, rate signal often is subject to disturb, and polytrope is arranged, and this just requires its acquiring and processing method must possess real-time, accuracy, stability and anti-interference.
Existing computing method are to use the pulse capture module of processor to receive signal, and calculate cycle of pulse through the form of interrupting, and are aided with processing means such as filtering, calculating again and finally draw velocity amplitude, do not possess direction determining and dutycycle computing function.Because prior art uses processor and software language to realize, stable and the real-time of calculating will lean on the optimization degree of performance of processors and software language to guarantee, have risk.Because prior art uses the interrupt mode of processor to calculate, when pulsed frequency is higher, the frequent response of processor is interrupted, thereby taken a large amount of processor resources, even make it at a standstill.Because prior art uses the capture module of processor to carry out the reception of pulse; So be subject to the hardware resource of processor itself; When the input pulse number more for a long time; System will need the cooperation of multi-disc processor could accomplish the reception of all input pulses, and this has increased cost on the one hand greatly, also makes the synchronism of these speed sampling values receive loss on the other hand.Simultaneously, prior art does not also possess the velocity reversal decision-making function, does not possess the zero-speed decision-making function, does not possess the pulse duty factor computing function.
Summary of the invention
The purpose of this invention is to provide a kind of motor speed computing method, real-time, accuracy and stability that this method has solved the prior art existence are not high, are not suitable for the technical matters of processing of multichannel input signal and concurrent operation function.
In order to realize the foregoing invention purpose, the present invention specifically provides a kind of technic relization scheme of motor speed computing method, and this method specifically may further comprise the steps:
S10: will import B with pulse from one group of speed pulse signal pulse input A of the speed pickup of motor output and carry out low-pass filtering treatment;
S11: will pass through the pulse input A and the output of pulse input B each minute two-way of Filtering Processing; Wherein one road treated pulse input A and pulse input B carry out the pulse choice processing, other one road treated pulse input A and pulse input B travel direction determination processing;
S12: when treated pulse input A and pulse input B travel direction determination processing, judge current velocity reversal according to the phase differential of pulse input A and pulse input B, and direction signal is exported; When treated pulse input A and pulse input B carry out the pulse choice processing; From pulse input A and two pulses of pulse input B, selecting a pulse input signal that is fit to calculate divides three the tunnel to export respectively; One road pulse input signal carries out frequency computation part to be handled; One road pulse input signal carries out the zero-speed determination processing, and one road pulse input signal carries out the dutycycle computing;
S13: one road pulse input signal carries out the zero-speed determination processing, when judging current speed pickup no-output pulse, and output zero-speed id signal; When one road pulse input signal carries out the frequency computation part processing, calculate and the output pulse frequency signal; When one road pulse input signal carries out the dutycycle computing, calculate and export current duty of ratio signal.
As the further improvement of a kind of motor speed computing method of the present invention technical scheme, the motor speed computing method are moved based on FPGA, and pulse input A and pulse input B are from the IO pin input of said FPGA, and low-pass filtering treatment is carried out in the inside of FPGA.
Further improvement as a kind of motor speed computing method of the present invention technical scheme; Pulse input A and pulse input B through low-pass filtering treatment carry out the pulse choice processing; The pulse choice processing is selected a pulse input signal that is fit to calculate according to following rule and is divided three tunnel outputs, carries out frequency computation part processing, zero-speed determination processing and dutycycle computing respectively:
When pulse input A existed with pulse input B simultaneously, A was imported in the output pulse;
A is normal when the pulse input, when pulse input B loses, and output pulse input A;
B is normal when the pulse input, when pulse input A loses, and output pulse input B.
Further improvement as a kind of motor speed computing method of the present invention technical scheme; When treated pulse input A and pulse input B travel direction determination processing, the process of judging current velocity reversal according to the phase differential of pulse input A and pulse input B further may further comprise the steps:
S121: judge at the rising edge of input system clock whether pulse input A rising edge occurred in last system clock cycle, if then composite pulse output transfers high level to; If pulse input B rising edge occurred in last system clock cycle, then composite pulse output transfers low level to;
S122: the high level time that calculates composite pulse output; And the cycle of calculating pulse input A; The high level time that the cycle that A is imported in pulse dwindles after half with composite pulse output again compares; If the half the high level time less than composite pulse output in pulse input A cycle, the dutycycle that composite pulse output then is described is then exported the A turn signal greater than 50%; If the half the high level time greater than composite pulse output in pulse input A cycle is then exported the B turn signal.
As the further improvement of a kind of motor speed computing method of the present invention technical scheme, from two pulses of pulse input A and pulse input B, select the process that a pulse input signal that is fit to calculate carries out the frequency computation part processing and further may further comprise the steps:
S131: after the rising edge of pulse input signal arrives, at first count, will pass through the clocking value that counts to get and latch, and the cycle of a last pulse is latched as the cycle of this subpulse;
S132: when next pulse input signal is imported, restart counting, carry out timing next time; The periodic quantity of the periodic quantity of this subpulse and a last pulse is subtracted each other and is compared, if fiducial value greater than a preset maximum period of change limit value, then the recurrence interval value signal Period of output is the periodic quantity of a last pulse; If fiducial value is less than a preset maximum period of change limit value, the recurrence interval value signal Period that then exports is the periodic quantity of subpulse for this reason;
S133: recurrence interval value signal Period and computation period preset value compare, and, then the recurrence interval value signal of input is sued for peace less than the computation period preset value as if the recurrence interval value signal, and pulse number signal Num is carried out from adding 1 operation;
S134: when the recurrence interval value signal summing value of input during greater than the computation period preset value; The signal of computation period signal Time for the recurrence interval value signal of input is sued for peace; Divide operations is carried out in pulse number signal Num and computation period signal Time output, and will carry out result and the pulse number signal Num of sum operation all zero clearings of result the recurrence interval value signal of input from add operation;
S135: if the recurrence interval value signal is during greater than the computation period preset value; Then pulse number signal Num is 1; Computation period signal Time is current pulse-period signal; And pulse number signal Num and computation period signal Time output carried out divide operations, and with computation period signal Time and all zero clearings of pulse number signal Num;
S136: divide operations result's output signal carries out output pulse frequency signal after the Filtering Processing.
As the further improvement of a kind of motor speed computing method of the present invention technical scheme, from two pulses of pulse input A and pulse input B, select the process that a pulse input signal that is fit to calculating carries out the zero-speed determination processing and further may further comprise the steps:
The rising edge of paired pulses input signal is caught and is carried out timing and operate; Timing operation output signal compares with preset maximum impulse periodic signal; If do not receive the rising edge of pulse input signal in the cycle, promptly think the no pulse input, and judge that the speed of this moment is zero in maximum impulse; The output of present speed sensor no pulse, and output zero-speed sign.
As the further improvement of a kind of motor speed computing method of the present invention technical scheme, from two pulses of pulse input A and pulse input B, select the process that a pulse input signal that is fit to calculating carries out the dutycycle computing and further may further comprise the steps:
Calculate the high level time of pulse according to the pulse input signal of input,, pulse high level time signal and pulse-period signal are carried out division arithmetic, obtain the dutycycle of pulse input signal according to the cycle of the pulse input signal calculating pulse of importing.
Through implementing the technical scheme of a kind of motor speed computing method of the invention described above, have following technique effect:
(1) the present invention can handle the pulsed rate signal processing that reaches tens of ways simultaneously, and the pulsed frequency wide ranges that receives, and the velocity amplitude error of output is minimum;
(2) the accessible input pulse frequency range of the present invention is 0.1 ~ 500KHz, can satisfy most engineering demands, possesses higher applicability;
(3) the present invention can simultaneously treated input pulse quantity be 1 ~ 16 the tunnel, and under the condition that hardware can be supported, expands, and possesses higher practicality and cost performance;
(4) the velocity amplitude error of the present invention's output is very little, and the measurement error when the input pulse frequency is 10KHz is 0.005%, possesses high accuracy and resolution;
(5) the present invention possesses the velocity reversal decision-making function;
(6) the present invention possesses the zero-speed decision-making function;
(7) the present invention possesses the pulse duty factor computing function;
(8) the present invention is integrated in functions such as rate signal filtering, velocity amplitude calculating, the judgement of speed zero-speed, velocity reversal judgement, pulse duty factor calculating on the FPGA with hardware description language is modular; Can effectively utilize the FPGA aboundresources; Ability with high speed processing, concurrent operation, modular design possesses higher stability, confidentiality and integrated level simultaneously.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the system architecture diagram of a kind of embodiment of the applied motor speed calculation element of motor speed computing method of the present invention.
Fig. 2 is the working timing figure of a kind of embodiment low-pass filtering module of the applied motor speed calculation element of motor speed computing method of the present invention.
Fig. 3 is the working timing figure of a kind of embodiment direction determining of the applied motor speed calculation element of motor speed computing method of the present invention module.
Fig. 4 is the structural principle block diagram of a kind of embodiment pulse choice of the applied motor speed calculation element of motor speed computing method of the present invention module.
Fig. 5 is the structural principle block diagram of a kind of embodiment frequency computation part of the applied motor speed calculation element of motor speed computing method of the present invention module.
Fig. 6 is a kind of work wave synoptic diagram that possesses the speed pickup of direction deixis.
Fig. 7 is the structural principle block diagram of a kind of embodiment zero-speed of the applied motor speed calculation element of motor speed computing method of the present invention determination module.
Fig. 8 is the structural principle block diagram of a kind of embodiment dutycycle of the applied motor speed calculation element of motor speed computing method of the present invention computing module.
Among the figure: 1-low-pass filtering module, 2-pulse choice module, 3-direction determining module, 4-frequency computation part module, 5-zero-speed determination module, 6-dutycycle computing module; The 7-data outputting module, 31-pulse synthesizer, 32-timer one, 33-timer two, 34-comparer one; 401-timer three, 402-latch one, 403-latch two, 404-comparer two, 405-comparer three; 406-is from adding device one, and 407-is from adding device two, 408-subtracter, 409-divider one, 410-wave filter; 51-timer four, 52-comparer four, 61-pulse high level timer, 62-recurrence interval timer, 63-divider two.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment only is a part of embodiment of the present invention, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
A kind of motor speed computing method specifically may further comprise the steps:
S10: will import B with pulse from one group of speed pulse signal pulse input A of the speed pickup of motor output and carry out low-pass filtering treatment;
S11: will pass through the pulse input A and the output of pulse input B each minute two-way of Filtering Processing; Wherein one road treated pulse input A and pulse input B carry out the pulse choice processing, other one road treated pulse input A and pulse input B travel direction determination processing;
S12: when treated pulse input A and pulse input B travel direction determination processing, judge current velocity reversal according to the phase differential of pulse input A and pulse input B, and direction signal is exported; When treated pulse input A and pulse input B carry out the pulse choice processing; From pulse input A and two pulses of pulse input B, selecting a pulse input signal that is fit to calculate divides three the tunnel to export respectively; One road pulse input signal carries out frequency computation part to be handled; One road pulse input signal carries out the zero-speed determination processing, and one road pulse input signal carries out the dutycycle computing;
S13: one road pulse input signal carries out the zero-speed determination processing, when judging current speed pickup no-output pulse, and output zero-speed id signal; When one road pulse input signal carries out the frequency computation part processing, calculate and the output pulse frequency signal; When one road pulse input signal carries out the dutycycle computing, calculate and export current duty of ratio signal.
Shown in accompanying drawing 1 to accompanying drawing 8, provided the specific embodiment of a kind of motor speed computing method of the present invention, below in conjunction with accompanying drawing and specific embodiment the present invention is described further.
Shown in accompanying drawing 1 is the embodiment of the applied motor speed calculation element of a kind of motor speed computing method of the present invention, and the motor speed calculation element comprises: low-pass filtering module 1, pulse choice module 2, direction determining module 3, frequency computation part module 4, zero-speed determination module 5, dutycycle computing module 6 and data outputting module 7.One group of velocity pulse from the output of the speed pickup of motor; Pulse input A and pulse input B input low-pass filtering module 1 carry out filtering, and the pulse input A of process Filtering Processing and pulse input B export direction determining module 3 and pulse choice module 2 respectively to.Direction determining module 3 is judged current velocity reversal according to the phase differential of pulse input A and pulse input B, and exports direction signal to data outputting module 7.Pulse choice module 2 is selected a pulse that is fit to calculate and is exported frequency computation part module 4, zero-speed determination module 5 respectively to from pulse input A and two pulses of pulse input B, and dutycycle computing module 6.The output zero-speed identified to data outputting module 7 when zero-speed determination module 5 was responsible for judging current speed pickup no-output pulse.Frequency computation part module 4 is responsible for calculating and output pulse frequency to data outputting module 7.Dutycycle computing module 6 is responsible for calculating and exporting current duty of ratio signal to data outputting module 7.
As a kind of preferred implementation; The motor speed calculation element is further based on FPGA (Field Programmable Gate Array; Field programmable gate array) design, pulse input A and pulse input B are one group of velocity pulse of speed pickup output.Pulse input A and pulse input B carry out filtering from the low-pass filtering module 1 that the IO pin of FPGA inputs to FPGA inside.Owing to when practical engineering application, exist electromagnetic environment abominable, speed pickup to control system transmission range is than many unfavorable factors such as length, and velocity pulse can produce the burr of high frequency because of external interference in transmission course.These burrs can have a strong impact on the accuracy of calculating, and shown in accompanying drawing 2, the described technical scheme of the specific embodiment of the invention uses low-pass filtering module 1 to remove burr.Wherein, t is minimum pulse-high level or the low level width that can pass through.Owing to adopted the design with hardware description language completion motor speed calculation element, made the described technical scheme of the specific embodiment of the invention have very high stability and high efficiency, and higher confidentiality is arranged based on FPGA.Based on structure flexibly that FPGA possessed and powerful processing power, reception that the present invention can be synchronous fully and computing possess high accuracy simultaneously than the multichannel input pulse, and the highest computational accuracy of reality can reach 0.005%.But, make the present invention can be transplanted to new design easily based on field programming and modular design function.
Pulse input A and the further input pulse of pulse input B through low-pass filtering module 1 filtering are selected module 2; Pulse choice module 2 is selected a pulse that is fit to calculate according to following rule and is exported frequency computation part module 4, zero-speed determination module 5 respectively to, and dutycycle computing module 6:
When pulse input A existed with pulse input B simultaneously, A were imported in the 2 output pulses of pulse choice module;
A is normal when the pulse input, when pulse input B loses, and pulse choice module 2 output pulse input A;
B is normal when the pulse input, when pulse input A loses, and pulse choice module 2 output pulse input B.
A lot of speed pickups possess the direction deixis; This function generally has the pulse of phase relation to realize through exporting two, works as signal A preceding like JT-2007-027D_JD118A type speed pickup regulation, and signal B has " A turns to " when the back; Otherwise " B turns to " arranged, shown in accompanying drawing 6.For distinguishing speed direction correctly, and avoid the influence that dutycycle and phase differential bring, direction determining module 3 also further comprises pulse synthesizer 31, timer 1, timer 2 33 and comparer 1.The present invention at first is provided with a pulse synthesizer 31, and its sequential chart is shown in accompanying drawing 3.Pulse synthesizer 31 judges at the rising edge of input system clock whether pulse input A rising edge occurred in last system clock cycle, if then composite pulse output transfers high level to.If pulse input B rising edge occurred in last system clock cycle, then composite pulse output transfers low level to.Timer 1 calculates the high level time of composite pulse output, and timer 2 33 calculates the cycle of pulse input A.The cycle of pulse input A compares through the high level time of comparer 1 with composite pulse output after dwindling half again; If the half the high level time in pulse input A cycle less than composite pulse output; The dutycycle that composite pulse output then is described is greater than 50%, then through comparer one 34 output A turn signals.If the half the high level time greater than composite pulse output in pulse input A cycle is then through comparer one 34 output B turn signals.FPGA realizes that schematic diagram is shown in accompanying drawing 4.
Frequency computation part module 4 is cores of whole invention technical scheme, mainly in order to realize the computing function of pulsed frequency.Its schematic diagram is shown in accompanying drawing 5.Frequency computation part module 4 also further comprise timer 3 401, latch 1, latch 2 403, comparer 2 404, comparer 3 405, certainly add device 1, add device 2 407, subtracter 408, divider 1, wave filter 410 and several MUX MUX certainly.MUX comprises the first MUX MUX1, the second MUX MUX2 and the 3rd MUX MUX3.Pulse input signal incoming frequency computing module 4 from pulse choice module 2; After the rising edge of pulse input signal arrives; Count by timer 3 401; Latch 1 latchs the clocking value of timer 3 401 as the cycle of this subpulse, latch 2 403 latchs the cycle of a last pulse.When next pulse input signal is imported, restart timer 3 401, carry out timing next time.Value in value in the latch 1 and the latch 2 403 is subtracted each other in subtracter 408 as comparing; If fiducial value is greater than a preset maximum period of change limit value; Then the recurrence interval value signal Period by first MUX MUX1 output is the value of latch 2 403; If fiducial value is less than a preset maximum period of change limit value, then the recurrence interval value signal Period by first MUX MUX1 output is the value of latch 1.Recurrence interval value signal Period and computation period preset value compare in comparer 2 404, if the recurrence interval value signal, adds device 2 407 certainly less than the computation period preset value recurrence interval value signal of input are sued for peace, and add device 1 certainly and add 1.When the recurrence interval value signal summing value of input during greater than the computation period preset value; The signal of computation period signal Time for the recurrence interval value signal of input is sued for peace; To export divider 1 to the computation period signal Time that exports by the 3rd MUX MUX3 by the pulse number signal Num of second MUX MUX2 output and carry out divide operations, and will add device 1 certainly and add all zero clearings of device 2 407 certainly.If the recurrence interval value signal is during greater than the computation period preset value; Then pulse number signal Num is 1; Computation period signal Time is current pulse-period signal; And will export divider 1 to by the pulse number signal Num of second MUX MUX2 output and computation period signal Time and carry out divide operations by the 3rd MUX MUX3 output, and will add certainly device 1 (add certainly and be pulse number signal Num in the device 1) with from adding all zero clearings of device 2 407 (add certainly and be computation period signal Time in the device 2 407).The output signal of divider 1 carries out output pulse frequency signal after the filtering via wave filter 410.
Output zero-speed sign when zero-speed determination module 5 is responsible for judging current speed pickup no pulse output.In embodiment of the present invention, be provided with a maximum impulse cycle; After maximum impulse does not receive the rising edge of pulse in the cycle, promptly think the no pulse input, and judge that the speed of this moment is zero; Output zero-speed sign, its principle is shown in accompanying drawing 7.Zero-speed determination module 5 also further comprises timer 4 51 and comparer 4 52.Pulse input signal input zero-speed determination module 5 from pulse choice module 2; The rising edge of timer 4 51 paired pulses input signals is caught, and the output timing signal of timer 4 51 compares in comparer 4 52 with preset maximum impulse periodic signal, after maximum impulse does not receive the rising edge of pulse in the cycle; Promptly think the no pulse input; And judge that speed at this moment is zero, the output of present speed sensor no pulse, and output zero-speed sign.
The function of dutycycle computing module 6 is to calculate each cycle length and the high level time of pulse input signal in real time, and high level time can be obtained dutycycle divided by the cycle, and its principle is shown in accompanying drawing 8.Dutycycle computing module 6 also further comprises pulse high level timer 61, recurrence interval timer 62 and divider 2 63, from the pulse input signal input duty cycle computing module 6 of pulse choice module 2.Pulse high level timer 61 calculates the high level time of pulse according to the pulse input signal of input; Recurrence interval timer 62 calculates the cycle of pulse according to the pulse input signal of input; By divider 2 63 will from the pulse high level time signal of pulse high level timer 61 with carry out division arithmetic from the pulse-period signal of recurrence interval timer 62, obtain the dutycycle of pulse input signal.
Signal definition in accompanying drawing 4,5,7,8 is following: CLK is a clock signal, and Input is an input signal, and Output is the output signal, and Reset is a reset signal, and Start is a commencing signal, and Enable is an enable signal, and Update is a update signal.
A kind of embodiment of utilizing the motor speed computing method that above-mentioned motor speed calculation element calculates, this method may further comprise the steps:
S10: import low-pass filtering module 1 from one group of speed pulse signal pulse input A of the speed pickup of motor output with pulse input B and carry out filtering;
S11: pulse input A and pulse input B through Filtering Processing export pulse choice module 2 and direction determining module 3 respectively to;
S12: direction determining module 3 is judged current velocity reversal according to the phase differential of pulse input A and pulse input B, and exports direction signal to data outputting module 7; Pulse choice module 2 is selected a pulse that is fit to calculate and is exported frequency computation part module 4, zero-speed determination module 5 respectively to from pulse input A and two pulses of pulse input B, and dutycycle computing module 6;
S13: when zero-speed determination module 5 was judged current speed pickup no-output pulse, the output zero-speed identified to data outputting module 7; Frequency computation part module 4 is calculated and output pulse frequency to data outputting module 7; Dutycycle computing module 6 calculates and exports current duty of ratio signal to data outputting module 7.
The motor speed computing method are moved based on FPGA, and pulse input A and pulse input B are from the IO pin input of said FPGA, and low-pass filtering treatment is carried out in the inside of FPGA.
Pulse input A and pulse input B input pulse through low-pass filtering module 1 Filtering Processing are selected module 2; Pulse choice module 2 is further selected a pulse that is fit to calculate according to following rule and is exported frequency computation part module 4, zero-speed determination module 5 respectively to, and dutycycle computing module 6:
When pulse input A existed with pulse input B simultaneously, A were imported in the 2 output pulses of pulse choice module;
A is normal when the pulse input, when pulse input B loses, and pulse choice module 2 output pulse input A;
B is normal when the pulse input, when pulse input A loses, and pulse choice module 2 output pulse input B.
The process that direction determining module 3 is judged current velocity reversal according to the phase differential of pulse input A and pulse input B further may further comprise the steps:
S121: pulse synthesizer 31 judges at the rising edge of input system clock whether pulse input A rising edge occurred in last system clock cycle, if then composite pulse output transfers high level to; If pulse input B rising edge occurred in last system clock cycle, then composite pulse output transfers low level to;
S122: timer 1 calculates the high level time of composite pulse output; Timer 2 33 calculates the cycle of pulse input A; The cycle of pulse input A compares through the high level time of comparer 1 with composite pulse output after dwindling half again; If the half the high level time less than composite pulse output in pulse input A cycle, the dutycycle that composite pulse output then is described are greater than 50%, then through comparer one 34 output A turn signals; If the half the high level time greater than composite pulse output in pulse input A cycle is then through comparer one 34 output B turn signals.
S131: from the pulse input signal incoming frequency computing module 4 of pulse choice module 2; After the rising edge of pulse input signal arrives; Count by timer 3 401; Latch 1 latchs the clocking value of timer 3 401 as the cycle of this subpulse, latch 2 403 latchs the cycle of a last pulse;
S132: when next pulse input signal is imported, restart timer 3 401, carry out timing next time; Value in value in the latch 1 and the latch 2 403 is subtracted each other in subtracter 408 as comparing; If fiducial value is greater than a preset maximum period of change limit value, then the recurrence interval value signal Period by first MUX MUX1 output is the value of latch 2 403; If fiducial value is less than a preset maximum period of change limit value, then the recurrence interval value signal Period by first MUX MUX1 output is the value of latch 1;
S133: recurrence interval value signal Period and computation period preset value compare in comparer 2 404, if the recurrence interval value signal, adds device 2 407 certainly less than the computation period preset value recurrence interval value signal of input are sued for peace, and add device 1 certainly and add 1;
S134: when the recurrence interval value signal summing value of input during greater than the computation period preset value; The signal of computation period signal Time for the recurrence interval value signal of input is sued for peace; Export pulse number signal Num and computation period signal Time to divider 1 and carry out value average period that divide operations obtains pulse input signal, and will add certainly device 1 with from adding all zero clearings of device 2 407;
S135: if the recurrence interval value signal is during greater than the computation period preset value; Then pulse number signal Num is 1; Computation period signal Time is current pulse-period signal; And export pulse number signal Num and computation period signal Time to divider 1 and carry out divide operations, and will add certainly device 1 with from adding all zero clearings of device 2 407;
S136: the output signal of divider 1 carries out output pulse frequency signal after the filtering via wave filter 410.
The process of output zero-speed sign further may further comprise the steps when zero-speed determination module 5 was judged current speed pickup no-output pulse:
Pulse input signal input zero-speed determination module 5 from pulse choice module 2; The rising edge of timer 4 51 paired pulses input signals is caught, and the output timing signal of timer 4 51 compares in comparer 4 52 with preset maximum impulse periodic signal, after maximum impulse does not receive the rising edge of pulse in the cycle; Promptly think the no pulse input; And judge that speed at this moment is zero, the output of present speed sensor no pulse, and output zero-speed sign.
The process that dutycycle computing module 6 calculated and exported current duty of ratio signal further may further comprise the steps:
Pulse input signal input duty cycle computing module 6 from pulse choice module 2; Pulse high level timer 61 calculates the high level time of pulse according to the pulse input signal of input; Recurrence interval timer 62 calculates the cycle of pulse according to the pulse input signal of input; By divider 2 63 will from the pulse high level time signal of pulse high level timer 61 with carry out division arithmetic from the pulse-period signal of recurrence interval timer 62, obtain the dutycycle of pulse input signal.
The present invention uses FPGA and hardware description language to accomplish design, and changes all algorithms into hardware circuit and be solidificated on the FPGA, possesses higher real-time, accuracy and stability.The present invention uses FPGA to calculate, and it possesses concurrency completely, and under the situation of FPGA internal resource abundance, can in 0.1 ~ 500KHz frequency range, reach the calculating of tens of way input pulses simultaneously.The present invention uses the igniter module of FPGA to carry out pulse capture, can walk abreast easily to catch the multichannel input pulse.The present invention possess at speed pickup support on the basis of corresponding function that velocity reversal is judged, zero-speed decision-making function and pulse duty factor computing function.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention, or are revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical scheme of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, be equal to replacement, equivalence changes and modify, all still belong in the scope that technical scheme of the present invention protects.
Claims (7)
1. motor speed computing method is characterized in that, may further comprise the steps:
S10: will import B with pulse from one group of speed pulse signal pulse input A of the speed pickup of motor output and carry out low-pass filtering treatment;
S11: will pass through the pulse input A and the output of pulse input B each minute two-way of Filtering Processing; Wherein one road treated pulse input A and pulse input B carry out the pulse choice processing, other one road treated pulse input A and pulse input B travel direction determination processing;
S12: when treated pulse input A and pulse input B travel direction determination processing, judge current velocity reversal according to the phase differential of pulse input A and pulse input B, and direction signal is exported; When treated pulse input A and pulse input B carry out the pulse choice processing; From pulse input A and two pulses of pulse input B, selecting a pulse input signal that is fit to calculate divides three the tunnel to export respectively; One road pulse input signal carries out frequency computation part to be handled; One road pulse input signal carries out the zero-speed determination processing, and one road pulse input signal carries out the dutycycle computing;
S13: one road pulse input signal carries out the zero-speed determination processing, when judging current speed pickup no-output pulse, and output zero-speed id signal; When one road pulse input signal carries out the frequency computation part processing, calculate and the output pulse frequency signal; When one road pulse input signal carries out the dutycycle computing, calculate and export current duty of ratio signal.
2. a kind of motor speed computing method according to claim 1; It is characterized in that: said motor speed computing method are moved based on FPGA; Pulse input A and pulse input B are from the IO pin input of said FPGA, and low-pass filtering treatment is carried out in the inside of FPGA.
3. a kind of motor speed computing method according to claim 2; It is characterized in that: pulse input A and pulse input B through low-pass filtering treatment carry out the pulse choice processing; The pulse choice processing is selected a pulse input signal that is fit to calculate according to following rule and is divided three tunnel outputs, carries out frequency computation part processing, zero-speed determination processing and dutycycle computing respectively:
When pulse input A existed with pulse input B simultaneously, A was imported in the output pulse;
A is normal when the pulse input, when pulse input B loses, and output pulse input A;
B is normal when the pulse input, when pulse input A loses, and output pulse input B.
4. according to the described a kind of motor speed computing method of arbitrary claim in the claim 1 to 3; It is characterized in that: when treated pulse input A and pulse input B travel direction determination processing, the process of judging current velocity reversal according to the phase differential of pulse input A and pulse input B further may further comprise the steps:
S121: judge at the rising edge of input system clock whether pulse input A rising edge occurred in last system clock cycle, if then composite pulse output transfers high level to; If pulse input B rising edge occurred in last system clock cycle, then composite pulse output transfers low level to;
S122: the high level time that calculates composite pulse output; And the cycle of calculating pulse input A; The high level time that the cycle that A is imported in pulse dwindles after half with composite pulse output again compares; If the half the high level time less than composite pulse output in pulse input A cycle, the dutycycle that composite pulse output then is described is then exported the A turn signal greater than 50%; If the half the high level time greater than composite pulse output in pulse input A cycle is then exported the B turn signal.
5. a kind of motor speed computing method according to claim 4 is characterized in that: from two pulses of pulse input A and pulse input B, select the process that a pulse input signal that is fit to calculate carries out the frequency computation part processing and further may further comprise the steps:
S131: after the rising edge of pulse input signal arrives, at first count, will pass through the clocking value that counts to get and latch, and the cycle of a last pulse is latched as the cycle of this subpulse;
S132: when next pulse input signal is imported, restart counting, carry out timing next time; The periodic quantity of the periodic quantity of this subpulse and a last pulse is subtracted each other and is compared, if fiducial value greater than a preset maximum period of change limit value, then the recurrence interval value signal Period of output is the periodic quantity of a last pulse; If fiducial value is less than a preset maximum period of change limit value, the recurrence interval value signal Period that then exports is the periodic quantity of subpulse for this reason;
S133: recurrence interval value signal Period and computation period preset value compare, and, then the recurrence interval value signal of input is sued for peace less than the computation period preset value as if the recurrence interval value signal, and pulse number signal Num is carried out from adding 1 operation;
S134: when the recurrence interval value signal summing value of input during greater than the computation period preset value; The signal of computation period signal Time for the recurrence interval value signal of input is sued for peace; Divide operations is carried out in pulse number signal Num and computation period signal Time output, and will carry out result and the pulse number signal Num of sum operation all zero clearings of result the recurrence interval value signal of input from add operation;
S135: if the recurrence interval value signal is during greater than the computation period preset value; Then pulse number signal Num is 1; Computation period signal Time is current pulse-period signal; And pulse number signal Num and computation period signal Time output carried out divide operations, and with computation period signal Time and all zero clearings of pulse number signal Num;
S136: divide operations result's output signal carries out output pulse frequency signal after the Filtering Processing.
6. a kind of motor speed computing method according to claim 5 is characterized in that: from two pulses of pulse input A and pulse input B, select the process that a pulse input signal that is fit to calculating carries out the zero-speed determination processing and further may further comprise the steps:
The rising edge of paired pulses input signal is caught and is carried out timing and operate; Timing operation output signal compares with preset maximum impulse periodic signal; If do not receive the rising edge of pulse input signal in the cycle, promptly think the no pulse input, and judge that the speed of this moment is zero in maximum impulse; The output of present speed sensor no pulse, and output zero-speed sign.
7. a kind of motor speed computing method according to claim 6 is characterized in that: from two pulses of pulse input A and pulse input B, select the process that a pulse input signal that is fit to calculating carries out the dutycycle computing and further may further comprise the steps:
Calculate the high level time of pulse according to the pulse input signal of input,, pulse high level time signal and pulse-period signal are carried out division arithmetic, obtain the dutycycle of pulse input signal according to the cycle of the pulse input signal calculating pulse of importing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201210224259 CN102707083B (en) | 2012-07-02 | 2012-07-02 | Motor speed calculating method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201210224259 CN102707083B (en) | 2012-07-02 | 2012-07-02 | Motor speed calculating method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102707083A true CN102707083A (en) | 2012-10-03 |
| CN102707083B CN102707083B (en) | 2013-10-09 |
Family
ID=46900019
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201210224259 Active CN102707083B (en) | 2012-07-02 | 2012-07-02 | Motor speed calculating method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102707083B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105628955A (en) * | 2015-12-25 | 2016-06-01 | 南京南瑞集团公司 | Speed measurement device for pump storage group static frequency converter and speed measurement method thereof |
| CN106089598A (en) * | 2016-06-02 | 2016-11-09 | 三重型能源装备有限公司 | A kind of wind power generator rotor detection method and system |
| CN106444459A (en) * | 2016-11-15 | 2017-02-22 | 贵州大学 | Control apparatus for detecting duty ratio of rectangular wave signal in real time and realization method thereof |
| CN108013838A (en) * | 2017-10-31 | 2018-05-11 | 北京视觉世界科技有限公司 | Monitoring method, device, equipment and the storage medium of cleaning equipment |
| CN108226761A (en) * | 2017-12-28 | 2018-06-29 | 合肥工大高科信息科技股份有限公司 | A kind of rail traffic vehicles speed acquires the method with replacing self-test in real time |
| CN110579618A (en) * | 2019-09-17 | 2019-12-17 | 西安翔迅科技有限责任公司 | Motor rotating speed acquisition and analysis device and method based on FPGA |
| CN114109794A (en) * | 2021-11-26 | 2022-03-01 | 广东美的暖通设备有限公司 | Steering determination method, device, readable storage medium and air conditioning equipment |
| CN115837925A (en) * | 2022-11-11 | 2023-03-24 | 新誉轨道交通科技有限公司 | Speed measurement method, device and system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2022250B2 (en) * | 1969-05-08 | 1977-03-10 | Matsushita Electric Industrial Co., Ltd., Kadoma, Osaka (Japan) | ARRANGEMENT ON A MOVING MAGNETIC MEMORY FOR REGULATING THE RELATIVE SPEED OF THE RECORDING MEDIUM IN RELATION TO A MAGNETIC HEAD |
| CN101316093A (en) * | 2008-07-23 | 2008-12-03 | 株洲南车时代电气股份有限公司 | Constant slip frequency vector control method and system for linear induction motor |
| WO2009104576A1 (en) * | 2008-02-20 | 2009-08-27 | 株式会社明電舎 | Rotor phase and velocity detection device |
| CN101750512A (en) * | 2008-12-01 | 2010-06-23 | Abb公司 | Method and apparatus for estimating a rotation speed of an electric motor |
| CN102200541A (en) * | 2010-03-24 | 2011-09-28 | 中国科学院自动化研究所 | Method and device for measuring rotating speed of motor |
-
2012
- 2012-07-02 CN CN 201210224259 patent/CN102707083B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2022250B2 (en) * | 1969-05-08 | 1977-03-10 | Matsushita Electric Industrial Co., Ltd., Kadoma, Osaka (Japan) | ARRANGEMENT ON A MOVING MAGNETIC MEMORY FOR REGULATING THE RELATIVE SPEED OF THE RECORDING MEDIUM IN RELATION TO A MAGNETIC HEAD |
| WO2009104576A1 (en) * | 2008-02-20 | 2009-08-27 | 株式会社明電舎 | Rotor phase and velocity detection device |
| CN101316093A (en) * | 2008-07-23 | 2008-12-03 | 株洲南车时代电气股份有限公司 | Constant slip frequency vector control method and system for linear induction motor |
| CN101750512A (en) * | 2008-12-01 | 2010-06-23 | Abb公司 | Method and apparatus for estimating a rotation speed of an electric motor |
| CN102200541A (en) * | 2010-03-24 | 2011-09-28 | 中国科学院自动化研究所 | Method and device for measuring rotating speed of motor |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105628955B (en) * | 2015-12-25 | 2018-10-30 | 南京南瑞集团公司 | A kind of speed measuring device and its speed-measuring method of pump-storage generator static frequency changer |
| CN105628955A (en) * | 2015-12-25 | 2016-06-01 | 南京南瑞集团公司 | Speed measurement device for pump storage group static frequency converter and speed measurement method thereof |
| CN106089598A (en) * | 2016-06-02 | 2016-11-09 | 三重型能源装备有限公司 | A kind of wind power generator rotor detection method and system |
| CN106444459B (en) * | 2016-11-15 | 2023-04-28 | 贵州大学 | Control device for detecting duty ratio of rectangular wave signal in real time and implementation method |
| CN106444459A (en) * | 2016-11-15 | 2017-02-22 | 贵州大学 | Control apparatus for detecting duty ratio of rectangular wave signal in real time and realization method thereof |
| CN108013838A (en) * | 2017-10-31 | 2018-05-11 | 北京视觉世界科技有限公司 | Monitoring method, device, equipment and the storage medium of cleaning equipment |
| CN108226761A (en) * | 2017-12-28 | 2018-06-29 | 合肥工大高科信息科技股份有限公司 | A kind of rail traffic vehicles speed acquires the method with replacing self-test in real time |
| CN108226761B (en) * | 2017-12-28 | 2020-06-02 | 合肥工大高科信息科技股份有限公司 | Method for real-time acquisition and alternate self-inspection of speed of rail transit vehicle |
| CN110579618A (en) * | 2019-09-17 | 2019-12-17 | 西安翔迅科技有限责任公司 | Motor rotating speed acquisition and analysis device and method based on FPGA |
| CN110579618B (en) * | 2019-09-17 | 2021-08-20 | 西安翔迅科技有限责任公司 | Motor rotating speed acquisition and analysis device and method based on FPGA |
| CN114109794A (en) * | 2021-11-26 | 2022-03-01 | 广东美的暖通设备有限公司 | Steering determination method, device, readable storage medium and air conditioning equipment |
| CN114109794B (en) * | 2021-11-26 | 2023-08-04 | 广东美的暖通设备有限公司 | Steering determination method, apparatus, readable storage medium, and air conditioning device |
| CN115837925A (en) * | 2022-11-11 | 2023-03-24 | 新誉轨道交通科技有限公司 | Speed measurement method, device and system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102707083B (en) | 2013-10-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102707083B (en) | Motor speed calculating method | |
| CN2922277Y (en) | Clock burr testing circuit | |
| CN103858346B (en) | Variable frequency ratio leggy pulse width modulation produces | |
| CN105245203B (en) | High-precision low-speed clock duty ratio detecting system and method | |
| CN105718257B (en) | Timer arrangement and timing method based on embedded system | |
| CN104317253A (en) | System method for servo motor position control | |
| CN104901657A (en) | Full-digital debouncing circuit and method | |
| CN105302226B (en) | A kind of multifunctional mode timer circuit based on APB buses | |
| CN102902879B (en) | A kind of synchronized phasor computational methods based on FPGA hardware DFT recursion | |
| CN103487649B (en) | Method and device capable of measuring both frequency of continuous waves and frequency of pulse modulation carrier waves | |
| CN1776373A (en) | Phase demodulating circuit for incremeutal rotary encoder | |
| CN103995742A (en) | Embedded type real-time scheduling control device and method based on MCU | |
| CN109412582A (en) | A kind of pwm signal sample detecting circuit, processing circuit and chip | |
| CN103558753B (en) | A kind of high-resolution clock detection method and device | |
| CN102636769B (en) | Error counter for electric energy meter and error counting method | |
| CN103645379B (en) | TTL signal frequency saltus step monitoring system and method | |
| CN103516279A (en) | Permanent magnet synchronous motor control chip based on FPGA | |
| CN108700633A (en) | For safety and the ultrafast master clock observation circuit of secure automobile application | |
| CN103399808B (en) | A kind of method that realizes the two redundancies of crystal oscillator in flight control computer | |
| CN105917584A (en) | Digital period divider | |
| CN102750451B (en) | Motor speed calculation device | |
| CN102792167B (en) | Speed detection device | |
| CN108205605A (en) | Digitize the design method of multichannel pulse scope-analyzer configuration curring time | |
| CN103631161A (en) | Filtering method based on state machine | |
| CN102890445B (en) | Multi-functional timer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: The age of 412001 in Hunan Province, Zhuzhou Shifeng District Road No. 169 Patentee after: ZHUZHOU CRRC TIMES ELECTRIC Co.,Ltd. Address before: 412001 Hunan Province, Zhuzhou Shifeng District Tian Xin era Road No. 169 Patentee before: ZHUZH CSR TIMES ELECTRIC Co.,Ltd. |