CN108226761B - Method for real-time acquisition and alternate self-inspection of speed of rail transit vehicle - Google Patents
Method for real-time acquisition and alternate self-inspection of speed of rail transit vehicle Download PDFInfo
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- CN108226761B CN108226761B CN201711465248.5A CN201711465248A CN108226761B CN 108226761 B CN108226761 B CN 108226761B CN 201711465248 A CN201711465248 A CN 201711465248A CN 108226761 B CN108226761 B CN 108226761B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31703—Comparison aspects, e.g. signature analysis, comparators
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
- G01P3/00—Measuring linear or angular speed; Measuring differences of linear or angular speeds
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31708—Analysis of signal quality
Abstract
The invention relates to a method for acquiring the speed of a rail transit vehicle in real time and alternately self-checking, which comprises the following steps: (1) filtering the external sensor pulse signal and the test self-check signal; (2) the four-path sensor signal and the four-path self-checking signal are respectively sent to two channels of the FPGA through a state machine, and two groups of different pulses enter the two independent channels after a certain time through state switching; (3) independently calculating frequency values and direction values of four paths of pulses entering the two channels in respective channels; (4) and judging whether the frequency value and the direction value are the same as the frequency value and the direction value of the expected self-checking signal through the CPU, if so, indicating that the internal circuit of the FPGA normally works, otherwise, judging that the internal circuit of the FPGA abnormally works. The invention carries out self-checking on the acquired sensor pulse frequency value through the self-checking pulse, can accurately calculate the frequency value of a multi-channel signal, and reduces the burden of a CPU.
Description
Technical Field
The invention relates to the field of rail transit, in particular to a method for acquiring the speed of a rail transit vehicle in real time and alternately self-checking the speed of the rail transit vehicle.
Background
At present, some self-checking modes and frequency acquisition mostly adopt some CPUs, singlechips or DSPs to carry out self-checking and acquisition, and because the self-checking modes and the frequency acquisition operate according to an instruction cycle, even if multiple threads exist, the self-checking and acquisition cannot be truly operated in parallel. When multiple paths of signals need to be acquired simultaneously and the acquired signals need to be subjected to self-checking, the real-time performance is insufficient, and a large amount of resources are occupied. In the field of rail transit, in order to reduce the burden of a CPU, the powerful parallel processing capacity of an FPGA is utilized, and the frequency value of a plurality of paths of signals can be accurately calculated. And can also discover in time when FPGA internal register takes place the adhesion, and the register of arbitrary flow goes wrong and all detectable goes wrong and leads to safety in time. The invention provides a frequency quantity signal acquisition and self-checking scheme based on the cooperation of an FPGA and a CPU.
Disclosure of Invention
The invention aims to provide a method for acquiring the speed of a rail transit vehicle in real time and alternately self-checking, which is used for self-checking the acquired sensor pulse frequency value through self-checking pulses on the premise of simultaneously and accurately measuring multi-path pulse frequencies, so that the speed of the rail transit vehicle is improved.
In order to achieve the purpose, the invention adopts the following technical scheme:
a method for real-time acquisition and alternate self-inspection of rail transit vehicle speed comprises the following steps:
(1) filtering the external sensor pulse signal and the test self-check signal;
(2) the four-path sensor signal and the four-path self-checking signal are respectively sent to two channels of the FPGA through a state machine, and two groups of different pulses enter the two independent channels after a certain time through state switching;
(3) independently calculating frequency values and direction values of four paths of pulses entering the two channels in respective channels;
(4) and judging whether the frequency value and the direction value are the same as the frequency value and the direction value of the expected self-checking signal through the CPU, if so, indicating that the internal circuit of the FPGA normally works, otherwise, judging that the internal circuit of the FPGA abnormally works.
Further, in the step (1), the pulse signal of the external sensor and the test self-check signal are filtered, the counter starts counting after the rising edge of the detection signal, the high and low level of the signal is judged again after the count reaches a certain value, if the signal is high, the signal is considered to be a normal signal, and if the signal is low, the signal is considered to be an interference signal.
Further, the cut-off frequency of the filtering module can be adjusted by adjusting parameters.
According to the technical scheme, the method for acquiring the speed of the rail transit vehicle in real time and alternately self-checking the speed of the rail transit vehicle carries out self-checking on the acquired sensor pulse frequency value through the self-checking pulse. When the frequency value is wrong, the register inside the FPGA is sticky, data is unavailable at the moment, and when any position register inside the FPGA fails, the data can be timely found out, the frequency value of the multi-channel signal can be accurately calculated by utilizing the strong parallel processing capacity of the FPGA, and the load of a CPU is reduced. The invention adopts the FPGA to filter the frequency quantity signal, and the cut-off frequency is adjustable. And the frequency quantity information is calculated by adopting an improved M/T rule, so that the real-time property is improved.
Drawings
FIG. 1 is a system diagram of the present invention;
FIG. 2 is a partial timing diagram of the improved M/T rule of the present invention;
FIG. 3 is a schematic diagram of pulse switching and frequency value switching of the present invention;
FIG. 4 is a state transition diagram for pulse switching of the present invention;
FIG. 5 is a timing diagram illustrating the direction determination of the present invention;
fig. 6 is a flow chart of the method of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings:
the system adopted by the method for real-time acquisition and alternate self-inspection of the speed of the rail transit vehicle in the embodiment of fig. 1 comprises: the device comprises a microprocessor (CPU), a filtering module, a state machine switching module, a frequency calculation module, a direction judgment module and a data registering module, wherein the input end of the filtering module is connected with the input end of the state machine, the output end of the state machine is connected with the input end of a register, and the output end of the register is connected with the input end of the CPU. The FPGA filters a sensor pulse signal and a self-checking signal coming from the outside, a counter starts counting after the rising edge of the detection signal, the high and low levels of the signal are judged again after the counting reaches a certain value, if the signal is high, the signal is considered to be a normal signal, and if the signal is low, the signal is considered to be an interference signal.
The FPGA carries out software filtering on a sensor pulse signal and a self-checking signal which come from the outside. The counter starts counting after the rising edge of the signal is detected, the high-low level of the signal is judged again after a certain number is counted, if the signal is still high, the signal is considered to be a normal signal, and if the signal is low, the signal is considered to be an interference signal. In addition, the count parameter is configurable; the filtered sensor signal and the self-checking signal enter a pulse switching state machine, so that the sensor signal and the self-checking signal enter two different channels to respectively carry out independent frequency calculation and direction judgment; the frequency calculation module and the direction judgment module are mainly used for calculating the frequency quantity and judging the direction of the acquired sensor signal and the self-checking signal; the data registering module mainly switches once again according to the switching signals which enter the two channels of the FPGA so that each register stores corresponding sensor signals and self-checking signals. The problem that the sensor signal stored in the same register is the self-checking signal stored in the same register is solved. Therefore, the CPU can directly read the stored and registered data according to the interface time sequence. In addition, the FPGA uses an independent time window watchdog, and the FPGA needs to feed dogs for an external watchdog, so that the purpose of monitoring the working clock of the FPGA is achieved.
As shown in fig. 2, T1, T2, and ch1 are synchronized to the operating clock of the FPGA, T2 is the time of state switching, and T1 is a condition set according to the ATP operating cycle to save the amount of computation frequency. The M/T rule is improved by combining a position signal and a T1 signal to store a calculated frequency value, and the result does not need to be stored until the T2 threshold in the traditional method is finished, so that the calculation period is shortened, and the limit of manually judging high and low frequencies is avoided.
As shown in fig. 3, the eight-path two-group pulse on the right side enters two channels through the switching state machine, and the calculation result is put into a corresponding register through an alternative multiplexer for the CPU to read the frequency value and the direction value acquired by the FPGA. The switching of the numerical value of the register for storing the frequency value and the direction value along with the switching of the self-checking signal and the sensor signal is avoided, and the CPU is convenient to distinguish the self-checking frequency value register from the real sensor frequency value register.
As shown in fig. 1, the left CPU communicates with the FPGA over a parallel bus. And the CPU judges the frequency of the read self-detection pulse, and if the frequency is equal to the expected frequency value, the channel FPGA circuit is considered to be not in fault. The calculation of the next sensor pulse switched in is considered to be available. If the frequency value is not equal to the expected frequency value, the FPGA circuit is considered to be in fault, and the calculated value of the sensor pulse switched in next time is considered to be unavailable, so that the sensor pulse is guided to the safety side.
Fig. 4 is a state transition diagram of a switching state machine, and as shown in fig. 4, the switching time of the state machine is set according to the self-test period. The sensor signal and the CPU self-checking signal are switched to two independent signal processing modules of the FPGA in a time-sharing mode for processing, all register values used by the FPGA are guaranteed to be changed, the condition that the value of a certain register is not changed for a long time is avoided, and the register can be found out in time after the register in the FPGA fails.
As shown in fig. 5, the timing chart of the direction determination is such that, as shown in fig. 5, recognition is performed immediately after the two switched groups of pulses enter different channels, and the high/low level of ch2 when the rising edge of ch1 arrives is determined. When ch1 is high and ch2 is low, dir is considered low and is encoded as an eight-bit binary number. When ch1 is high and ch2 is high, dir is considered high and encoded as another eight-bit binary number. At this time, the direction is considered to be changed, and the direction signal is coded into a series of binary codes, mainly for preventing errors. If the direction of the self-detection signal detected by the CPU in the last switching period is not consistent with the expected value, the direction judgment of this time is deemed to be incredible.
As shown in fig. 6, the method for real-time speed acquisition and alternate self-inspection of rail transit vehicles includes the following steps:
s1: filtering the external sensor pulse signal and the test self-check signal to avoid the interference of external interference on frequency quantity calculation and direction judgment, and the cut-off frequency of the external sensor pulse signal and the test self-check signal can be adjusted through parameters;
s2: four-path sensor signals and four-path self-checking signals are sent to two channels of the FPGA in a time-sharing mode through a state machine, two groups of different pulse signals enter the two independent channels after a certain time through state switching, and therefore the two independent channels can calculate the frequency and direction values of the sensors and the self-checking signals at the same time without mutual interference;
s3: and independently calculating frequency values and direction values of four paths of pulses entering the two channels in respective channels:
the frequency value calculation uses the improved M/T rule to calculate the frequency of the eight paths of pulse signals. On one hand, signals of the sensor are synchronized to a working clock of the FPGA, and the two counters start counting under the synchronous signals, so that counting errors are avoided; on the other hand, the traditional method stores the calculation result only when the threshold time T2 is over, and the calculation result is stored by combining the pulse rising edge signal (pose) and the T1 threshold time; in addition, the register stores the value of the last rising edge before the next rising edge comes; the method also avoids the problem of artificially setting the high and low level frequency limits. Wherein, T1 is a threshold time generated on the premise of satisfying the operation period of ATP, and enough basic pulses can be ensured to calculate the frequency at high frequency.
S4: and the CPU reads the frequency and the direction of the self-checking signals in the two channels and judges whether the self-checking signals are equal to an expected value or not, so that whether two independent channels for signal processing in the FPGA have faults or not is judged. And if the self-checking pulse frequency value is different from the expected value, the signal processing channel in the FPGA is considered to be in fault. And as long as any register participating in signal processing in the FPGA has adhesion fault, the adhesion fault can be immediately found and guided to be safe.
The above-mentioned embodiments are merely illustrative of the preferred embodiments of the present invention, and do not limit the scope of the present invention, and various modifications and improvements of the technical solution of the present invention by those skilled in the art should fall within the protection scope defined by the claims of the present invention without departing from the spirit of the present invention.
Claims (2)
1. A rail transit vehicle speed real-time acquisition and alternate self-checking method is characterized by comprising the following steps:
(1) filtering an external sensor pulse signal and a test self-checking signal through a filtering module, wherein the cut-off frequency of the filtering module is adjusted through adjusting parameters;
(2) the four-path sensor signal and the four-path self-checking signal are respectively sent to two channels of the FPGA through a state machine, and two groups of different pulses enter the two independent channels after a certain time through state switching;
(3) independently calculating frequency values and direction values of four paths of pulses entering the two channels in respective channels;
(4) and judging whether the frequency value and the direction value are the same as the frequency value and the direction value of the expected self-checking signal through the CPU, if so, indicating that the internal circuit of the FPGA normally works, otherwise, judging that the internal circuit of the FPGA abnormally works.
2. The method for real-time acquisition and alternate self-inspection of rail transit vehicle speed according to claim 1, characterized in that: in the step (1), the pulse signal of the external sensor and the test self-check signal are filtered, the counter starts counting after the rising edge of the detection signal, the high and low levels of the signal are judged again after a certain number of values are counted, if the signal is high, the signal is considered to be a normal signal, and if the signal is low, the signal is considered to be an interference signal.
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| CN109278674B (en) * | 2018-08-31 | 2020-10-09 | 百度在线网络技术（北京）有限公司 | Unmanned vehicle system safety detection method, device, equipment and storage medium |
| CN109085370A (en) * | 2018-08-31 | 2018-12-25 | 高新兴创联科技有限公司 | Locomotive speed acquisition device and control method |
| CN110429934B (en) * | 2019-08-02 | 2023-01-31 | 西安星舟天启智能装备有限责任公司 | Anti-interference self-adaptive counting method |
| CN111220814A (en) * | 2019-11-12 | 2020-06-02 | 西安航空制动科技有限公司 | Airplane wheel speed acquisition system and fault detection method |
| CN111137701A (en) * | 2019-12-30 | 2020-05-12 | 合肥工大高科信息科技股份有限公司 | Non-stop ore drawing system and method |
| CN112272023B (en) * | 2020-10-23 | 2023-06-20 | 成都航天通信设备有限责任公司 | Signal processing channel selection method based on FPGA |
| CN112433064A (en) * | 2020-11-06 | 2021-03-02 | 杭州和利时自动化有限公司 | Rotating speed detection method, device and equipment |
| CN115629298B (en) * | 2022-12-19 | 2023-06-06 | 杭州加速科技有限公司 | Method and device for capturing abnormal synchronous trigger signal in ATE equipment |
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Effective date of registration: 20200407 Address after: 230088 Anhui city of Hefei province high tech Zone Xiyou road 1682 Applicant after: HEFEI GONGDA HIGH-TECH INFORMATION TECHNOLOGY Co.,Ltd. Applicant after: HEFEI NORMAL University Address before: 230088 Anhui city of Hefei province high tech Zone Xiyou road 1682 Applicant before: HEFEI GONGDA HIGH-TECH INFORMATION TECHNOLOGY Co.,Ltd. |
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