CN102946529A - Image transmission and processing system based on FPGA (Field Programmable Gate Array) and multi-core DSP (Digital Signal Processor) - Google Patents
Image transmission and processing system based on FPGA (Field Programmable Gate Array) and multi-core DSP (Digital Signal Processor) Download PDFInfo
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Abstract
The invention discloses an image transmission and processing system based on an FPGA (Field Programmable Gate Array) and a multi-core DSP (Digital Signal Processor). The system comprises a PC (Personal Computer), a PCI (Peripheral Component Interconnect) bridge, a double channel selector switch, the FPGA, the multi-core DSP, a crystal oscillator, a power supply and two memories. The PC is connected with the FPGA through the PCI bridge, the FPGA is connected with the double channel selector switch, the double channel selector switch is connected with the two memories and the DSP, the DSP is connected with the FPGA through an HPI (Hardware Platform Interface) interface, and the power supply is respectively connected with the FPGA and the DSP. The PC transmits image data to the FPGA through the PCI bridge. The FPGA carries out FIFO (First In, First Out) cache for the image data. Continuous image data is alternately stored between the two memories and transmitted to the multi-core DSP to process in turn in a ping-pong manner, so that the efficient and highly stable data transmission can be obtained.
Description
Technical field
The invention belongs to image transmitting and processing technology field, be based on specifically image transmitting and the treatment system of FPGA and multi-core DSP.
Background technology
Development along with science and technology, people's living standard is also in continuous improve, the arrival of digital age has brought the human world " information huge explosion ", so that data volume increases, meanwhile, in fields such as video detection, medical imagings, the two dimension that becomes increasingly complex, three-dimensional even four-dimensional image are processed the parallelizingsystem that needs to move complicated algorithm, especially in field of video image processing, usually need to be in extremely short time settling signal Treatment Analysis, be very high to the requirement of the performance for the treatment of system each side this moment.
With respect to monokaryon DSP, FPGA (Field Programmable Gate Array) or ASIC framework, have the advantages such as real-time, that flexibility is high and reliability is high based on the mode of FPGA and DSP work compound, thereby become the main flow design of high speed image transmission and treatment system in recent years.Some are arranged at present based on the successful case of this framework, but all be based on FPGA and monokaryon DSP framework.In the sample of high-resolution image and compressibility of the people such as Tang's Yao design, FPGA finishes the collection of image and the management of two SDRAM (frame is deposited) control, the image that collects alternately is deposited among two SDRAM by the control of FPGA, then the form of being expanded by EMIF by DSP reads the data among the SDRAM, carries out the processing of image again.This system seems cleaner and tidier, but in this structure, and FPGA and DSP will access complicated and slow SDRAM, and SDRAM also should provide its clock signal by DSP when transferring DSP to, and therefore whole circuit design is very complicated.In the real-time video-processing platform of the people such as Sheng Lei design, utilize VHDL language at the inner EMIF of realization of FPGA interface, directly be connected with the EMIF of DSP (C6711), and realize that EMIF is to the bus interface logic of I2C.What the EMIF of FPGA inside directly accessed is the FIFO memory that has image information.This system configuration is very simple, but the suitable complexity of the sequential logic of EMIF gives at efficient EMIF bus interface logic of the inner realization of FPGA to bring challenges.The people such as Zhong Daxiong have adopted the structure of a slice FPGA and three monokaryon DSP at plane planning hardware platform.Three DSP are interconnected by EMIF mouth and FPGA, and expanded DDR2SDRAM(second generation double data rate Synchronous Dynamic Random Access Memory for each DSP).This system can realize image transmitting at a high speed and the parallel processing between the DSP, but the interconnected logic between FPGA and three the monokaryon DSP is complicated, increased the complexity of the design of system, FPGA also need realize three arbitrations between the DSP simultaneously, along with the increase of DSP quantity, it is very complicated that this arbitration mechanism will become.
The design philosophy of multi-core DSP is that many kernels are integrated on the single-chip.DSP compares with monokaryon, and the multi-core DSP internal storage space is effectively expanded, and its arithmetic speed, handling property also have significantly raising than the former.With respect to a plurality of monokaryon DSP cascade frameworks, multi-core DSP has clear superiority aspect power consumption and chip area, the execution efficient.Just because of the many advantages of multi-core DSP, be applied to gradually in recent years the every field of Digital Signal Processing.But, according to existing paper and patent, present stage the framework based on FPGA and multi-core DSP also be not applied to image processing field.
Summary of the invention
The invention provides one based on image transmitting and the treatment system of FPGA and multi-core DSP, improve arithmetic speed and the handling property of view data.
Based on image transmitting and the treatment system of FPGA and multi-core DSP, comprise PC, PCI bridge, binary channels diverter switch, FPGA, multi-core DSP, crystal oscillator, power supply and two memories;
PC meets FPGA by the PCI bridging, and FPGA connects the binary channels diverter switch, and the binary channels diverter switch connects two memories and DSP, and DSP connects FPGA by the HPI interface, and power supply connects respectively determine FPGA and DSP;
PC is sent to FPGA with view data by the PCI bridge, and FPGA carries out the FIFO buffer memory to view data; The on off state of FPGA control binary channels diverter switch is to realize hocketing of the first read/write channel and the second read/write channel, and multi-core DSP is done parallel processing to the data that read, and result is returned to FPGA by the HPI interface;
Described the first read/write channel is: FPGA writes first memory with the current data of self buffer memory, and multi-core DSP reads the data that previous moment writes from second memory simultaneously; Described the second read/write channel is: FPGA writes second memory with the current data of self buffer memory, and multi-core DSP reads the data that previous moment writes from first memory simultaneously.
Described binary channels diverter switch adopts CPLD to realize.
Described memory adopts Double Data Rate synchronous DRAM DDR.
When being connected conducting with DSP, described DDR is serially connected with resistance between the two.
Technique effect of the present invention is embodied in:
In the coprocessing system based on FPGA and multi-core DSP framework, whether the mode of data communication is efficient between FPGA and the DSP, directly affects efficient and the performance of whole system.The present invention is after the system architecture and communication mechanism of having studied several FPGA commonly used of present stage and DSP associated treatment platform, in conjunction with characteristics such as DDR2SDRAM high data rate, low-power consumption, high stabilities, a kind of communication mechanism of novelty has been proposed, adopt memory (preferred DDR) as the data storage between FPGA and the multi-core DSP, mode by table tennis takes turns the consecutive image data alternately to store and alternately deliver to multi-core DSP and carry out parallel processing between two DDR2SDRAM, to obtain efficient and the high-stability data transmission.
Description of drawings
Fig. 1 is based on image transmitting and the treatment system schematic diagram of FPGA and multi-core DSP;
Fig. 2 is FPGA and DDR2SDRAM Design of Interface Module schematic diagram;
Fig. 3 is the Design of Interface Module schematic diagram of DSP and DDR2SDRAM;
Embodiment
The present invention is described in further detail below in conjunction with drawings and Examples.
As shown in Figure 1, based on image transmitting and the treatment system of FPGA and multi-core DSP, comprise PC, PCI bridge, FPGA, binary channels diverter switch, multi-core DSP, crystal oscillator, power supply and two DDR2SDRAM.In addition, series arrangement chip EPCS reconfigures it when powering on for FPGA.Synchronous Dynamic Random Access Memory SDRAM adopts many Bank structure, but the access speed of Effective Raise memory.
PC meets FPGA by the PCI bridging, and FPGA connects the binary channels diverter switch, and the binary channels diverter switch connects two memories and DSP, and DSP connects FPGA by the HPI interface, and power supply connects respectively determine FPGA and DSP;
PC is sent to FPGA with view data by the PCI bridge, and FPGA carries out the FIFO buffer memory to view data; The on off state of FPGA control binary channels diverter switch is to realize hocketing of the first read/write channel and the second read/write channel, and multi-core DSP is done parallel processing to the data that read, and result is returned to FPGA by the HPI interface;
Described the first read/write channel is: FPGA writes first memory with the current data of self buffer memory, and multi-core DSP reads the data that previous moment writes from second memory simultaneously; Described the second read/write channel is: FPGA writes second memory with the current data of self buffer memory, and multi-core DSP reads the data that previous moment writes from first memory simultaneously.
Power supply is used for to FPGA and DSP power supply, and the clock signal that crystal oscillator is used for providing basic is synchronous to guarantee FPGA and DSP.
The binary channels diverter switch can adopt CPLD to realize, memory can adopt Double Data Rate synchronous DRAM DDR.
The below provides an instantiation:
1. after system powered on, the FPGA(model was EP2C35F672C6N) part finishes and just begins after the initialization to be cached among the inner FIFO through PCI bridge reads image data.Here, bridging meets PC and FPGA as PCI to select PCI9056.The signal (signals such as data, address, control) of the local of PCI9056 end is connected with the FPGA pin, just can realizes the interface of PCI9056 and FPGA.
2.FPGA it is MT47H16M16 that the data among the FIFO are written to the DDR2SDRAM(model that is attached thereto).The DDR2SDRAM interface of FPGA as shown in Figure 2.
3.DDR2SDRAM in data reach a certain amount of after FPGA notice CPLD be TMS320C6472 with the bus control right of twin-channel DDR2SDRAM at FPGA and DSP(model) between exchange, and send an interrupt signal to DSP.Here, need to prove: TMS320C6472 itself directly is not connected with DDR2SDRAM, needs to be connected with one road DDR2SDRAM wherein by the switching of CPLD.The signal of DDR2SDRAM with need between the two, be connected in series 22 ohm resistance when DSP is connected, to improve Signal integrity.Based on above-mentioned consideration, designed the interface module of DSP and DDR2SDRAM shown in Figure 3.
4.DSP read data from the DDR2SDRAM that obtains bus control right, allocating task to 6 kernel is done parallel processing.The result who calculates transfers to FPGA through the HPI interface.
5.DSP after internal data was finished dealing with, notice FPGA calculation task was finished, FPGA notifies again switch data path of CPLD in idle condition.
Based on above-mentioned thinking, designed high speed data transfer and the treatment system of FPGA and multi-core DSP.Adopt this system that the PCI9056 transmitted data rates is tested, test result is as shown in table 1.Can reach greater than 60Mbytes/S(61592860.5 when as can be seen from Table 1, writing data) speed.Can reach the speed greater than 23Mbytes/S in the time of through the PCI9056 read data.
Data writing amount and the writing speed of table 1PCI9056
Those skilled in the art will readily understand; the above only is preferred embodiment of the present invention; not in order to limiting the present invention, all any modifications of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., all should be included within protection scope of the present invention.
Claims (4)
1. based on image transmitting and the treatment system of FPGA and multi-core DSP, comprise PC, PCI bridge, binary channels diverter switch, FPGA, multi-core DSP, crystal oscillator, power supply and two memories;
PC meets FPGA by the PCI bridging, and FPGA connects the binary channels diverter switch, and the binary channels diverter switch connects two memories and DSP, and DSP connects FPGA by the HPI interface, and power supply connects respectively determine FPGA and DSP;
PC is sent to FPGA with view data by the PCI bridge, and FPGA carries out the FIFO buffer memory to view data; The on off state of FPGA control binary channels diverter switch is to realize hocketing of the first read/write channel and the second read/write channel, and multi-core DSP is done parallel processing to the data that read, and result is returned to FPGA by the HPI interface;
Described the first read/write channel is: FPGA writes first memory with the current data of self buffer memory, and multi-core DSP reads the data that previous moment writes from second memory simultaneously; Described the second read/write channel is: FPGA writes second memory with the current data of self buffer memory, and multi-core DSP reads the data that previous moment writes from first memory simultaneously.
2. FPGA according to claim 1 and DSP data transmission system is characterized in that, described binary channels diverter switch adopts CPLD to realize.
3. FPGA according to claim 1 and DSP data transmission system is characterized in that, described memory adopts Double Data Rate synchronous DRAM DDR.
4. FPGA according to claim 3 and DSP data transmission system is characterized in that, are serially connected with resistance between the two when described DDR is connected conducting with DSP.
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