CN109558373B - High-performance fusion server - Google Patents

High-performance fusion server Download PDF

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CN109558373B
CN109558373B CN201811465942.1A CN201811465942A CN109558373B CN 109558373 B CN109558373 B CN 109558373B CN 201811465942 A CN201811465942 A CN 201811465942A CN 109558373 B CN109558373 B CN 109558373B
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chip
fpga
interface
memory array
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CN109558373A (en
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姜凯
于治楼
郝虹
李朋
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Shandong Inspur Science Research Institute Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F2015/761—Indexing scheme relating to architectures of general purpose stored programme computers
    • G06F2015/766—Flash EPROM
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention particularly relates to a high-performance fusion server. The high-efficiency fusion server adopts a heterogeneous architecture of a general processor and double FPGA chips to realize high-efficiency fusion of a network, calculation and storage, and comprises the general processor, an FPGA 1 chip, an FPGA2 chip, a local memory, a memory array, a flash memory array and an FPGA local memory; the FPGA 1 chip, the FPGA2 chip and the local memory are all connected to the general processor, the memory array and the flash memory array are all connected to the FPGA 1 chip, the FPGA local memory is connected to the FPGA2 chip, and the FPGA 1 chip and the FPGA2 chip are connected through a data bus. The high-efficiency fusion server adopts a heterogeneous architecture of a general processor and two FPGA chips, has high flexibility, low energy consumption and strong fault-tolerant characteristic, realizes the fusion of calculation, storage and a network, and greatly improves the cloud application efficiency.

Description

High-performance fusion server
Technical Field
The invention relates to the technical field of servers, in particular to a high-performance fusion server.
Background
With the rapid growth of internet users and the rapid expansion of the volume of data, the demand of data centers for computing is also rapidly increasing. The computing requirements of various applications such as deep learning online prediction, video transcoding in live broadcasting, picture compression and decompression, and HTTPS encryption are far beyond the capabilities of conventional CPU processors.
Historically, with the continuing evolution of semiconductor technology, the throughput and system performance of computer architectures has increased, doubling the performance of processors every 18 months (well known as "moore's law") so that the performance of processors can meet the requirements of application software. However, in recent years, semiconductor technology improvements have reached physical limits, and circuits have become more complex, with development costs of up to millions of dollars per design, with billions of dollars in new product viability. 24/3/2016, intel announces that the "Tick-tack" processor development model is formally disabled, and that future development cycles will shift from two-year cycles to three-year cycles. Until now, moore's law has nearly failed for intel.
On the one hand, processor performance can no longer be increased according to moore's law, and on the other hand, data growth has exceeded the computational performance requirements by the rate of increase according to moore's law. The inability of the processor itself to meet the Performance requirements of HPC (High Performance computing) application software has resulted in a gap between requirements and Performance.
In view of this situation, a technical person proposes a solution to improve the processing performance by hardware acceleration and using a heterogeneous computing method of a dedicated coprocessor.
An fpga (field Programmable Gate array), i.e. a field Programmable Gate array, is a product of further development on the basis of Programmable devices such as PAL, GAL, CPLD, etc. The FPGA is used as a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), which not only solves the defects of the custom circuit, but also overcomes the defect that the gate circuit number of the original programmable device is limited.
Compared with the traditional general-purpose processor, the heterogeneous computing cut-off aspect of the reconfigurable architecture adopting the CPU processor + FPGA has many advantages, such as: higher performance, greater flexibility, lower power consumption characteristics, natural fault tolerance characteristics, capability of greatly shortening the product development period, and the like. The FPGA chip is adopted to replace a GPU (Graphics Processing Unit) as an accelerator for future high-performance computation, and the FPGA chip is supposed to be the main melody developed by FPGA heterogeneous intelligent computation at the present stage.
Based on the above situation, the present invention provides a high performance fusion server.
Disclosure of Invention
In order to make up for the defects of the prior art, the invention provides a simple and efficient high-efficiency fusion server.
The invention is realized by the following technical scheme:
a high performance converged server, comprising: the method is characterized in that a heterogeneous architecture of a general processor and double FPGA chips is adopted, and a network, calculation and storage are efficiently integrated, wherein the heterogeneous architecture comprises the general processor, an FPGA 1 chip, an FPGA2 chip, a local memory, a memory array, a flash memory array and an FPGA local memory; the FPGA 1 chip, the FPGA2 chip and the local memory are all connected to the general processor, the memory array and the flash memory array are all connected to the FPGA 1 chip, the FPGA local memory is connected to the FPGA2 chip, and the FPGA 1 chip and the FPGA2 chip are connected through a data bus.
The FPGA 1 chip adopts a high-speed memory interface to realize high-speed interconnection with a general processor, and a memory array interface and a flash memory interface are expanded to enlarge a high-speed storage space and realize interconnection with an SRIO interface of the FPGA2 chip; the FPGA2 chip adopts a general heterogeneous architecture and is used for realizing network message analysis and unloading and arbitrating a data function and a sending direction.
The FPGA 1 chip is used for storage expansion and acceleration, and is internally provided with 2 DDR4 interfaces, 1 SRIO interface, 1 flash controller interface, an internal RAM logic module and a storage control and arbitration logic module; the 2 DDR4 interfaces, the 1 SRIO interface, the 1 flash controller interface and the internal RAM logic module are all connected to the storage control and arbitration logic module.
The memory controller comprises 2 DDR4 interfaces, an SRIO interface, a flash memory controller interface, an internal RAM logic module and a storage control and arbitration logic module, wherein the 2 DDR4 interfaces are respectively used for connecting a memory array and a general processor, the SRIO interface is used for realizing data interconnection between an FPGA 1 chip and an FPGA2 chip, the flash memory controller interface is used for connecting the flash memory array, the internal RAM logic module is used for storing a data Mapping table, and the storage control and arbitration logic module is responsible for classifying data instructions and confirming that data is read or written in the memory array or the flash memory array.
The FPGA2 chip is used as an intelligent network card, and is internally provided with a network interface, a DDR4 interface, an SRIO interface, a PCIE interface and a network message unloading and arbitration logic module; and the network interface, the SRIO interface and the PCIE interface are all connected to the network message unloading and arbitration logic module.
The network interface is used for external data interconnection, the DDR4 interface is used for connecting an FPGA local memory, the SRIO interface is used for realizing data interconnection between an FPGA2 chip and an FPGA 1 chip, the PCIE interface is interconnected with the general processor, and the network message unloading and arbitration logic module is used for analyzing and unloading a network protocol and arbitrating a data sending direction.
The data Mapping table in the internal RAM logic module comprises a data storage position and a cold and hot table of data, wherein the data storage position is a memory array or a flash memory array, the cold and hot table of the data is the use heat of stored data, the hot data is stored in the memory array, and the cold data is stored in the flash memory array; the data cooling and heating degree is evaluated according to the number of times data is written into and read out once in unit time, and the number of times of reading is set according to application.
The high-efficiency fusion server receives external data through a network interface of the FPGA2 chip, and the external data is unloaded through a network message and then confirms whether the message needs to be transmitted to the general processor or the FPGA 1 chip through arbitration logic; if the data is sent into the general processor, the general processor determines whether the data is sent out or written into the FPGA 1 chip after processing; if the data is sent into the FPGA 1 chip, the data is analyzed through the storage control and arbitration logic module, and the data is read or written into the memory array or the flash memory array according to the instruction; and the data reading or writing strategy is to store the data use heat according to the data cold-hot table, store the hot data into the memory array and store the cold data into the flash memory array.
The invention has the beneficial effects that: this high-effect integration server adopts the heterogeneous structure of general processor + two FPGA chips, and the flexibility is high, and the energy consumption is low, and fault-tolerant characteristic is strong, has realized calculating, the integration of storage and network, has greatly promoted cloud application efficiency, can satisfy HPC application software's performance demand, has filled the breach between demand and the performance, suitable popularization and application.
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FIG. 1 is a schematic diagram of a high performance fusion server according to the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is described in detail below with reference to the accompanying drawings and embodiments. It should be noted that the specific embodiments described herein are only for explaining the present invention and are not used to limit the present invention.
The high-efficiency fusion server adopts a heterogeneous architecture of a general processor and double FPGA chips to realize high-efficiency fusion of a network, calculation and storage, and comprises the general processor, an FPGA 1 chip, an FPGA2 chip, a local memory, a memory array, a flash memory array and an FPGA local memory; the FPGA 1 chip, the FPGA2 chip and the local memory are all connected to the general processor, the memory array and the flash memory array are all connected to the FPGA 1 chip, the FPGA local memory is connected to the FPGA2 chip, and the FPGA 1 chip and the FPGA2 chip are connected through a data bus.
The FPGA 1 chip adopts a high-speed memory interface to realize high-speed interconnection with a general processor, and a memory array interface and a flash memory interface are expanded to enlarge a high-speed storage space and realize interconnection with an SRIO interface of the FPGA2 chip; the FPGA2 chip adopts a general heterogeneous architecture and is used for realizing network message analysis and unloading and arbitrating a data function and a sending direction.
The FPGA 1 chip is used for storage expansion and acceleration, and is internally provided with 2 DDR4 interfaces, 1 SRIO interface, 1 flash controller interface, an internal RAM logic module and a storage control and arbitration logic module; the 2 DDR4 interfaces, the 1 SRIO interface, the 1 flash controller interface and the internal RAM logic module are all connected to the storage control and arbitration logic module.
The memory controller comprises 2 DDR4 interfaces, an SRIO interface, a flash memory controller interface, an internal RAM logic module and a storage control and arbitration logic module, wherein the 2 DDR4 interfaces are respectively used for connecting a memory array and a general processor, the SRIO interface is used for realizing data interconnection between an FPGA 1 chip and an FPGA2 chip, the flash memory controller interface is used for connecting the flash memory array, the internal RAM logic module is used for storing a data Mapping table, and the storage control and arbitration logic module is responsible for classifying data instructions and confirming that data is read or written in the memory array or the flash memory array.
The FPGA2 chip is used as an intelligent network card, and is internally provided with a network interface, a DDR4 interface, an SRIO interface, a PCIE interface and a network message unloading and arbitration logic module; and the network interface, the SRIO interface and the PCIE interface are all connected to the network message unloading and arbitration logic module.
The network interface is used for external data interconnection, the DDR4 interface is used for connecting an FPGA local memory, the SRIO interface is used for realizing data interconnection between an FPGA2 chip and an FPGA 1 chip, the PCIE interface is interconnected with the general processor, and the network message unloading and arbitration logic module is used for analyzing and unloading a network protocol and arbitrating a data sending direction.
The data Mapping table in the internal RAM logic module comprises a data storage position and a cold and hot table of data, wherein the data storage position is a memory array or a flash memory array, the cold and hot table of the data is the use heat of stored data, the hot data is stored in the memory array, and the cold data is stored in the flash memory array; the data cooling and heating degree is evaluated according to the number of times data is written into and read out once in unit time, and the number of times of reading is set according to application.
The high-efficiency fusion server receives external data through a network interface of the FPGA2 chip, and the external data is unloaded through a network message and then confirms whether the message needs to be transmitted to the general processor or the FPGA 1 chip through arbitration logic; if the data is sent into the general processor, the general processor determines whether the data is sent out or written into the FPGA 1 chip after processing; if the data is sent into the FPGA 1 chip, the data is analyzed through the storage control and arbitration logic module, and the data is read or written into the memory array or the flash memory array according to the instruction; and the data reading or writing strategy is to store the data use heat according to the data cold-hot table, store the hot data into the memory array and store the cold data into the flash memory array.
This high-effect integration server adopts the heterogeneous structure of general processor + two FPGA chips, and the flexibility is high, and the energy consumption is low, and fault-tolerant characteristic is strong, has realized calculating, the integration of storage and network, has greatly promoted cloud application efficiency, can satisfy HPC application software's performance demand, has filled the breach between demand and the performance, suitable popularization and application.

Claims (7)

1. A high performance converged server, comprising: the method is characterized in that a heterogeneous architecture of a general processor and double FPGA chips is adopted, and a network, calculation and storage are efficiently integrated, wherein the heterogeneous architecture comprises the general processor, an FPGA 1 chip, an FPGA2 chip, a local memory, a memory array, a flash memory array and an FPGA local memory; the FPGA 1 chip, the FPGA2 chip and the local memory are all connected to the general processor, the memory array and the flash memory array are all connected to the FPGA 1 chip, the FPGA local memory is connected to the FPGA2 chip, and the FPGA 1 chip and the FPGA2 chip are connected through a data bus;
the FPGA 1 chip adopts a high-speed memory interface to realize high-speed interconnection with a general processor, and a memory array interface and a flash memory interface are expanded to enlarge a high-speed storage space and realize interconnection with an SRIO interface of the FPGA2 chip; the FPGA2 chip adopts a general heterogeneous architecture and is used for realizing network message analysis and unloading and arbitrating a data function and a sending direction.
2. The high-performance fusion server as recited in claim 1, wherein: the FPGA 1 chip is used for storage expansion and acceleration, and is internally provided with 2 DDR4 interfaces, 1 SRIO interface, 1 flash controller interface, an internal RAM logic module and a storage control and arbitration logic module; the 2 DDR4 interfaces, the 1 SRIO interface, the 1 flash controller interface and the internal RAM logic module are all connected to the storage control and arbitration logic module.
3. The high-performance fusion server as recited in claim 2, wherein: the memory controller comprises 2 DDR4 interfaces, an SRIO interface, a flash memory controller interface, an internal RAM logic module and a storage control and arbitration logic module, wherein the 2 DDR4 interfaces are respectively used for connecting a memory array and a general processor, the SRIO interface is used for realizing data interconnection between an FPGA 1 chip and an FPGA2 chip, the flash memory controller interface is used for connecting the flash memory array, the internal RAM logic module is used for storing a data Mapping table, and the storage control and arbitration logic module is responsible for classifying data instructions and confirming that data is read or written in the memory array or the flash memory array.
4. The high-performance fusion server as recited in claim 1, wherein: the FPGA2 chip is used as an intelligent network card, and is internally provided with a network interface, a DDR4 interface, an SRIO interface, a PCIE interface and a network message unloading and arbitration logic module; and the network interface, the SRIO interface and the PCIE interface are all connected to the network message unloading and arbitration logic module.
5. The high-performance fusion server as recited in claim 4, wherein: the network interface is used for external data interconnection, the DDR4 interface is used for connecting an FPGA local memory, the SRIO interface is used for realizing data interconnection between an FPGA2 chip and an FPGA 1 chip, the PCIE interface is interconnected with the general processor, and the network message unloading and arbitration logic module is used for analyzing and unloading a network protocol and arbitrating a data sending direction.
6. The high-performance fusion server as recited in claim 3, wherein: the data Mapping table in the internal RAM logic module comprises a data storage position and a cold and hot table of data, wherein the data storage position is a memory array or a flash memory array, the cold and hot table of the data is the use heat of stored data, the hot data is stored in the memory array, and the cold data is stored in the flash memory array; the data cooling and heating degree is evaluated according to the number of times data is written into and read out once in unit time, and the number of times of reading is set according to application.
7. The high-performance fusion server as recited in claim 6, wherein: receiving external data through a network interface of the FPGA2 chip, and determining whether the message needs to be transmitted to the general processor or the FPGA 1 chip through arbitration logic after the external data is unloaded through a network message; if the data is sent into the general processor, the general processor determines whether the data is sent out or written into the FPGA 1 chip after processing; if the data is sent into the FPGA 1 chip, the data is analyzed through the storage control and arbitration logic module, and the data is read or written into the memory array or the flash memory array according to the instruction; and the data reading or writing strategy is to store the data use heat according to the data cold-hot table, store the hot data into the memory array and store the cold data into the flash memory array.
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US11082410B2 (en) 2019-04-26 2021-08-03 Advanced New Technologies Co., Ltd. Data transceiving operations and devices
CN110177083B (en) * 2019-04-26 2021-07-06 创新先进技术有限公司 Network card, data sending/receiving method and equipment
CN110765064B (en) * 2019-10-18 2022-08-23 山东浪潮科学研究院有限公司 Edge-end image processing system and method of heterogeneous computing architecture
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