SU532968A1 - Device for searching for pseudo-noise signals - Google Patents

Description

(54) DEVICE FOR SEARCHING FOR PUSHDOG-SIGNAL SIGNALS

The invention relates to radio engineering and is intended for searching and synchronizing pseudo-noise signals in a temporal position and a clock frequency.

A device for searching for pseudo-noise signals (ASL) is known, which contains a discriminator, an etched generator, a counter and a control unit connected in series, the second input of which is connected to the discriminator's input via a decision circuit, to one of whose inputs the output of the controlled generator is connected via a shift register with feedbacks.

However, the known device has a longer search time for PSHS with small values of the signal-to-noise ratio.

The aim of the invention is to reduce the time to search for PSN for small values of the signal-to-noise ratio.

To do this, a delay line, an additional shift register, a memory block, a write block, a reversible counter block, and a rewrite block are entered into the PSH search device, and the delay line is connected between the first and second discriminator inputs, to the third input of which the output of the first bit is connected. the shift register, to the clock input of which the output of the controlled oscillator is connected, to the signal input is the first input of the dio- criminator, and the outputs of the bits of the additional register are connected to the inputs of the corresponding bits Shift feedback register through a sequentially connected recording unit, between the corresponding inputs of which a memory unit, a reversible counter unit and a rewriter unit are connected, the corresponding control unit inputs being connected to the control inputs of the memory unit and the recording and rewriting units. .

The drawing shows a structural electrical circuit of the PSG search device. The device contains successively

connected discriminator 1, controlled oscillator 2, counter 3, control unit 4, the second input of which is connected to the input of discriminator 1 via solving circuit 5, to one of the inputs of which under the shift register with feedback 6, delay line 7, additional shift register 8, memory block 9, recording block 10, reversible counter block 11, and rewriting block 12. In this case, a decade line 7 is connected between the first and second inputs of the discriminator 1, to the third input of which the output of the first bit is connected yes additional shift register 8, to the clock input of which is connected to the output of the controlled generator 2, to the signal input is the first input of the discriminator 1, and the outputs of the bits of the additional register 8 are connected to the inputs of the corresponding bits of the shift register with feedback 6 through serially connected recording unit 10, the corresponding inputs of which the memory block 9, the reversible counter block 11, and the rewriting unit 12 are turned on, and the corresponding outputs of the control block are connected to the control inputs of the memory block and the write and rewrite blocks The device works as follows. The input oscillation is fed to the input of the delay line 7, the discriminator Ij of the additional shift register 8 and the decisive circuit 5. Using the delay line 7, the discriminator 1, the first time of the additional register 8, the controlled oscillator 2, the clock frequency of the received signal is extracted and using counter 3, the periods of the received signal are counted. At the moment of appearance of the pulse at the output of counter 3, the control unit 4 records the information about the state of the received pulses of the received signal to the memory unit 9, through the recording unit 10 - the reversible counter block 11 and through the rewriting block 12 in each bit of the shift register with feedbacks 6. At the initial moment of time, information is written from each bit of the additional register 8 to the memory block 9, to the reversible counter block 11 and to the register feedback shift 6 If at the moment of recording information at the input of any of the elements of memory block 9, initially set to zero, there was a high voltage level, then a high level of voltage is also set at the output of the same memory element Yeni. Otherwise, the state does not change,

voltage, then one pulse is added to this counter. Otherwise, one pulse is subtracted from the counter of the counter. When multiple records are written in reversible counters, accumulation of information on the cocTOJt of elementary pulses of the received CSP occurs. As a result of accumulation, the probability of correctly estimating several times of the next pulses increases significantly. After the first recording of the information about the state of the elementary pulses of the received signal into the shift register with feedbacks 6, a check follows that the feedback shift register 6 generates a reference signal from the recorded code that is matched with the received If the signals coincide in the time position and clock frequency, then the decision circuit 5 issues a command to the control unit 4 on the best {repeated recording of information, as the fished and reference signals are synchronized. If synchronization during the check did not occur; then exactly after the first recording, the second recording of information only in the block of reversible counters 11 and with them overwriting the shift register B with feedback 6 "Dt to eliminate the uncertainty of the decision making after each record of information about the state of the pulses The memory block 9 is used in the device. With its help, in each even-numbered counting, information recording records are connected to the BXCN corresponding to 1. its reversible counter of the inverted output of the corresponding memory block element 9. This is the signal It is impossible to subtract from the reversible counters the information recorded in the block pa: vshti 9, In the bake periods, the direct paths of the memory block 9 are connected to the inputs of the reversible counters, which means adding information to the reversible counters recorded in the memory block 9 Takik: image and reversible counters always have information about an odd number of records, which eliminates the uncertainty in the evaluation of the corresponding, its impulse of the received signal, At that time, checking the correct assessment of the new film information B reversible counters produces at all moments aapisk, 1st :: Increases the number of search attempts to lnala and umenyiaet his Bryl1Ya,