JPH0323565A - Sector mark detector - Google Patents

Abstract

PURPOSE:To improve the sector mark detection precision by outputting a sector mark detection signal at the time of coincidence between inputted data and each pattern of a sector mark and stopping the counting operation of each counter with a reset signal at the time of not giving an enable signal to the counter from another counter of the preceding stage. CONSTITUTION:When data indicating a regular sector mark is inputted, respective counters A to N of a detecting counter part 21 count prescribed numbers a' to n' of bits of inputted data '1' or '0' to output enable signals to counters of succeeding stages. Consequently, counters which receive enable signals continue the counting operation though the reset signal is inputted from a reset generating counter part 23, and the sector mark detection signal is outputted by the counter N of the last stage. If data other than the regular sector mark is inputted, the sector mark detection signal is not outputted by the reset signal from the reset generating counter part 23 because enable signals are not outputted from respective counters A to N of the detecting counter part 21. Thus, the precision of sector mark detection is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a device for detecting a sector mark, which is a mark that identifies the position of a sector (fan-shaped area) of a disk-shaped recording medium such as an optical disk, and particularly relates to It is possible to effectively detect sector marks even when there are scratches or dust on the recording surface of the recording medium, improve detection accuracy, and reduce the number of registers compared to conventional methods. This article relates to a sector mark detection device that can reduce the circuit scale. [Prior Art] On a disk-shaped recording medium such as an optical disk, a sector mark is recorded for each sector that separates a track to identify the sector. For example, this sector mark is made by first recording one piece of data continuously for a predetermined number of bits a (
"l l l 1..."), and then, following this, O data is continuously recorded for a predetermined number of bits b ("oo
oo…”), followed by consecutive 1s for the predetermined number of bits c, d…n in the same way as above.
and consecutive O data are recorded alternately. FIGS. 3 and 4 are circuit diagrams showing conventional sector mark detection devices for detecting such sector marks. Of these, FIG. 3 uses a shift register 1 into which data is input manually and each gate 2, 3, 4, . . . into which the output from this shift register 1 is input.
A when all outputs from ... are at the old gh level
A sex mark detection signal is output from the ND gate 5. Further, FIG. 4 shows a counter 6 into which data is input, and a D flip-flop 7 which outputs the signal given from this counter 6 as it is in synchronization with the clock.
, 8.9.10 and each of these D flip-flops 7 to 10
When the output from t{ i
g Consists of a combinational circuit 11 that outputs a h-level signal, and an AND gate 13 that receives the output from the combinational circuit 1l and the output from a shift register 12 to which a clock is input and outputs a sector mark detection signal. ．． [Problems to be Solved by the Invention] However, in the detection device shown in FIG. The circuit scale becomes large. Furthermore, if the disk of the recording medium is scratched or has dust attached to it, the detected pattern will not completely match the sector mark pattern, making detection impossible. Furthermore, the detection device shown in FIG. 4 is similar to the one shown in FIG. 3 in that it is susceptible to scratches and dust on the recording medium, and the detection device shown in FIG. When a pattern such as "oooo" is input, it is not possible to determine the mutual order of the patterns, so there is a risk of erroneous detection in which the sector mark detection signal is output in either order. 6 to solve the problem, it is possible to effectively detect sector marks even when there are scratches or dust on the recording surface of the recording medium, and it is possible to improve the detection accuracy. It is an object of the present invention to provide a sector mark detection device capable of reducing the circuit scale by reducing the number of registers. to the medium, 1
Each pattern a. b. C... for each of these patterns a. b. c... are continuous with each other, and each pattern a, b. A detecting device for a sector mark formed by recording such that data types 1 and O are inverted every time a plurality of counters A.c... B. C... are connected, and each counter A. B. C... counts the number of inputs of 1 or 0 data from each input data, and calculates this number of inputs by a predetermined number of bits determined in relation to the number of bits of each data of each pattern ab, c... Number of times a', b',
When counting up to c'..., each counter other than the last stage outputs an enable signal to the next stage counter to enable counting operation regardless of the input of the reset signal, and the last stage counter a detection counter section that outputs a mark detection signal; and a plurality of counters A'. B'. C'... are connected in parallel, and each of these counters A'. B'. C'
. . . are the respective counters A. The number of clock pulse inputs is counted in response to the start of each counting operation of B, C, etc., and this number of inputs is calculated according to each pattern a. b. c.
A predetermined number of times a, β, . . . determined in relation to the number of bits of each data. γ..., each of the counters A. This device is characterized in that it is equipped with a reset generation counter section that outputs a reset signal at B, C, . . . . [Function 1] According to the above means, the data of l and 0 are arranged in a predetermined pattern a. b. The sector marks that are consecutively and alternately recorded every time c... are detected in the order in which they were recorded, and a sector mark detection signal is output only when a pattern in that order is finally detected. ing. That is, when data indicating a regular sector mark is input, each counter A. of the detection counter section is input. B, C...
• counts input 1 or O data by a predetermined number of bits a', b', c', etc., and sequentially outputs an enable signal to the next stage counter. therefore,
After a reset signal is input from the reset generation counter section, the counter that has received the enable signal continues counting operations, and the last stage counter outputs a sector mark detection signal. Also, if data that is not a regular sector mark is input, each counter A. B. Since the enable signal is not output from C..., the sector mark detection signal is not output by the reset signal from the reset generation counter section. In addition, each counter A, B, C, .
, b. The number of times a'.c is determined in relation to each bit number of c... b', c'...The enable signal or sector mark detection signal is output when something goes wrong. Therefore, if the input data is sector mark pattern a. ．． b, (:...), but if they match to a certain extent, a sector mark detection signal is output, so if part of the input data is missing due to scratches or dust on the recording medium. [Embodiment 1] An embodiment of the present invention will be described below based on the drawings. Fig. 1 shows a sector mark detection device according to an embodiment of the present invention. FIG. 2 is a time chart for explaining the operation of the sector mark detection device shown in FIG. 1. In FIG. Detection counter A.B, C.D...N
It is composed of Each of these detection powers A-N
The read data and system clock inputs are connected in parallel, and the enable signal (a signal to keep the counter in operation regardless of the input of the reset signal) output from the EN terminal of each counter is connected in cascade. It is connected. This enable signal is used for each detection counter A. E. C. In D... (excluding N), data of 1 or O is detected from the read data in synchronization with the clock, and when the number of detections reaches a predetermined number of times determined in advance for each counter, the next stage This is output for all subsequent detection counters. The enable signals of 6 and 6 are AN for detection counters after C.
D gate 22c. 22d...22n, therefore, the enable signal is input to the detection counters C, D...N after C. It is now limited to cases where it is being output.

The detection counter N at the last stage outputs a sector mark detection signal when data of 1 is input a predetermined number of times from the read data. Further, reference numeral 23 is a reset occurrence counter, which is a counter for outputting a plurality of reset signals A', B', . CD. E'-
(hereinafter abbreviated as "counters A', B'.C'-J") are connected in parallel.In other words, each counter A'
．． B'. When a clock is input to C' . . . , a selection signal from the multiplexer 24 is input to C' and 6, respectively. This multiplexer 24 connects each detection counter A. B, C. In response to the mode signal output from the M terminal of each counter A'. B'. C
' It is used to output a control signal (selection signal) to operate one of the following. Moreover, each of the counters A', B'. The output side of C'... is connected to the input side of the OR gate 25. As a result, each counter A', B' . When a reset signal is output from any of the counters C', . . ., the reset signal is input from this OR gate 25 to each of the detection counters A to N. Next, the operation of this embodiment will be explained with reference to the time chart shown in FIG. In the same figure, (c) is a waveform showing the read data input to each detection counter A-N, and (d) is a waveform showing each detection counter A-N.
and each counter A', B', C' for reset output
This is a waveform showing the clock input to... In addition, FIG. 3(b) shows each pattern a.d. of each sector mark pattern in which one piece of data is continuous. C. A period corresponding to the number of bits (number of clock pulses) of e and each pattern in which 0 data continues b. It shows the period corresponding to the number of bits (number of clock pulses) of d. In FIG. 1, when data without a sex mark is input to each detection power unc A to N in the Ol detection counter 2l, data of 1 or 0 is input to each detection counter A to N in synchronization with the clock. Start counting the number of times. Then, the detection counter A is set to a predetermined number of bits a' in relation to the number of bits corresponding to the period a.
(In this embodiment, the number of bits corresponding to the period a is 6
When the count reaches a slightly smaller number of bits, the enable signal El (Fig. 2(e)) is output. This enable signal El is applied to AND gates 22c-2.
2n, it is not input to the detection counters after detection counter C, but is only input to detection counter B. Also, when data “1” is input to detection counter A (the sector mark is set to start from data l), the mode signal (for example “”) is output from detection counter A.
10'') is output. The multiplexer 24 receives this mode signal and sends a selection signal to the reset output counter A' to start the operation of the counter A'. This counter A' controls the number of input clock pulses. , and when the count reaches the number of clock pulses corresponding to a period α slightly shorter than the period of pattern a in Fig. 2(b) (see 9 in Fig. 2(a)), the α reset signal (Fig. 2(j) e
output). When this α reset signal is output,
The detection counters other than the detection counter B to which the enable signal E1 from the detection power counter A is input are reset, and the enable signal E3. E4 and sex mark detection signals are prevented from being output. Next, when data of pattern b in Fig. 2(b) is input, detection counter B starts counting the number of times the "O" signal is detected. When only data with a short number of bits b is counted, an enable signal E2 is output. This enable memory E
2 is output only to the detection counter C via the AND gate 22c. Further, the detection power count B outputs a mode signal (for example, ゛OO゜゜) to the multiplexer 24 at the same time as the start of counting. The multiplexer 24 receives this mode signal and outputs a selection signal to the β counter B' to start the operation of the β counter B'. β counter B' counts the number of clock pulses, and when it has counted up to the number of clock pulses corresponding to a period β (see Fig. 2 (a) e) which is slightly shorter than the number of bits in the period of pattern b, β reset is activated. (see Figure 2 (k)). By this β reset signal, the detection power counters D and N other than the detection counters B and C to which the enable signals EIJ5 and E2 have been inputted earlier are reset, and these detection counters D. The enable signal E4 and the sector mark detection signal are prevented from being output from N. Thereafter, detection counters C and D similarly count the number of input times of "1" data and the number of input times of "0" data, respectively, and count the predetermined number of times (bits corresponding to periods d and e in FIG. 2(b)). When the bit count is slightly smaller than the number of bits), the enable signals E3i3 and E4 (the second
(See figures (g) and (f)). Similarly, γ counter C'. for reset output. D'',
E and γ.E in FIG. 2(a), respectively. δ． When the number of clock pulses corresponding to ε is counted, the γ reset signal, δ reset signal, and ε reset signal (Fig. 2 (
ff). (m) and (n)). Through the above operations, each detection counter A. B,C
．． D operate in sequence, and the enable signal El. E2 and E3 are output, and after this enable signal is output, α. β,
γ... By issuing a reset signal, that is, by a combination of these signals, when a normal signal is input, the detection counter A. B. C. D... or it will continue to operate in order without being reset. Then, when the detection counter N at the last stage counts the number of inputs of the data of ゛1゛゜ to the number of bits slightly smaller than the number of bits corresponding to the period e shown in Fig. 2(b), the sector mark detection signal is (See Figure 2 (i)) is now output. On the other hand, when data other than the regular sector mark is input, the reset signal counter A'( B', C'...
) is outputted from α (β, γ...) reset signal, and the detection counters B, C. D... will be reset, so
There is no risk of a sector mark detection signal being output by mistake. As described above, according to this embodiment, the reset output counters A' to E' output a reset signal when a predetermined period α to ε has elapsed. Therefore, each detection counter A. B. C... is each sector mark pattern a. b. Each period of c... (See Figure 2 (b.)'?)
There is no possibility that the number of inputs of "1" or "0" will be counted without limit and the sector mark detection signal will be output erroneously.Furthermore, by using the reset generation counter 23, the previous stage Since the detection counter at the subsequent stage cannot perform a counting operation unless an enable signal is output from the detection counter, the 111.
It is now determined whether the order between the patterns ``...'' and ゛'ooo...゜゛ matches the order of each bartan of the parent sector mark, improving the accuracy of sector mark detection. In addition, in this embodiment, the detection counters A, B, C, . . . and N output the enable signal and the sector mark detection signal depending on the number of times the data of "l" or "'0" is input. , each sector mark pattern a. b. The number of times a', b', c', etc. corresponding to the number of bits of each data c... (see Figure 2 (b)) is counted up to a slightly smaller number of times, so for example, the recording medium 6, sector marks can be detected effectively even if part of the data is missing due to scratches or dust adhesion.
Furthermore, in this embodiment, since a counter using n memory elements can count 2" bits of data, for example, as shown in FIG.
Compared to conventional devices that require n memory elements, the circuit scale can be significantly reduced. [Effects] As described above, according to the present invention, input data is divided into sector mark patterns a, b, . A sector mark detection signal is output if there is a certain degree of agreement with c..., so even if part of the input data is missing due to scratches or dust on the recording medium, the sector mark can be detected. This enables effective detection. Further, each counter is configured such that, unless an enable signal is applied from the preceding stage counter, the counting operation is inhibited by a reset signal from the reset generation counter section. Therefore, the sector mark detection signal is output only when the order between the patterns obtained from the input data matches the order between the sector mark patterns a, b, c... Accuracy will be improved. Further, according to the present invention, by using n storage elements, 2″
Since it counts bit data, the number of memory elements can be reduced compared to conventional sector mark detection devices, and the circuit scale can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a sector mark detection device according to an embodiment of the present invention, FIG. 2 is a time chart for explaining the operation of the sector mark detection device of FIG. 1, and FIGS. Figure 4 is a circuit diagram showing a conventional sector mark detection device. 21...01 detection counter, 23... Reset occurrence counter, A. B. C, D, N...detection counter, B
″,C'.D...Counter.

Claims (1)

[Claims] 1. Each pattern a, b, c, etc. in which one of 1 and 0 data is consecutively formed by a predetermined number of bits on a recording medium.
... are recorded so that these patterns a, b, c... are continuous and the data types 1 and 0 are reversed for each pattern a, b, c... This is a sector mark detection device formed by a plurality of counters A, B, C..., which are connected to each other, and each counter A, B, C... detects one or more of the input data. The number of inputs of 0 data is counted, and the number of inputs is calculated as a predetermined number of times a', b' determined in relation to the number of bits of each data of each pattern a, b, c, . . .
, c'..., each of the counters other than the last stage outputs an enable signal to each of the next stage counters to enable the counting operation regardless of the input of the reset signal, and the last stage counter It consists of a detection counter section that outputs a sector mark detection signal, and a plurality of counters A', B', C'... connected in parallel, and each of these counters A', B', C'...
. . . counts the number of clock pulse inputs corresponding to the start of each counting operation of each of the counters A, B, C .
A reset generation counter that outputs a reset signal to each of the counters A, B, C, etc. when counting up to a predetermined number of times α, β, γ, etc. determined in relation to the number of bits of each data. A sector mark detection device comprising: