SU1169017A1 - Device for synchronizing memory - Google Patents

Abstract

A MEMORY SYNCHRONIZATION DEVICE containing a reversible counter whose direct count input is connected to the output of the first element OR, the outputs are connected to the inputs of the decoder, and the input of the initial installation is connected to the first input of the element AND, and is the input of the initial installation of the device; the inputs of the first group of the AND block, the inputs of the second group of which are the synchronization input of the device, and the outputs are connected to the corresponding inputs of the sync signal generation blocks, the outputs which are connected to the inputs of the block of elements OR, the outputs of the block of elements OR are the synchronization outputs of the device, the first output of the decoder is connected to the first inputs of the element AND-NOT and the first element OR, the second input of the element AND-NOT is connected to the output of the inverter, characterized in that in order to increase the reliability and speed of the device, it contains the first one. the second, third and fourth triggers, the second and third elements OR, the S inputs of the first, second, third and fourth triggers are connected to the output of the AND-NOT element whose input is connected to the second input of the first OR element and the output of the second OR element, the first the input of which is connected to the synchronization input of the first trigger, the first voltage of the third element OR, and is the first control input of the device, the second input is connected to the synchronization input of the second trigger, with the information input and inverse output of the first trigger and second input of the third element OR, respectively, and the third input is connected to the forward output i of the second trigger, the inverse output of which is connected to the third input of the third (L OR element, the fourth input of which is connected to the direct output of the third trigger and is the first output of the device control , R-inputs of the first, second and third flip-flops are connected to the output of the element And, the R-input of the fourth trigger is connected to the input of the initial installation of the reversible counter, the counting input of which is connected to the synchronization input: Another trigger and with a third-party electrical output: e11ta OR, the direct output of the fourth trigger is connected to the information input of the second trigger, and is the second control output of the third trigger, and the synchronization input of the fourth trigger is connected to the second input of the element And the second control input of the devices.

Description

The invention relates to digital computing and can be used to build unified synchronization units for storage devices (GIS) with smooth adaptation to the time characteristics of a storage device.

The aim of the invention is to improve the accuracy and reduce the tuning time.

The drawing shows a functional diagram of a memory synchronization device.

The device contains a reversible counter 1, a decoder 2, a group of elements AND 3-6 group of elements 7-10 delay, a block of elements OR 11, elements AND-NOT 12 and 13, element And 14, three elements OR 15-17, four D-flip-flops 18-21, the device outputs 22, the second control input 23, the synchronization input 24, the initial installation input 25, the first input 26, the controls, the outputs 27 and 28 of the control.

A memory synchronization device can operate in two modes: settings and operating.

Before setting up, a negative pulse is applied to the setup input 25 of the device, which flips the triggers 18–21 and the reversible counter 1, while the logical outputs “O (low voltage levels) are output to the right outputs of the triggers, and voltage levels). At both outputs of the reversible counter 1, low voltage levels are set, as a result of which logical "1 appears at the first output of the decoder 2 and i: i the first input of the And 3 element. Then, using the built-in memory control, the drive starts testing the drive, for which input 24 the devices are given start-up pulses that pass through the And 3 element to the input of the delay element 7. The magnitudes of the delays of the latter are selected minimally with respect to the most high-speed accumulator, therefore, at the outputs of 22 elements OR 11, a sequence of synchronizing signals is formed.

signals corresponding to the maximum speed memory. In the case of successful passing the test to the device input 23, a negative impulse is received, which passes through the element I 14 to the reset inputs of the flip-flops 18-20, confirming their zero state, and setting its back front to “1 flip-flop 21.” From the last shoulder of the last The voltage level is output to the device output 28 as a sign of the end of the tuning.

If an error is detected during testing, a negative impulse arrives at input 26. Since its output occurs at the first erroneous reading, the total number of hits

from the beginning of testing to the appearance of a pulse at input 26 can be reduced to two. It is necessary, however, to take into account that the error may occur due to an accidental failure, and not due to the lack of sufficient time delays between the synchronizing signals. Therefore, with the arrival of the first pulse at the input 26, the fact of a failure is memorized, the time diagram of the memory does not change,

and testing of the accumulator is restarted, and the fact of the failure is remembered by turning on trigger 18, operating in counting mode and firing at the trailing edge of the pulse at its sync input. If in the process of re-passing the test, a negative impulse is again fed to the input 26, a logical "O from the output of the element OR 16 is output, at all three inputs of which at this moment there are low potentials. Then the logical “O through the element OR 15 enters the summing input of the reversible counter 1 and increases its content by one. As a result, a high level of voltage

appears at the second output of the decoder 2. On the trailing edge of the second pulse at the input 26, the flip-flop 18 again zeroes and a positive voltage drop occurs at its inverse output, which goes to the synchronizing

trigger input 19. However, the latter does not trigger, since at its D-input there is a low voltage level from the direct output of trigger 21. Since the start-up pulses now begin to pass through the element 4 to the input

delay element 8; the next testing is carried out according to a new time diagram defined by this element. The duration of the signal passing through the delay element 8 is selected by a few baht,

than element 7, therefore at the outputs 22 a more synchronizing sequence is formed over time

signals. Hereinafter, the described operation of the device is repeated.

If there is a malfunction in the accumulator, independent of its timing diagram, the impulses to the input 26 also arrive at the formation of the synchronizing signals using the delay element 10, which creates the greatest temporary

shifts. Since the first input of the element OR 15 in this case contains a high voltage level, the passage of a logical " O from the output of the element OR 16 to the summing input of the reversible counter 1 is prohibited. At the same time, an IS-NE 13 element is opened, at both inputs of which logical "1" negative pulses are output from its output to the installation inputs of the flip-flops 18-21 and translate them into a single state. A memory failure symptom is output to device 27, and a configuration end indication is output to output 28.

The appearance of the sign of the end of tuning at output 28 (if there is a logical “About at output 27) indicates that the memory is ready for operation, and from that moment the memory synchronization device goes into operation mode. As in the setup mode, the built-in memory control device continues to operate in the operating mode, which produces negative pulses at input 23 when all the cells of the storage device are correctly read and input 26 at the first error detected. If the drive conditions do not change, the pulses are passed to input 23, thereby exposing the zero state of flip-flops 18-20 and the single state of flip-flop 21. When the calculation process changes to input 26, signals indicating errors occur. Then on the first of them the entry “1 to trigger 18 occurs.

If the detected error is caused by a random failure, the next test is successful, the negative pulse is fed to the input 23, and the trigger 18 is zeroed. Otherwise, the second signal is output to the input 26, indicating an error, which increases by one the contents of the reversible counter, writes "O to trigger 18 and" I to trigger 19. Subsequently, the memory runs according to a longer time diagram, and, if errors are insufficient delays between synchronization signals, negative pulses start arriving at input 23, which causes reset to trigger 19. If the cause of errors is an unrecoverable failure in the accumulator, then a third pulse arrives at input 26 which again writes "1 in

trigger 18. As a result, at the second, third and fourth inputs of the element OR 17 there are low potentials and with the arrival of the fourth pulse to the input 26 at its output appears the logical "O, which returns the reversible counter 1 to its previous state and writes its back edge "1 to trigger 20. At output 27 of the device, a memory malfunction indication is displayed, indicating that it is not possible to eliminate the error by changing the timing diagram.

Claims (1)

A MEMORY SYNCHRONIZATION DEVICE containing a reversible counter, the direct count input of which is connected to the output of the first OR element, the outputs are connected to the inputs of the decoder, and the input of the initial installation is connected to the first input of the AND element and is the input of the device’s initial installation, the outputs of the deflector are connected to the inputs of the first group of the block of elements And, the inputs of the second group of which are the synchronization input of the device, and the outputs are connected to the corresponding inputs of the blocks for the formation of clock signals, the outputs of which connected to the inputs of the block of OR elements, the outputs of the block of OR elements are the synchronization outputs of the device, the first output of the decoder is connected to the first inputs of the AND AND NOT element and the first OR element, the second input of the AND gate is NOT connected to the inverter output, characterized in that, with In order to increase the reliability and speed of the device, it contains the first, second, third and fourth triggers, the second and third OR elements, S-inputs of the first, second, third and fourth triggers are connected to the output of the AND-NOT element, the input of which is connected connected with the second input of the first OR element and the output of the second OR element, the first input of which is connected to the synchronization input of the first trigger, the first input of the third OR element and is the first control input of the device, the second input is connected to the synchronization input of the second trigger, with the information input and inverse output the first trigger and the second input of the third OR element, respectively, and the third input is connected to the direct output of the second trigger, the inverse output of which is connected to the third input of the third OR element, even The gated input of which is connected to the direct output of the third trigger and is the first control output of the device, the R-inputs of the first, second, and third triggers are connected to the output of the And element, the R-input of the fourth trigger is connected to the input of the initial installation of the reverse counter, the input of the countdown of which is connected to the synchronization input of the third trigger and with the output of the third element OR, the direct output of the fourth trigger is connected to the information input of the second trigger and is the second control output ^ triple, and the synchronization input tion of the fourth trigger is connected to the second input of the And element and is the second control input device ^.