JPH03253135A - Clock monitoring circuit - Google Patents

Abstract

PURPOSE:To digitally and easily set up a detection time and to improve the accuracy and stability of the clock monitoring circuit by providing the circuit with a backward monitoring circuit and a forward monitoring circuit both of which consist of respective shift registers. CONSTITUTION:Each of flip flops(FFs) 13, 14 and an AND gate 15 forms a reset pulse at a change point of a clock to be monitored. A shift register 16 for inputting the reset pulse, a shifting clock and logic '1' respectively to its reset input, clock input and data input constitutes the backward monitoring circuit. On the other hand, a shift register 17 for inputting an output signal generated when the backward monitoring circuit turns off the clock to be monitored, a shifting clock and logic '1' respectively to its reset input, clock input and data input constitutes the forward monitoring circuit. In such a case, the forward and backward monitoring circuits are attained by full digital circuits. Consequently, the detection time can be digitally and easily set up, the formation of a gate array can be available and the accuracy and stability can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock monitoring circuit, and more particularly to a clock monitoring circuit having forward monitoring and backward monitoring.

[Conventional technology]

An example of a conventional clock monitoring circuit of this type is shown in FIG. 6 and will be described.

A conventional clock monitoring circuit uses two monostable multivibrators as shown in FIG. 6.

In the figure, 63 and 66 are monostable multivibrators (
M/M), this monostable multivibrator 63 is for backward monitoring to confirm that the clock is continuously disconnected, and if the monitored clock 6C1 is continuously disconnected, the resistor 61 and capacitor 2 Q output becomes “0” after the settling time
Nashi, the output of Nant Gate 6 Todoroki becomes "1". The monostable multivibrator 66 is for forward monitoring to confirm that the clock is continuously input.
, when the monitored clock restarts and the Q output of the monostable multipipe rake 63 rises from "0" to rlJ, the trigger is activated, and the Q output remains "0" for a time determined by the resistor 64 and capacitor 65. become. Therefore, while ensuring that the clock restart continues, Nantes Gate 6,
This prevents the output from returning to rOJ. buffer 6
T, 6□, a resistor 68, and a capacitor 69 are a smoothing circuit for preventing output of a whisker-like pulse, which is a sudden pulse that causes a narrow disturbance in the clock interruption signal, when the clock is restarted.

[Problem to be solved by the invention]

In the conventional clock monitoring circuit described above, the detection time is set using a time constant circuit consisting of a resistor and a capacitor. ■ To change the detection time setting, it is necessary to prepare as many resistors and capacitors as there are settings. There is.

■ Since it has an analog part and cannot be fully digitalized, it cannot be converted into a gate array.

■ Lack of accuracy and stability because the setting time depends on analog elements.

There was a problem.

[Means to solve the problem]

The clock monitoring circuit of the present invention includes a reset/ζ pulse control means for creating a reset pulse at a change point of the monitored clock, a reset pulse from the reset/ζ pulse generating means as a reset input, and a shift clock as a clock. Manually, a backward monitoring circuit consisting of a shift register with logic "1" inputted to the data input, an output signal generated when the monitored clock is disconnected from this backward monitoring circuit as the reset input, and a shift clock as the clock input, Logic "1"
It is equipped with a forward monitoring circuit consisting of a shift register that inputs the following data to its data input.

[Effect]

According to the present invention, the front holy night circuit and the rear monitoring circuit can be realized by fully digital circuits, and the detection time can be easily set digitally, and accuracy and stability can be improved.

〔Example〕

Embodiments of the present invention will be described in detail below based on the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a clock monitoring circuit according to the present invention.

In the figure, 11 is a clock oscillation section, and 12 is a clock division section for dividing the output of the clock oscillation section 11.

13.14 is 7-lip 70-tube CF/F), 15 is the Q output of flip-flop 13 and the Q of 7-lip flop 14.
These are AND gates that take an output as an input, and constitute a reset pulse generating means that generates a reset pulse at a change point of the monitored clock. Reference numeral 16 denotes a shift register (SR) in which the reset pulse from this reset pulse generating means is used as a reset input, the shift clock is inputted as a clock input, and logic "1" is inputted as a data input.This shift register 16 has a rear monitoring circuit. It consists of Reference numeral 17 denotes a shift register (SR) in which the output signal generated when the monitored clock is cut off in this backward monitoring circuit is used as a reset input, the shift clock is input as a clock input, and logic "1" is input as a data input. 1T constitutes a forward monitoring circuit.

The clock oscillator 11 serves as a basic clock for operating the clock monitoring circuit shown in FIG. The output of this clock oscillation section 11 is divided by a clock division section 12, and serves as a clock input for the backward monitoring shift register 16 and the forward monitoring shift register 1T.

The flip-flops 13 and 14 and the AND gate 15 are parts that create a reset pulse at the rising edge of the monitored clock, and their operation will be explained with reference to the timing chart of the reset pulse creation part shown in FIG.

In this figure, (a) shows the monitored clock, (b) shows the clock input CK of the 7-ribbon flop 13, (e) the Q output of the flip-flop 13, and (d) shows the flip-flop. The Q output of the 70-tube 14, (.) represents the output (=reset pulse) of the AND gate 15.

When the monitored clock shown as (IL) in FIG. 2 rises, the data is captured at the next rising edge of the clock input CK of the flip-flop 13 shown in FIG. The Q output of becomes "1".

Then, at the next rising edge of the clock input CK of the flip-flop 14, the output of the flip-flop IX)Q becomes "1".
As a result, flip-flop 1
The Q output of 4 becomes rOJ. This 7 lip flop 13
Both the Q output of 7 lip 70 tube 14 are “1”.
”, the output of the AND gate 15 is “1”, so
As shown in FIG. 2, immediately after the rising edge b of the monitored clock, the clock input CKI of the 7 lip-flop j3.
A reset pulse equal to the period is output.

Next, the operation of the rear monitoring circuit will be explained with reference to the rear monitoring timing chart shown in FIG.

In FIG. 3, (a) shows the monitored clock IC, (b) shows the shift register 160!7 set REs, (c) shows the clock aX of the shift register 16, (a) is the Qs output of the shift register 16, (・
) indicates the Q-output (=clock cut signal) of the shift register 1T.

Since "1" is always input as data input to the shift register 16, the data is Q! along with the shift clock. →It is shifted in the Qs direction. However,
Since the shift register 16 is reset every time the monitored clock rises, normally "1" is not shifted to the Qs output.

However, when the monitored clock is cut off, the reset is no longer performed, and after a certain period of time, the Q output also becomes "1", the 1 shift register 17 is reset, and a clock cutoff signal is output. This clock disconnection signal is not output unless the clock disconnection continues for a certain period of time (backward monitoring time), so it is possible to avoid detecting a momentary failure such as a momentary clock disconnection.

The accuracy of the backward monitoring time may have an error of up to one cycle of the shift clock, but if the shift register is not an 8-bit shift register as in the embodiment shown in FIG. By increasing the frequency of the shift clock, it is possible to increase the accuracy as much as possible. The backward monitoring time can be set simply by changing the frequency of the shift clock.1 This is possible by digitally controlling the clock division section 12 to change the number of divisions.
This can be facilitated using an input selector.

Next, the operation of the forward monitoring circuit will be explained with reference to the forward monitoring timing chart shown in FIG.

In Figure 4, (a) shows the monitored clock! 2. (b) is the Q output of the shift register 16,
(e) Fi shift register IT clock manual CK,
(d) shows the shift register ITcDQ output (=clock cut signal).

When the monitored clock continues to be input, the Q output of the shift register IT is "1" as the data input "1" is shifted. Therefore, the Q-output of the shift register 17 is rOJ. When the clock is cut off, the shift register 16's Q.
A reset is activated by the output, and the Qi output of the shift register 17 becomes "1". Here, when the monitored clock restarts, the shift register 16 is reset, so its Qs output becomes "O". Therefore, the shift register 1γ comes out of the reset state, and! Shift register 17
When eight shift clocks are input to , the Qs output of the shift register 1T becomes rOJ.

That is, the clock cutoff signal stops. The clock is restarted by the time the clock disconnection signal stops! The time when II is (
Since the forward monitoring clock must continue longer than the forward monitoring time, it is possible to eliminate the phenomenon in which the open monitoring clock appears to have restarted after a while due to noise or the like. The accuracy and setting of the forward monitoring time are the same as those for the rear monitoring time.

Figure 5 is an explanatory diagram of front holy night/rear monitoring, where (-) indicates the monitored clock! (b) shows a clock cutoff signal.

〔Effect of the invention〕

As explained above, the present invention allows the front monitoring circuit and the rear monitoring circuit to be realized by fully digitalized circuits. As a result, firstly, the detection time can be easily set digitally; It is possible to form a gate array into the second part, and the third part is
This has the effect of improving accuracy and stability.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the clock monitoring circuit according to the present invention, FIG. 2 is a timing chart of the reset pulse generator, FIG. 3 is a rear monitoring timing chart, FIG. 4 is a forward monitoring timing chart, and FIG. The figure is an explanatory diagram of forward monitoring/backward monitoring, and FIG. 6 is a circuit diagram showing an example of a conventional clock monitoring circuit. 11...Clock oscillation section, 12...Clock frequency division section, 13, 14...Flip-flop (F/F
), 15...and gate, 16°17...
Shift register (SR).

Claims (1)

[Claims] A reset pulse generating means for generating a reset pulse at a change point of a monitored clock, a reset pulse from the reset pulse generating means as a reset input, a shift clock as a clock input, and a logic "1" input as a data input. A backward monitoring circuit consisting of a shift register, and a shift register that has an output signal generated when the monitored clock is cut off as a reset input, a shift clock as a clock input, and a logic "1" as a data input. A clock monitoring circuit comprising a forward monitoring circuit.