JPS6389917A - Clock break detecting circuit - Google Patents

Abstract

PURPOSE:To detect clock break only by a logical element by providing two counters that count clock signals, and output signals when the count arrived at a specified value, and at the same time, cleared by rise and fall of clocks. CONSTITUTION:When break that makes the level '1' is caused continuously after fall of a basic clock signal 300, an output signal 303 of a clock rise detecting circuit 4 goes to '0' for a specified time, and a counter 2 is cleared and FF 6 is reset. Thereafter, output of the circuit 4 goes to '1' continuously, and count value of the counter 2 increases and becomes above a specified value. The output signal 200 of the counter 2 becomes 0 and the FF 6 is set. At this time, the output signal 402 of a clock fall detecting circuit 5 becomes '1' continuously, and the count value of a counter 3 increases and becomes above a specified value, and an FF 7 is set. Thus, as counters 2, 3 are provided, break of the basic clock signal can be detected quickly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock disconnection detection circuit that detects disconnection of a basic clock signal of an information processing device.

[Conventional technology]

Traditionally, this type of clock failure detection circuit consists of a retriggerable multi-by-break element triggered by a basic clock signal, and resistor and capacitor circuit components that perform timing adjustment, and when the multi-by-break is in an inactive state. By doing so, disconnection of the basic clock signal is detected.

[Problem that the invention seeks to solve]

By the way, information processing devices are constructed using integrated circuits that use gate arrays, and when a clock disconnection detection circuit is added to such information processing devices, the above-mentioned multi-high breaker element is used. Conventional clock disconnection detection circuits using resistors and capacitors cannot be incorporated into integrated circuits for gate arrays, and must be installed as external circuits, resulting in problems such as an increase in the number of parts and an increase in the size of the device. there were.

The present invention solves the above-mentioned problems, and its purpose is to provide a lock failure detection circuit that can be easily incorporated into an integrated circuit using a gate array.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention generates a clock signal having a period shorter than the period of the basic clock signal in a clock interruption detection circuit that detects an interruption state of the basic clock signal of an information processing device. a clock generation circuit; a clock rise detection circuit that outputs a signal at the rise of the basic clock signal; a clock fall detection circuit that outputs a signal at the fall of the basic clock signal; and from the clock generation circuit. a first counter that counts the clock signals of the clock signal and outputs a signal Σ when the counted value reaches a specified value, and the counted value is cleared by the output signal of the clock rising edge detection circuit;・Count the 7 signals,
A clock loss detection circuit comprising: a second counter which outputs a signal when the count value reaches a specified value and whose count value is cleared by the output signal of the clock fall detection circuit.

[For production]

The count value of the first counter is cleared every time the basic clock signal rises, and the count value of the second counter is cleared every time the basic clock signal falls. Therefore,
When a break in the basic clock signal occurs such that the basic clock signal becomes "1" continuously, a signal indicating the break in the basic clock signal is output from the second counter, and then the first counter outputs a signal indicating the break in the basic clock signal.
A signal indicating a break in the basic clock signal is output from the first counter, and if a break in the basic clock signal occurs such that the basic clock signal becomes "0" continuously, a signal is output from the first counter. After that, a signal is output from the second counter.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIGS. 2 to 4 are explanatory diagrams of the operation of FIG. 1.

The clock generation circuit 1 is composed of an AND element 10, n buffers 11-1 to 11-n composed of, for example, AND elements, and an inverter 12, and receives an external trigger signal 1.
It is activated by 00. As shown in FIG. 2, when the external trigger signal 100 becomes "1", first the output signal 101 of the AND element 10 becomes "1", and then the buffer 11-1
The output signals of 11-n become "1" sequentially. in this case,
The output signal 102 of the buffer 11-n is output from the AND element 10.
And due to delays occurring in buffers 11-1 to 11-n,
“1” after a delay of time TDO from the external trigger signal 100
becomes. As the output signal 102 of the buffer 11-n becomes "ul", the output signal 103 of the inverter 12 becomes "ul".
O" and is fed back to the AND element 10. As a result, the output signal 101 of the AND element 10 becomes 0",
Thereafter, the output signals of the buffers 11-1 to 11-n are sequentially "
0". In this case, the output signal 1 of the buffer 11-n
02 becomes “0” when the output signal 10 of the inverter 12
It is time TD after 3 becomes "0". Therefore,
The buffer 1Ln holds its output signal 102 at "1" for a time T D + which is the sum of the time TD0 and the delay time of the inverter 12.

Further, when the output signal 102 of the buffer 11-0 becomes "0", the output signal 103 of the inverter 12 becomes "1" and is fed back to the AND element 10. As a result, the output signals of the buffers 11-1 to 11-n sequentially become "1", and the output signal 102 of the buffer 11-n becomes "1" after time TDO after the output signal 103 of the inverter 12 becomes "1".
”. Therefore, the buffer 11-n is stored at the time T D
The time TD which is the sum of o and the delay time of the inverter 12
, the output signal 102 is held at "0".

In this way, when the external trigger signal lOO is “1”,
Since the output signal 102 of the buffer 11-n changes from 0" to "1" or from 1" to "0" every predetermined time TD, the clock signal 102 with a period of 2 TD is output from the clock generation circuit l. will be done. The buffer 11-1 is arranged so that the period of the clock signal 102 is a sufficient ratio compared to the period of the basic clock 300 of the information processing device.
~11-n is set. Also,
While the external trigger signal lOO is “θ”, the buffer 10-
Since the output signal 102 of n is 0'', no clock signal is generated. Also, as the external trigger signal 100, for example, an output confirmation signal of a power supply unit is used.

The clock signal 102 from the clock generation circuit 1 is the first.
It is applied to the clock terminal CLK of the second counters 2 and 3, and the first. The second counters 2 and 3 each count the clock signal 102, and set their output signals 200 and 201 to "0" each time the counted value reaches a specified value. Further, a clock rise detection circuit 4. is connected to the reset terminal R3T of the counters 2 and 3. Output signal 303 of clock fall detection circuit 5
, 402 are added, and the signals 303, 402 are O''
As a result, the count values of counters 2 and 3 are cleared.

As shown in FIG. 3, the clock rise detection circuit 4 sets its output signal 303 to "0" for a predetermined period of time at the rise of the basic clock signal 300 of the information processing device, and has m buffers. 20-1 to 20-m and inverter 21
and a NAND element 22.

The basic clock signal 300 applied to the clock rise detection circuit 4 is applied to one input terminal of the NAND element 22, and is also applied to the buffers 20-1 to 20-m and the inverter 2.
1 to the other input terminal of the NAND element 22. Here, the output signal 30 of the m-th stage buffer 20-m
1 is the basic clock signal 300 for a predetermined time TD2 (TD2
is the total delay time of each buffer 20-1 to 20-n+)
Since the output signal 302 of the inverter 21 is the inverted version of the output signal of the buffer 20-m, the output signal 303 of the NAND element 22 is delayed at the rising edge of the basic clock signal 300 as described above. It becomes "0" for a predetermined time.

Further, as shown in FIG. 4, the clock fall detection circuit 5 sets its output signal 402 to 0'' for a predetermined time at the fall of the basic clock signal 300 of the information processing device, and detects p signals. It is composed of buffers 30-1 to 30-p and a gate element 31. A basic clock signal 300 applied to the clock fall detection circuit 5 is transmitted to the gate element 3.
1 and is applied to the other input terminal of the gate element 31 via p buffers 30-1 to 30-p.

Here, the output signal 401 of the p-th stage buffer 30-p is the basic clock signal 300 delayed by a predetermined time T'D3 (T0n is the total delay time of each buffer 30-1 to 30-p). Therefore, the output signal 402 of the gate element 31 becomes "0" for a predetermined time from the fall of the basic clock signal 300, as described above.

Now, while the basic clock signal 300 is being output normally, the output signal 303 of the clock rise detection circuit 4 becomes "0" every time the basic clock signal 300 rises, and the count value of the counter 2 is cleared and the flip-flop 6 is reset. Here, as mentioned above, the counter 2 receives the clock signal 10 from the clock generation circuit l.
2, and when the count value becomes equal to or greater than a specified value, the output signal 200 is set to "0". By setting the clock number to be larger than the clock number of the clock signal 102 output from the counter 2, the output signal 200 of the counter 2 is held at "1". That is, while the basic clock signal 300 is being output normally, the output signal of the flip-flop 6 is “
It will be held at θ″.

Further, while the basic clock signal 300 is being output normally, the output signal 402 of the clock fall detection circuit 5 becomes "0" every time the basic clock signal 300 falls, and the current value of the counter 3 is cleared. Since the flip-flop 7 is reset, the count 3 sets the specified value for setting the output signal 201 to "0" as the clock output from the clock generation circuit 1 during one period of the basic clock signal 300. By setting the clock number to be larger than the clock number of the counter 3 output signal 20
1 will always be held at "1". That is, while the basic clock signal 300 is being output normally, the output signal of the flip-flop 7 is also held at "0".

Next, the operation when the basic clock signal 300 is disconnected will be explained.

As shown in FIG. 5, if a break in the basic clock signal 300 occurs such that the level of the basic clock signal 300 becomes "1" continuously after the basic clock signal 300 rises, At this time, the output signal 303 of the clock rise detection circuit 4 becomes 0'' for a predetermined period of time, the count value of the counter 2 is cleared, and the flip-flop 6 is reset. Since it becomes "1" continuously, the current clearing of the counter 2 and the flip-flop 6 are not performed. Therefore, the counter 2 that counts the clock signal 102 output from the clock generation circuit 1
The value of 1 to 1 gradually increases and becomes equal to or higher than the specified value. As a result, the output signal 200 of the counter 2 becomes "0",
Flip-flop 6 is set. Also, in this case,
Since the output signal 402 of the clock fall detection circuit 5 also becomes "1" continuously, the count value of the counter 3 is not cleared and the flip-flop 7 is not set.

Therefore, the clock signal 102 from the clock generation circuit 1
The count value of the counter 3 gradually increases and becomes equal to or higher than the specified value. As a result, the output signal 201 of the counter 3 becomes "0" and the flip-flop 7 is set. That is, the basic clock signal 30 as shown in FIG.
If a disconnection of 0 occurs, flip-flop 7 is set, and then flip-flop 6 is set.

Further, the basic clock signal 300 is such that the level thereof becomes "0" continuously after the falling of the basic clock signal 300.
If a disconnection occurs, the output signal 4 of the clock fall detection circuit 5 will basically be detected at the fall of the clock signal 300.
02 becomes "0", the count value of the counter 3 is cleared, and the flip-flop 7 is reset, but from now on,
Since the output signal 402 of the clock fall detection circuit 5 becomes "1" continuously, the count value of the counter 3 is not cleared and the flip-flop 7 is not reset.

Therefore, the clock signal 102 from the clock generation circuit 1
The count value of the counter 3 gradually increases and becomes equal to or higher than the specified value. As a result, the output signal 201 of count 3 becomes "0" and the flip-flop 7 is set. In addition, in this case, since the output signal 303 of the clock rise detection circuit 4 also becomes "1" continuously, the counter 2
Clearing of the count value and resetting of the flip-flop 6 are no longer performed. Therefore, the count value of the counter 2 that counts the clock signal 102 gradually increases,
The value exceeds the specified value. As a result, the output signal 2 of counter 2
00 becomes "0" and the flip-flop 6 is set. That is, the basic clock signal 3 whose level becomes "0" continuously after the fall of the basic clock signal 300.
00, the flip-flop 7 is set and then the flip-flop knob 6 is set, contrary to the case shown in FIG.

In this way, since the present embodiment is provided with the first and second counters 2 and 3, compared to the case of either one,
Discontinuation of the basic clock signal can be quickly detected.

〔Effect of the invention〕

As described above, the present invention allows a clock loss detection circuit to be constructed using only logic elements, and therefore has the advantage that the clock loss detection circuit can be incorporated into an integrated circuit using a genit array. Furthermore, the present invention also includes:
The first counter counts the clock signal from the clock generation circuit and is cleared at the rising and falling edges of the basic clock signal.

Since the second counter is provided, there is also the advantage that disconnection of the basic clock can be quickly detected.

[Brief explanation of the drawing]

1 is a block diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of the clock generation circuit 1, FIG. 3 is an explanatory diagram of the operation of the clock rise detection circuit 4, and FIG. 4 is an illustration of the operation of the clock fall detection circuit 5. FIG. 5 is an explanatory diagram of the operation when the basic clock signal is cut off. In the figure, ■... clock generation circuit, 2. 3...
・First. Second counter, 4... Clock rising detection circuit, 5... Clock falling detection circuit, 6, 7...
flip flop.

Claims (1)

[Scope of Claims] A clock disconnection detection circuit for detecting a disconnection state of a basic clock signal of an information processing device includes: a clock generation circuit that generates a clock signal having a period shorter than the period of the basic clock signal; a clock rising detection circuit that outputs a signal at the rising edge of the clock signal; a clock falling detection circuit that outputs the signal at the falling edge of the basic clock signal; counting the clock signals from the clock generating circuit; a first counter that outputs a signal when the counted value reaches a specified value and whose counted value is cleared by the output signal of the clock rising edge detection circuit; A clock interruption detection circuit comprising: a second counter which outputs a signal upon reaching a specified value and whose count value is cleared by the output signal of the clock fall detection circuit.