JP2985582B2 - Clock circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention is a clock circuit BACKGROUND OF THE, in particular, Den
ECL clocks with a low logical level provided in the transmission path
Input circuit.

[0002]

2. Description of the Related Art Conventionally, this type of clock circuit has a technique disclosed in Japanese Patent Laid-Open No. 1-97010. FIG. 2 is a circuit diagram showing an example of the related art. The clock signal a input from the input terminal 1 is cut by the capacitor 2, terminated by the resistor 3, and input to the OR circuit 4. The terminating resistor 3 is composed of a feedback resistor 6 and a capacitor 7 which receive the inverted output d of the OR circuit 4.
And the integrated value e of the inverted output d of the clock signal a is O
The signal is fed back to the input b of the R circuit 4.

FIG. 3 is a waveform diagram for explaining the operation of FIG. 2. A broken line is a waveform immediately after a clock is input, and a solid line is a waveform in a steady state in which the time has changed and the duty has been corrected. The time constant of this time transition is determined by the integrator 8 including the resistor 6 and the capacitor 7 connected to the inverted output d in FIG. The waveform shown in FIG. 3 is a case where the duty of the input clock signal a is smaller than 50%, and the integrated value e fed back from the inverted output d to the OR circuit 4 changes the input signal b to a duty of 50%. Push up to the positive voltage side until

[0004]

In the conventional clock circuit, as shown in the signal waveform diagram of FIG. 4, the logic level of the input clock signal a is fixed at H level or L level (L level in FIG. 4). Then, the feedback level e applied to the terminating resistor 3 becomes the threshold level of the logic circuit, that is, the input b of the OR circuit 4 becomes an uncertainty level which is neither H level nor L level. However, there is a disadvantage that a large oscillation output is output.

[0005]

A clock circuit according to the present invention comprises an input signal branching circuit for branching an input signal into two and outputting the signal, and receiving one of the two branched input signals for a DC component of the signal. Except for a capacitor, a terminating resistor, an OR circuit that outputs an inverted output and a non-inverted output, and a feedback circuit that is connected to the inverted output and that feeds back the integrated value of the clock signal as a threshold level to the input. A circuit, a flip-flop receiving the other input signal at the clock input, a reset signal generator for periodically generating a signal at a reset input of the flip-flop, an output of the clock correction circuit and a flip-flop. And an AND circuit receiving the output.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. The clock signal input from the input terminal 1 is branched by the input signal branch circuit 10, output to the clock correction circuit 11 and the flip-flop 20, and connected to the output terminal 9 via the AND circuit 12. The clock correction circuit 11 includes a capacitor 2 for removing the DC component of the clock signal, a terminating resistor 3, an OR circuit 4 for outputting an inverted output and a non-inverted output, and a threshold connected to the inverted output for integrating the clock signal. .Feedback circuit 8 that feeds back to input as level
Consists of

The clock signal input from the input terminal 1 is
The signal is inverted by the OR circuit 4 and fed back as an offset value such that the duty becomes 50% by the integration operation of the clock signal performed by the resistor 6 and the capacitor 7 in the feedback circuit 8. The clock signal at input terminal 1 is H
When the clock correction circuit 11 is fixed at the L level or the L level, the clock correction circuit 11 oscillates in the same manner as in the prior art, but the output branched by the input branch circuit 10 is received by the flip-flop 20, and Since the L level is output to the AND circuit 12, the output from the clock correction circuit 11 is not output to the output terminal 9. The reset signal generator 30 is connected to a reset input of the flip-flop 20, and periodically generates a reset signal. The frequency of occurrence of the reset signal differs depending on the device in which the clock input circuit is incorporated, but is usually set to a value one digit shorter than the waiting time for determining that a line failure has occurred. The resistor 21 is for terminating the input of the flip-flop 20, and the resistors 22 and 23 are for terminating the input of the AND circuit 12.
The resistor 5 is for passing an output bias current when the OR circuit 4 is an ECL circuit.

[0009]

As described above, the clock circuit of the present invention has a flip-flop for detecting that the clock signal is fixed at the H level or the L level. It is possible to detect the state of the clock at the generated time intervals, and there is an effect that the oscillation signal is not output from the clock duty correction circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of the related art.

FIG. 3 is a signal waveform diagram for explaining a normal operation of FIG. 2;

FIG. 4 is a signal waveform diagram for explaining a malfunction in FIG. 2;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal 2, 7 Capacitor 3, 21, 22, 23 Terminating resistor 4 OR circuit 5 Bias resistor 6 Feedback resistor 8 Feedback circuit 9 Output terminal 10 Input signal branch circuit 11 Clock correction circuit 12 AND circuit 20 Flip-flop 30 Reset signal generator

Claims (2)

(57) [Claims] 1. An input signal branching circuit for branching an input signal into two, outputting one of the two branched input signals, a capacitor for removing a DC component of the signal, a terminating resistor, and an inverting circuit. A clock correction circuit having an OR circuit that outputs an output and a non-inverted output, a feedback circuit connected to the inverted output, and a feedback circuit that feeds back an integrated value of the clock signal as a threshold level to an input; A clock input, a reset signal generator that periodically generates a signal at a reset input of the flip-flop, and an AND circuit that receives an output of the clock correction circuit and an output of the flip-flop. Characteristic clock circuit. 2. The reset signal generation circuit according to claim 2, wherein
Signal occurrence frequency is about one
2. The clock circuit according to claim 1, wherein the clock circuit is set to a value that is an order of magnitude shorter.