JPH04336724A - Serial receiver - Google Patents

Abstract

PURPOSE:To synchronize serial reception in the serial data receiver. CONSTITUTION:A signal inputted from a serial clock input means 10 is inputted to 1st and end level discrimination means 100, 110, and every time the 1st discrimination means 100 discriminates it that the signal level is a predetermined setting level, an output of a register means 30 is set to a counter means 40 and an output of the 2nd discrimination means 110 is used to count the data by a counter means 40 repetitively. Thus, a head bit of a block of a serial reception data is recognized and the synchronization in the unit of blocks attained.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvements in serial receiving apparatus, and more particularly to synchronization of serial data reception.

0002

2. Description of the Related Art FIG. 2 is a block diagram showing an example of a conventional serial receiving device, in which 10 is a serial clock input means for inputting a serial clock, 20 is a serial data input means for inputting serial reception data, and 30 is a serial clock input means for inputting a serial clock. Register means for setting the number of bits per block of serial data; 40 is a counter means that counts down the set data using a clock from the serial clock input means 10; 50 is a register means for counting down the set data by a clock from the serial clock input means 10; Comparing means for determining underflow, 60 a serial reception end flag indicating the output of the comparing means 50, 70 shift register means for shifting and inputting the data of the serial data input means 20 using the clock from the serial clock input means 10; 80 is a data output means for outputting parallel data from the shift register means 70.

Next, the operation of the conventional example will be explained. The number of bits per block of serial data is set and stored in the register means 30 in advance, and the data in the register means 30 is set in the counter means 40 in an initial state. next,
The counter means 40 counts down by the clock from the serial clock input means 10, and at the same time the data from the serial data input means 20 is transferred to the shift register means 70.
Shift input the data. An underflow of the counter output from the counter means 40 is detected by the comparison means 50, and a serial reception end flag 60 is set. The output of the serial reception end flag 60 becomes a signal for setting the output of the register means 30 in the counter means 40. The output of the shift register means 70 is outputted from the data output means 80. The serial reception end flag 60 serves as an interrupt input signal to a microcomputer or the like.

0004

However, in the conventional example described above, it is not possible to recognize the leading bit of a data block of serial data. Therefore, if noise of one pulse or more occurs in the serial clock signal, the reliability of the captured data is significantly reduced.

[0005]

SUMMARY OF THE INVENTION In order to solve the above drawbacks, the present invention recognizes the leading bit of a data block of serial data by changing the voltage level of a serial reception clock.

That is, the specific configuration of the serial receiving device of the present invention includes a first input terminal for inputting a serial reception clock, a second input terminal for inputting serial reception data, and a terminal for inputting a serial reception clock, and a second input terminal for inputting serial reception data. register means for storing; first determining means for determining that the input level from the first input terminal is a set level; and the input level from the first input terminal is equal to or lower than the set level. a second discriminating means for discriminating, a counter means for setting the output of the register means according to the output of the first discriminating means, and counting down according to the output of the second discriminating means, and the second input terminal. The present invention is configured to include a shift register means for shifting input data from the second determining means according to the output of the second determining means, and a comparing means for determining an underflow of the counter means.

[0007]

[Operation] With the above configuration, in the present invention, the counter means can set the output of the register means by the output of the first determining means every time the input level from the first input terminal changes to the set level. Since the process is repeated, it is possible to obtain a serial receiving device that can synchronize serially received data in units of blocks.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 and 3 to 6. FIG. 1 is an example of a block diagram of a serial receiving device according to the present invention, in which 10 is a serial clock input means as a first input terminal for inputting a serial reception clock, and 20 is a second input for inputting serial reception data. Serial data input means as a terminal; 100 is first level determination means for determining that the input signal level from the serial clock input means 10 is a set value; 110 is the serial clock input means 1;
30 is a register means for storing the number of bits per block of serial data; 40 is the first level determining means; 30 is a register means for storing the number of bits per block of serial data; counter means 50 which inputs the output of the register means 30 according to the output of 100 and counts down the set data according to the clock output from the first level determination means 110;
60 is a serial reception end flag indicating the output of the comparison means 50. 70 is a comparison means for determining whether the output of the counter means 40 has underflowed due to a counting operation. 70 is a serial reception end flag indicating the output of the comparison means 50.
80 is a data output means for outputting the parallel data of the shift register means 70.

FIG. 3 shows a serial clock signal input to the serial clock input means 10, and FIG. 4 shows a serial data signal input to the serial data input means 20. 5 shows the output waveform of the first level determining means 100, and FIG. 6 shows the output waveform of the second level determining means 110.

In this embodiment, the number of bits per block of serial data is set to "8", and the value set in the register means 30 is "7", which is "8" minus "1".
”. First, in the serial clock input means 10, FIG.
When the first pulse of the serial clock shown in FIG. As shown in FIG. 5, while the input level is at the set level (VM level), V
Outputs a waveform that becomes L level. Similarly, the second level determining means 110 determines that the level is below the set level (VM level), resulting in the output waveform shown in FIG.

Next, when the second and subsequent pulses of the serial clock shown in FIG.
determines that it is not at the set level (VM level), and outputs the VH level as shown in FIG. Similarly, the second level determining means 110 determines that the level is below the set level (VM level), resulting in the output waveform shown in FIG.

The value "7" set in the register means 30 is set in the counter means 40 at the VL level of the signal shown in FIG. 7" down count operation. If the comparison means 50 determines that the output of the counter means 40 has underflowed, the serial reception end flag 60 can determine the end of serial reception. 4 is input to the serial data input means 20, this data is shifted in by the shift register means 70 at every rising edge of the signal shown in FIG. 6, and is output as parallel data from the data output means 80. .

Therefore, in this embodiment, each time the input level of the serial reception clock of the serial clock input means 10 reaches the set level (VM level), the counter means 4
Since the output of the register means 30 is repeatedly set to 0, it is possible to correctly determine the start of communication when receiving serial data.

[0014]

[Effects of the Invention] As explained above, according to the serial receiving device of the present invention, it is possible to correctly determine the start of communication when receiving serial data, so that noise of one pulse or more is not generated in the serial clock signal. It is also possible to correctly recognize the first bit of a data block of serial data.

Similarly, by configuring a plurality of means for determining the level of the serial reception clock, it is possible to not only detect the header of serial reception data but also detect the serial block of a system in which one block is composed of a plurality of pieces of serial reception data. It can also be used for header detection.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a block configuration of a serial receiving device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a block configuration of a conventional serial receiving device.

FIG. 3 is a diagram showing a waveform of a serial reception clock.

FIG. 4 is a diagram showing a waveform of serial data.

FIG. 5 is a diagram showing an output waveform of the first level determining means.

FIG. 6 is a diagram showing an output waveform of a second level determining means.

[Explanation of symbols]

10 Serial clock input means (first
20 Serial data input means (second input terminal) 30 Register means 40 Counter means 50 Comparison means 60 Serial reception end flag 70
Shift register means 80
Data output means 100 First level discrimination means (first discrimination means) 110 Second level discrimination means (second discrimination means)

Claims (1)

[Claims] Claims: 1. A first input terminal for inputting a serial reception clock, a second input terminal for inputting serial reception data, register means for storing the number of bits of serial data, and a first input terminal for inputting a serial reception clock; a first determining means for determining that an input level from the first input terminal is at a set level; a second determining means for determining that an input level from the first input terminal is equal to or lower than the set level; counter means that sets the output of the register means according to the output of the discriminating means and counts down according to the output of the second discriminating means; What is claimed is: 1. A serial receiving device comprising: shift register means for inputting a shift signal; and comparison means for determining underflow of said counter means.