KR100431748B1 - Vertical synchronous signal Detector - Google Patents

Abstract

The present invention is to provide a vertical synchronization signal detection apparatus for reducing the interrupt usage of the receiving system when detecting the vertical synchronization signal, and sensitively reacts to the change of the vertical synchronization signal to increase the processing speed of the receiving system. According to the present invention, the vertical synchronization signal is inputted up or down according to the logic level of the vertical synchronization signal. When the vertical synchronization signal maintains the first or second logic level for a predetermined period, it is part of the vertical synchronization signal. A vertical synchronization signal detector for recognizing and generating a clock; A vertical synchronizing signal change detector for counting a clock output from the vertical synchronizing signal detector for a predetermined period and comparing the same with the number of clock counts in a previous state, and detecting a change in the vertical synchronizing signal; And an overflow detector configured to generate an overflow signal for recognizing that the vertical sync signal is not applied when only a second logic level is output for a predetermined period by the vertical sync signal change detector, wherein the vertical sync signal detector includes: A vertical synchronizing signal input unit for detecting a logic level of the vertical synchronizing signal to generate an N-bit output signal, and a detection unit for generating a clock by determining whether the vertical synchronizing signal is input by logically combining the output of the vertical synchronizing signal input unit; The vertical synchronizing signal input unit generates an output of N bits, and inputs a vertical synchronizing signal as an input, and counts up-count when the signal of the first logic level is applied and down-counts when the signal of the second logic level is applied. When the signal of the first or second logic level is applied for a certain period, the outputs of the N bits all become the first logic level or The N-bit up-down counter which becomes a 2 logic level, and the detection unit, when the output of the N-bit output from the N-bit up-down counter are all the first logic level or all the second logic level, the first logic level A first NOR gate that outputs a first logic level when the logical AND gate to be output and the N-bit output from the N-bit up-down counter vertical synchronization signal input unit are all at a second logic level, and the AND gate And a logical sum gate for inputting the output of the AND gate and the first NOR gate, a first transition detector for detecting a moment at which the output value of the first NOA gate transitions, and a moment at which the output value of the AND gate transitions. It provides a vertical synchronization signal detector comprising a second transition detector for detecting.

Description

Vertical synchronous signal detector

The present invention relates to a vertical synchronizing signal detector, and more particularly, to a vertical synchronizing signal detector capable of operating at high speed with less load on a system using a vertical synchronizing signal.

In general, in order to restore a video signal transmitted from a system for transmitting a video signal to an original video, a timing matching process, that is, a synchronization process, is required at the transmitting side and the receiving side. For this synchronization processing, the normal video signal transmitting side includes the vertical and horizontal synchronizing signals and transmits the video signal.

As described above, the standard specification of the vertical synchronization signal included in the image signal will be briefly described with reference to FIG. 1.

Referring to FIG. 1, the vertical synchronization signal has a pulse width of at least 10 uS and at most 600 uS in a high level state, and one period of a pulse having such a pulse width is at least 5 mS and at most 25 mS.

In addition, the vertical sync signal included in the video signal transmitted from the transmitter is a vertical sync signal when the low level is constant for a positive polarity, and the high sync level is constant for a negative polarity. The pulse is a vertical synchronization signal, and as described above, the vertical synchronization signal has a minimum period and a maximum period, and is sufficient to detect the vertical synchronization signal when the transmitting side receives the image signal after receiving the image signal. Design should be given margin.

Therefore, in a system such as a screen display device using a synchronization signal, the analysis capability of the synchronization signal becomes a very important factor in determining the performance of the product. Analysis elements of the synchronization signal include the presence, frequency, and polarity of the signal. Analysis of these factors determines the operation of the system.

Conventional methods for analyzing the existence of the vertical synchronization signal is largely a direct (direct) method and an indirect (indirect) method.

First, the direct method is a method of examining whether a change of a terminal to which the vertical synchronous signal is input periodically occurs by checking a state of a terminal to which the vertical synchronous signal is input at a predetermined time with a software program.

If the vertical synchronization signal is not detected for a certain period or more periods in consideration of the margin according to the mutually agreed rule at the transmitting side and the receiving side, the receiving side determines that the vertical synchronization signal has failed to be detected and is four times the predetermined period. If the vertical synchronizing signal is not detected during the above time, it is determined that the vertical synchronizing signal is not input.

Next, the indirect method utilizes the vertical synchronizing signal as an interrupt signal applied to the receiving system, counts the occurrence period of the interrupt generated every time the vertical synchronizing signal is applied by a counter, reads the value, and changes the value. Is to check if it is constant.

At this time, the amount of change in the count value that counts the number of vertical sync signals detected within a certain period in which the vertical sync signals are detected based on the vertical sync signals that arrive latest according to the mutually agreed rule of the transmitter and the receiver. If this is not constant, it is determined that the vertical synchronization signal has failed to be detected at any point, or it is determined that the period of the vertical synchronization signal has changed according to the change of the mode, and if there is no change in the counted value, the vertical synchronization signal is externally inputted. Be judged not

The biggest problem with the direct method and the indirect method is that in both the direct and indirect methods, the system must allocate a specific counter dedicated to the monitoring of the vertical synchronization signal, and dedicate the interrupt having the highest priority of the system. It should be used.

Dedicated allocation of resources to be shared in terms of resource utilization of the system increases application disadvantages, and frequent use of the highest priority system interrupts can significantly disrupt the performance of other lower priority functions. Therefore, it becomes a factor that lowers the efficiency of the whole system.

In addition, when determining the change of the vertical synchronizing signal by using the software in the direct method, there is a problem in that the response speed of the system to the change of the external vertical synchronizing signal is remarkably lowered because the change of the signal is not sensed sensitively.

The present invention has been proposed to solve the above-described problems, and when detecting a vertical synchronization signal, it reduces the use of interrupts of the receiving system and increases the processing speed of the receiving system by making it sensitive to changes in the vertical synchronization signal. It is an object of the present invention to provide a vertical synchronization signal detection device.

1 is a timing diagram showing a standard specification of a vertical synchronization signal included in a video signal;

2 is a block diagram of a vertical synchronization signal detector according to an embodiment of the present invention;

3 is a timing diagram for explaining the operation of the N-bit up-down counter according to the present invention;

* Explanation of symbols for the main parts of the drawings

100: vertical sync signal detector 200: vertical sync signal change detector

300: overflow detection unit

According to an aspect of the present invention, a vertical synchronization signal is input to up or down count according to a logic level of the vertical synchronization signal, and the vertical synchronization signal maintains a first or second logic level for a predetermined period. A vertical synchronization signal detector for generating a clock by recognizing this as a part of the vertical synchronization signal; A vertical synchronizing signal change detector for counting a clock output from the vertical synchronizing signal detector for a predetermined period and comparing the same with the number of clock counts in a previous state, and detecting a change in the vertical synchronizing signal; And an overflow detector configured to generate an overflow signal for recognizing that the vertical sync signal is not applied when only a second logic level is output for a predetermined period by the vertical sync signal change detector, wherein the vertical sync signal detector includes: A vertical synchronizing signal input unit for detecting a logic level of the vertical synchronizing signal to generate an N-bit output signal, and a detection unit for generating a clock by determining whether the vertical synchronizing signal is input by logically combining the output of the vertical synchronizing signal input unit; The vertical synchronizing signal input unit generates an output of N bits, and inputs a vertical synchronizing signal as an input, and counts up-count when the signal of the first logic level is applied and down-counts when the signal of the second logic level is applied. When the signal of the first or second logic level is applied for a certain period, the outputs of the N bits all become the first logic level or The N-bit up-down counter which becomes a 2 logic level, and the detection unit, when the output of the N-bit output from the N-bit up-down counter are all the first logic level or all the second logic level, the first logic level A first NOR gate that outputs a first logic level when the logical AND gate to be output and the N-bit output from the N-bit up-down counter vertical synchronization signal input unit are all at a second logic level, and the AND gate And a logical sum gate for inputting the output of the AND gate and the first NOR gate, a first transition detector for detecting a moment at which the output value of the first NOA gate transitions, and a moment at which the output value of the AND gate transitions. It provides a vertical synchronization signal detector comprising a second transition detector for detecting.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

2 is a block diagram of a vertical synchronization signal detector according to an embodiment of the present invention.

Referring to FIG. 2, the vertical sync signal detector according to an embodiment of the present invention inputs a vertical sync signal and counts up or down according to a logic level of the vertical sync signal. When the high or low level is maintained, the vertical sync signal detector 100 generates a clock by recognizing it as part of the vertical sync signal, and the clock output from the vertical sync signal detector 100 is counted for a predetermined period and then When only the low level is output from the vertical synchronizing signal change detection unit 200 and the vertical synchronizing signal change detection unit 200 for detecting a change in the vertical synchronizing signal when it is not the same as the number of clock counts in the previous state. The overflow detector 300 generates an overflow signal for recognizing that the vertical synchronization signal is not applied. do.

Specifically, the vertical synchronizing signal detector 100 includes an N-bit up-down counter 110 for generating an N-bit output signal by detecting a logic level of the vertical synchronizing signal, and the N-bit up-down counter. And a detector 120 for logically combining the outputs of the outputs 110 to determine whether the vertical synchronization signal is input and to generate a clock.

The N-bit up-down counter 110 generates an N-bit output, and inputs a vertical synchronization signal to up-count when a high level signal is applied and down-count when a low level signal is applied, When a high or low level signal is applied for a predetermined period, the N bit output is an N bit up-down counter in which all of the N bit outputs become high level or low level, and the detection unit 120 performs the N bit up-down. When the outputs of the N-bits output from the counter 110 are all at the high level, the AND gate 121 outputting the high level and the outputs of the N-bits output from the N-bit up-down counter 110 are both present. The NOR gate 122 that outputs a high level when the level is low, the OR gate 123 that receives the outputs of the AND gate 121 and the NOA gate 122, and the output value of the NOA gate 122 To detect the moment of transition The detection unit 124 and the embodiment is configured to include a transition detector 125, for detecting the moment when the output value of the logical product gate 121 transition,

The vertical synchronizing signal change detector 200 may include an M bit counter 210 for counting a clock output from the vertical synchronizing signal detector 100 and a count value of a previous state output from the vertical synchronizing signal detector 100. And a register 220 to store the comparator 230 and a comparator 230 for generating an interrupt by comparing the output values of the M bit counter 210 and the register 220.

The overflow detection unit 300 is initialized when the outputs of the Noah gates 310 and 320 and the outputs of the Noah gate 310 are inputted as the inputs of the clock count number of the previous state stored in the vertical synchronization signal change detection unit 200. A P bit counter 330 for generating an overflow signal when the output of the NOR gate 320 is at a low level for a predetermined period and a transition detector for detecting a moment at which the output value of the NOR gate 320 transitions ( 340 is configured and implemented.

Hereinafter, the operation of the vertical sync signal detector having the above-described configuration will be described with reference to FIGS. 2 and 3.

First, when a vertical synchronization signal is applied to the N-bit up-down counter 110, the N-bit up-down counter 110 performs an up-count operation when the vertical synchronization signal is at a high level, and when the vertical synchronization signal is at a low level. Performs a down-count operation.

At this time, the period of the clock CLOCK1 for enabling the N-bit up-down counter 110 has a period for dividing an integer number of pulse widths when the vertical synchronization signal is at a high level.

That is, when the high level vertical synchronization signal is applied to the N-bit up-down counter 110, the pulse width during the high level is accurately detected to start an UP count, and the number of times according to the standard of the vertical synchronization signal is increased. When the high level continues, the result N bits output from the N-bit up-down counter 110 are all at the high level.

The change in the output signal value of the N-bit up-down counter 110 according to the logic level of the vertical synchronization signal is shown in FIG. 3.

As shown in FIG. 3, When the N-bit up-down counter 110 starts an up or down count operation or starts an up or down count operation in a state of high or low level, it means that a vertical synchronization signal has been input.

At this time, the N bit output of the N-bit counter 100 becomes a high level in a pulse section in which the vertical synchronization signal is at a high level, that is, a and b sections, or an N bit output of an N bit up-down counter in a section d. In order to prevent all of them from going low, the period of the sampling clock CLOCK1 applied to the N-bit up-down counter 110 must be adjusted, and the number of digits of the counter is detected so that the transition of the vertical synchronization signal can be detected as soon as possible. Determined in combination with N.

When the N bit up-down counter 110 reaches the high level or the low level, the N bit up-down counter 110 stops the count operation until the vertical synchronization signal transitions to the low level or the high level while maintaining the value.

Subsequently, when the outputs of the N-bit up-down counter 110 are all high or low, the output of the AND gate 121 of the state transition detector 120 and the output of the NOA gate 122 are respectively. Since the high and low levels are set, the high-level clock CLOCK is output from the OR gate 130.

In this case, the transition detectors 122 and 125 detect an output signal of the NOR gate 122 and the AND gate 121 when the signal transitions from low to high, and immediately output a high level pulse to thereby output an N-bit up-down counter. Increase the response speed of the detection unit 120 to the output of the input.

Similarly, even when the outputs of the N-bit up-down counter 110 are all at the low level, the clock CLOCK output from the detector 120 is at the high level.

Subsequently, when the high level clock CLOCK is output from the vertical synchronizing signal detector 100, the M bit counter 210 outputs all of the high or all low levels of the N bit up-down counter several times for a predetermined period. Count the number of times you have generated a.

At this time, the count value of the M bit counter 210 is the number of transitions of the input vertical synchronization signal.

Here, when the N-bit up-down counter 110 and the M-bit counter 210 count the vertical synchronization signal, the N-bit up-down counter 110 and the M-bit counter 210 perform a counting operation over a longer period than a prescribed period of the vertical synchronization signal.

That is, when detecting and counting a section in which a vertical synchronization signal having a certain period is at a high level, if the counter, which is a digital circuit, starts counting from the exact time when the vertical synchronization signal starts, the vertical synchronization signal is at a high or low level. Although the interval can be accurately detected at every fixed period, if the count starts later or earlier than the time when the vertical synchronization signal is applied, the accurate count value is not obtained.

As described above, since the period of the vertical synchronization signal is a signal having a minimum margin value and a maximum margin value, it means that the counter constituting the present invention must have a time margin accordingly.

The count value of M bit counter 210 is then stored in register 220 and then compared in comparator 230.

Here, the count value of the M-bit counter 210 is stored in the register 220 in response to the clock CLK1 enabled for each period of the maximum period + operation margin of the vertical synchronization signal, and also the M-bit counter 210. Cleared in response to clock CLK2 enabled at each period of the maximum period + operating margin.

Here, by setting the operation margin value of the M-bit counter 210 to be larger than the register 220, the count value of the M-bit counter 210 can be stored in the register 220 and then compared in the comparator 230. In addition, a time margin must be provided, and a P-bit counter should be allowed to receive a count value from the register 220.

Therefore, the operating margin of the counter, comparator and register constituting the vertical synchronization signal detector of the present invention has the largest operating margin of the M bit counter, and is in the order of the P bit counter, the comparator and the register.

Subsequently, the system compares the previous count value stored in the register 220 with the current count value stored in the M-bit counter 210 in the comparator 230, and generates an interrupt to receive an image signal when the value is not the same. Inform them.

That is, if the value stored in the register 220 and the value stored in the M bit register are the same, the interrupt is not generated, and thus the frequency of interrupt generation is significantly reduced as compared with the conventional vertical sync signal detector.

Subsequently, when the comparison operation between the M bit counter 210 and the register 220 is completed in the comparator 230, the value of the M bit counter 210 is applied to the register 220 and the value stored in the register 220 at this time. Accordingly, after the P bit counter 330 is cleared or an increment operation is performed, the M bit counter 210 is cleared.

Subsequently, when the vertical synchronization signal is not applied to the N-bit up-down counter 110, since the clock clock is not output from the vertical synchronization signal detector 100, the count value output from the M-bit counter 210 is M bits. All are at the low level, and this value is stored in register 220.

Since the value stored in the register is all low level, it means that the vertical synchronization signal has not been input for a certain period of time, so that the P-bit counter 330 is applied to the register 220 during the period of adding the maximum period of the vertical synchronization signal and a certain operating margin. When the stored value is at the low level, an overflow signal (overflow) for recognizing that the vertical synchronizing signal is not applied is output to notify the image signal receiving apparatus including the vertical synchronizing signal detector according to the present invention.

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in the art.

As described above, the present invention generates an interrupt only when the state of the vertical synchronizing signal applied for the detection of the vertical synchronizing signal changes, so that the response speed is faster and the vertical synchronism is higher than that of a detector for detecting the vertical synchronizing signal using software. Interrupt generation is extremely low compared to the vertical sync signal detector that uses the highest priority interrupt when the signal transitions. Therefore, the system waits due to interrupt priority and reduces the signal processing capability and speed of the receiving device receiving the vertical sync signal. Increase.

Claims (6)

delete delete delete A vertical sync signal is input to count up or down according to the logic level of the vertical sync signal. When the vertical sync signal maintains the first or second logic level for a predetermined period, the clock is recognized as part of the vertical sync signal. A vertical sync signal detector; A vertical synchronizing signal change detector for counting a clock output from the vertical synchronizing signal detector for a predetermined period and comparing the same with the number of clock counts in a previous state, and detecting a change in the vertical synchronizing signal; And An overflow detector configured to generate an overflow signal for recognizing that the vertical sync signal is not applied when only a second logic level is output for a predetermined period by the vertical sync signal change detector; The vertical sync signal detector, A vertical synchronizing signal input unit for detecting a logic level of the vertical synchronizing signal to generate an N-bit output signal, and a detection unit for generating a clock by determining whether the vertical synchronizing signal is input by logically combining the output of the vertical synchronizing signal input unit; and, The vertical synchronization signal input unit, Generates N-bit output, with the vertical sync signal as input, up-counts when a signal of the first logic level is applied and down-counts when a signal of the second logic level is applied, but for a period of time the first or second When a logic level signal is applied, the outputs of the N bits are all N-bit up-down counters to be the first logic level or the second logic level, The detection unit, An AND gate outputting a first logic level when the N-bit outputs output from the N-bit up-down counter are all at a first logic level or a second logic level, and the N-bit up-down counter vertical synchronization signal A first NOR gate that outputs a first logic level when the N-bit outputs output from the input unit are all at a second logic level, and an OR gate which receives the outputs of the AND gate, the AND gate, and the first NOA gate as inputs And a first transition detector for detecting a moment at which the output value of the first NOR gate transitions, and a second transition detector for detecting a moment at which the output value of the logical product gate transitions. . The method of claim 4, wherein The vertical synchronization signal change detection unit A first counter for counting a clock output from the vertical sync signal detector, a register for storing a count value of a previous state output from the vertical sync signal detector, an output value of the first counter and the register to compare an interrupt And a comparator for generating a vertical synchronization signal detector. The method of claim 4, wherein Overflow detection unit, The second and third NOR gates which input the number of clock counts of the previous state stored in the vertical synchronization signal change detection unit, and are initialized when the output of the second NOR gate is at a first logic level, and the output of the third NOR gate. And a second counter for generating an overflow signal at the second logic level during the predetermined period, and a third transition state detector for detecting the moment when the output value of the second NOR gate transitions. .