JPH01105698A - Signal input detecting circuit - Google Patents

Abstract

PURPOSE:To remove the influence of a noise and to detect the pulse of the width of a constant length without fail by starting the count of a first clock signal with a count means when an external signal is inputted and executing the reset of the count means with a signal stopping time detecting means in case of the external signal due to the noise. CONSTITUTION:While the external signal is inputted, an output '1' is outputted from OR gates 24-26 to a counter 13 and a first clock signal CLK is counted by the counter 13. When the external signal has the character of the noise of the short width, the external signal is not inputted immediately. Then, it is transmitted that there is no input of the external signal to data flip-flops DFF21-23 by a CLK2 and a Q output successively reset binary flip-flops BFF14-16. Normally, the pulse width of the noise is enough short to the pulse width of a reader pulse. Thus, before the Q output of the counter 16 goes to '1', the counter 13 is reset and the noise pulse is not detected by a detecting means 18.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal input detection circuit for remote control reception using infrared rays, etc., and particularly relates to a signal input detection circuit for detecting league pulses having a constant pulse width. .

[Prior Art] Remote control transceivers using infrared rays have been used in various consumer devices such as audio equipment and video equipment. FIG. 7 shows the configuration of a receiver of such a remote control transmitter/receiver.

That is, this remote control receiver includes an infrared light receiving diode 1,
It is composed of an amplifier 2, a reader pulse detection section 3, and a decoder integrated circuit 4.

An infrared light receiving diode 1 receives an infrared transmission signal obtained by modulating a carrier wave of several tens of kilohertz. The voltage generated by the infrared light receiving diode 1 due to this light reception is several 10
Since it is a weak signal of μV and is modulated as shown in Fig. 8A, the next stage amplifier 2 selectively amplifies the carrier wave, removes the carrier wave, and shapes the waveform to produce the signal as shown in Fig. 8B.
You will get the output as shown. In order to distinguish between original data and noise generated by external light, a leader pulse of about 10 m5 as shown in FIGS. 8A and 8B is added to the remote control signal before the data.

The league pulse detection unit 3 is mainly composed of a CR charging/discharging circuit, and as shown in FIG. When reaching , it is assumed that a league pulse with a width exceeding a certain time T has been input, and a signal (FIG. 8D) indicating this is generated.

The decoder integrated circuit 4 is usually composed of a microcomputer chip, and after receiving a signal indicating that a league pulse has been detected at its L terminal, receives remote control data at its Code terminal and decodes the remote control data.

[Problems to be Solved by the Invention] By the way, the league pulse detection unit 3 detects noise other than the leader pulse, for example, the noisy pulse in the preceding stage of the league pulse in FIG. 8E and the so-called hollow noise in the leader pulse. The time constant is set to the optimum value so that it does not react to For this reason, a resistor of several hundred ohms and a capacitance of several hundredths of a μF are used as external components for this circuit. On the other hand, in recent years, due to the demand for reducing the number of parts and downsizing of devices, peripheral circuits have been incorporated into microcomputers.

However, in the above-mentioned league pulse detection section which externally attaches a resistance of several hundred ohms and a capacitance of several hundredths of a μF,
Integration was difficult, and this was one of the factors that hindered the incorporation of two peripheral circuits.

On the other hand, if the league pulse detection section 3 can be configured with a simple digital circuit, it can be built into an integrated circuit, but in this case, it is not possible to remove noise by CR, and There is a problem in that narrow noise during reception cannot be effectively removed using arbitrary removal characteristics.

The present invention has been made in view of these problems, and can be configured with a simple digital circuit that can be incorporated into a microcomputer, has an excellent noise removal effect, and has an excellent noise removal effect.
It is an object of the present invention to provide a signal input detection circuit whose noise removal characteristics can also be easily adjusted.

[Means for solving the problem] The signal input detection circuit according to the first invention of the present application includes a counting means for counting a first clock signal when an external signal is input, and a counting means for counting a second clock signal. signal stop time detection means for resetting the count value of the counting means when the input of the external signal stops for a time exceeding a predetermined number of clock pulses of the second clock signal; The device is characterized in that it has a detection means for detecting that a predetermined external signal has been input when a predetermined value is reached.

The signal input detection circuit according to the second invention of the present application has an up-down function that up-counts the first clock signal when an external signal is input, and down-counts the second clock signal when the input of the external signal is stopped. a counting means;
The present invention is characterized by comprising a detection means for detecting that a predetermined external signal has been input when the count value of the up/down count means reaches a predetermined value.

[Operation] In the first invention of the present application, when the counting means receives an external signal, it measures the pulse width of the signal.
Start counting the clock signal.

If the external signal is due to noise, its pulse width is very fine, so the input of the external signal stops before the count value of the counting means reaches a predetermined value, and the stop period continues for a long time. Therefore, the signal stop time detection means resets the counting means, so that the input of the predetermined external signal is not detected.

When the external signal is a league pulse, the counting means continues counting up to a constant value without being reset, so that the league pulse is detected by the detection means.

When a signal drop occurs during league pulse input, the signal stop time detection means does not reset the counting means because the signal stop time only occurs for a short time. Therefore, the counting means stops counting. continue. When the count value reaches a predetermined value, the detection means detects the input of the league pulse.

In the second aspect of the present invention, when the external signal is input, the up/down counting means starts counting up the first clock signal.

If the external signal is due to noise, its pulse width is very narrow, so that the input of the external signal is stopped before the count value of the up/down counting means reaches a predetermined positive value. During the period when this external signal is not input, the up/down count means counts down the second clock signal, so the count value does not increase, and therefore the detection means does not detect the input of the external signal.

When the external signal is a league pulse, the up/down counting means continues counting up to a predetermined value without counting down, so that the league pulse is detected by the detection means.

When a gap occurs during input of a leader pulse, the up/down count means performs a down-count operation during the gap period, and the count value decreases. However, since this dropout only occurs for a short time, the count value only decreases slightly, and after the dropout period ends, the up-down counting means restarts up counting, and when the count value reaches a predetermined positive value, The detection means detects the input of the league pulse.

As described above, according to the present invention, it is possible to reliably detect a pulse having a constant width while eliminating the influence of noise.

Note that the noise removal characteristics can be arbitrarily determined without changing the hardware by appropriately changing the clock cycle when the external signal is input and the clock cycle when the external signal input is stopped. Furthermore, since this circuit can be constructed from a simple digital circuit, it can be integrated.

[Examples] Examples of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

In FIG. 1, the AND gate 11 guides the first clock signal CLKI to the counter 13 only while an external signal is input through the external terminal 12.
3 constitutes a counting means. The counter 13 includes, for example, binary flip-flops (BFF) 14, 15, 16 and an inverter 17 connected in cascade in three stages. The output of the AND gate 11 is given to the φ terminal of the BFF 14, and the signal obtained by inverting the output of the AND gate 11 by the inverter 17 is given to the T terminal. The Q and Q outputs of BFF14 are φ and φ of BFF15, respectively.
is applied to the φ terminal, and the Q and Q outputs of BFFl5 are respectively BF
It is given to the φ and T terminals of F16. BFFl6's Q
The output is given as a set input of a reset set flip-flop (RSFF) 18 as a detection means.

The signal stop time detection means converts the external signals connected in cascade in three stages and inputted to the external terminal 12 into a second clock signal CL.
Data flip-flop (DFF) that shifts sequentially with K2
)21.22.23 and each Q of these DFF21-23
The logical sum output of the output and the above external signal is sent to each BFF 14.
3 OR gates 2 output to reset terminal R of ~16
It is composed of 4°25.26.

Note that this circuit is integrated and incorporated into an integrated circuit such as a microcomputer.

Next, the operation of the signal input detection circuit configured as described above will be explained. Two clock signals CLKI, CLK
2 is a signal generated from inside the integrated circuit, and can be arbitrarily set by a stored program.

Timing charts of CLKI and CLK2 are shown in FIGS. 2a and 2b. CLK2 is set to a pulse with a shorter period than CLKI.

When an external signal as shown in FIG. 2C is input to the external terminal 12 from the outside, an external signal detection circuit (not shown) detects this and generates CLKI.

While the external signal is being input, the OR gates 24 to 26
The output “1” is output to the counter 13, and each BFF1
Since the resets of 4 to 16 are released, CLKI is counted by the counter 13.

If the external signal is noisy and has a short width like the first and second pulses in FIG. 2C, the external signal will immediately stop being input.

When the external signal disappears, the fact that the external signal is no longer input is sequentially transmitted to the DFFs 21, 22 and 23 by CLK2 (e, f+g in FIG. 2).

Q output of DFF21, 22.23 is OR gate 24.2
The BFFs 14 and 15° 16 are sequentially reset through 5.26 (h+'+J in Figure 2).

Normally, the pulse width of the noise is sufficiently shorter than the pulse width of the league pulse, so the output of the Q of the counter 16 is “
The 4 counter 13 is reset before reaching 1'', so noisy pulses like the first and second pulses are not detected by the R3FF 18.

If there is a gap in the league pulse, as in the third pulse shown in Figure 2C, the interrupted time and CLK2
The bits of the counter determined by the cycle of are reset. In the example of this figure, only BFFl4 is reset,
At this time, the count value of the counter 13 is "2", and the BF
Since the Q output of Fl4 is "0", the count value is not affected at all and counts four clocks of CLKI.

As a result, the Q output of BFF16 becomes 1'', and the league pulse is detected by R8FF18 without being affected by the hollow noise.

According to this embodiment, a part (lower bit) of the counter 13 can be reset within a range corresponding to the period of omission. In this example, in order to simplify the explanation, the counter 13 is composed of three stages of flip-flops, but it is possible to increase the number of stages and
By adjusting the cycles of CLKI and CLK2, the characteristics of the detection circuit can be adjusted to desired characteristics. In particular, by incorporating this circuit into a microcomputer and controlling CLKI and CLK2 with a program, changes in league pulse length and infrared receiving system can be handled without making any changes to the hardware. This makes it possible to detect league pulses that match.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention. This embodiment differs from the first embodiment in the configuration of the signal stop time detection means.

That is, in this embodiment, the signal stop time detection means is composed of DFFs 31 and 32 connected in two stages and one OR gate 33.
It consists of DFF31゜32 is external terminal 12
The OR gate 33 sequentially shifts the external signals input to the DFFs 31.3 and 31.3 using the second clock signal CLK2.
In step 2, the logical sum output of the external signal delayed by two clocks of CLK2 and the current external signal is output to the counter 13 as a common reset signal for BFFs 14-16.

In this embodiment, when a dropout occurs, the contents of the counter are held for two clocks of CLK2, and if there is a dropout of three or more clocks, all the counters are reset. In this embodiment, there are two ways to maintain the count value or to reset it entirely for the time interval of the interruption, but the circuit is simple.

Next, an embodiment of the first invention of the present application will be specifically described. FIG. 4 is a circuit diagram showing a signal input detection circuit according to an embodiment of the second invention of the present application. 3 person power AND gate 41 has 4
The output of the human OR gate 44 and the second clock CLK2
and the external signal of the external terminal 12 inverted by the inverter 46 are input. The two-man AND gate 42 is supplied with the clock CLKI and an external signal input to the external terminal 12. The outputs of the AND gates 41 and 42 are input to a two-man OR gate 43, and the output of the OR gate 43 is input to a clock terminal CK of a 4-bit up-down counter 40. This AND gate 41, 42 and O
A clock switching circuit 45 is configured by the R gate 43. The clock switching circuit 45 selects one of the clocks CLKI and CLK2 based on the high or low of the external signal input to the external terminal 12 and the output of the OR gate 44, and also uses the selected clock signal as a counter. 4
It switches whether to output to 0 or to stop output to the counter 40.

An external signal input to the external terminal 12 is input to the up/down switching terminal U/D of the 4-bit up/down counter 40. The counter 40 performs an up-count operation on the output of the clock switching circuit 45 inputted to the clock terminal CK when the external terminal 12 is at a high level, and performs a down-count operation when the external terminal 12 is at a low level. In addition, the counter 40
The output Q of each bit of . Q3 to Q3 are input to the AND gate 41 via the OR gate 44, and the most significant bit output Q
s is also input to the set terminal S of R3FF18 that constitutes the detection means.

Note that, like the first invention of the present application, this circuit is integrated and incorporated into an integrated circuit such as a microcomputer.

Next, the operation of the signal input detection circuit configured as described above will be explained.

Now, when a high level external signal is input to the external terminal 12, this external signal becomes low level by the inverter 46 and is input to the AND gate 41, so that the clock C
LK2 is not output to the OR gate 43. On the other hand, when the AND gate 42 to which this high-level external signal is input receives the clock CLKI, the clock CLK
I is output to the OR gate 43, and the OR gate 43 outputs this C.
L K 1 is output to the clock terminal CK of the counter 40.

Since the count value of the counter 40 is 0 and a high level is input to the up/down switching terminal U/D, the output of the clock switching circuit 45 (clock CLKI) is counted up. Then, the output Q3 of the counter 40
becomes high level only when the count value of the counter 40 reaches 8, and sets the set terminal S of R5FF18 to high level.

Then, when the external terminal 12 becomes low level, the AND gate 42 does not allow the clock CLKI to pass.If the count value of the counter 40 is 1 or more in this case,
The AND gate 41 passes the clock CLK2, and the output of the clock switching circuit 45 becomes the clock CLK2.

On the other hand, since a low level is input to the up/down switching terminal U/D of the counter 40, the counter 40 counts down the clock CLK2.

When the count value of the counter 40 reaches 0, this is input to the AND gate 41 via the OR gate 44, and the AND gate 41 blocks the passage of the clock CLK2, so the counter 40 stops the down-counting operation. Also, when the count value that was 8 or more becomes 7 or less, the highest value bit output Q3 of the counter 40 changes from high level to low level, this output is input to R5FF18, and the level of R8FF18 changes from high level to low level. Change in level.

Next, the above operation will be explained using the time chart shown in FIG. Now, when the external signal n (symbol n in the figure) changes from low level to high level, the switching circuit 45 selects the clock CLKI (symbol 1 in the figure) and outputs it to the counter 40. During the period when the external signal is at a high level as shown in FIG. 2n, the counter 40 receives CLK as shown in FIG.
Count up I. Then, when the external signal n changes to low level, the counter 40 changes to the clock switching circuit 4.
5 counts down the selected clock CLK2 (symbol m in the figure). As a result, the count value of the counter 40 changes from 5 to 3, for example.

Next, when the external signal n changes to high level again, the counter 40 performs an up-count operation at the timing of the clock CLKI. When the count value of the counter 40 reaches 8 (the most significant bit is high level), this high level becomes R5.
The signal is input to the FF18, and the output Q (symbol p in the figure) of the R8FF18 becomes high level. As a result, input of the league pulse to the external terminal 12 is detected. and,
When the external signal becomes low level, the counter 40 counts down, so the count value decreases, and R8FF1
The output of 8 becomes low level.

If the pulse width of the external signal is a short pulse such as a noisy pulse, the count value of the counter 40 is 8.
Then, before the output Q3 becomes high level, the counter 40 starts counting down, and eventually R8FF
A high level is not output from the output Q of 18. Therefore, even if a noise pulse is input to the external terminal 12, R3
No detection signal is output from the FF 18.

Furthermore, if there is a gap in the external signal n (league pulse), the count value decreases depending on the period of the gap and the cycle of clock CLK2, but the count value will not count up again, as shown in Figure 5. Started and eventually R8FF
18 outputs a high level (league pulse detection signal). Therefore, even if a dropout occurs, the league pulse can be reliably detected.

Note that in this example, to simplify the explanation, counter 4 is
Although the number of 0 bits is set to 4 bits, this number of bits may be changed as appropriate, or the clock CLKI and/or CL
By adjusting the period of K2, the characteristics of the detection circuit can be adjusted to desired characteristics.

The clocks CLKI and CLK2 do not need to be pulses with a constant cycle, and the cycle may be changed during the detection of the league pulse.The cycles of the clocks CLK1 and CLK2 can be freely set by a stored program, so For example, as shown in FIG. 6, the period of the clock CLK1 is shortened while an external signal is input to the external terminal 12 for a predetermined period of time or more, and the period of the clock CLK1 is shortened during other periods.
lengthen the cycle. After the league pulse is detected, the period of the clock CLK2 is shortened. As a result, as shown in FIG. 6, the speed at which the count value of the counter 40 increases is inversely proportional to the cycle of the clock CLKI, making it difficult for the count value of noise to increase. In addition, the detector R8FF
After high level is output from 18, clock CLK2
The cycle is shortened and the countdown operation is quick.

In this way, changes in the league pulse length, changes in the infrared light receiving system, etc. can be dealt with without making any changes to the hardware, and it is possible to detect league pulses that are suitable for the light receiving section.

[Effects of the Invention] As described above, according to the present invention, external components such as resistors and capacitors are not required, and a simple digital circuit can be used. There are fewer remote control receivers that can be configured. Further, there is an advantage that the noise removal characteristics and the hollowness characteristics can be easily adjusted by adjusting the period of the first clock signal CLK1 and the second clock signal CLK2 or the number of bits of the counting means.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the first invention of the present application, FIGS. 2a to 2 are timing charts of the embodiment, and FIG.
9 is a circuit diagram showing the configuration of the second embodiment of the first invention of the present application, FIG. 4 is a circuit diagram showing a signal detection circuit according to the embodiment of the second invention of the present application, and FIG. Figures A to E are timing charts of the same embodiment, FIG. 7 is a diagram showing the configuration of a remote control receiver, and FIGS. 8A to E are waveform diagrams of various parts of the receiver. 1; Infrared light receiving diode, 2; Amplifier, 3; Reader pulse detection unit, 4; Decoder integrated circuit, 11, AND gate, 12; External terminal, 13; Counter, 14 to 16; Binary flip-flop, 17.46 ;Inverter, 1
8: Reset flip-flop, 21-23.31,3
2; Data flip-flop, 24-26, 33, 43
．． 44, OR gate, 40; 4-bit up-down counter, 41, 42; AND gate, 45; clock switching circuit

Claims (7)

[Claims] (1) A counting means that counts a first clock signal when an external signal is input, and a second clock signal that is introduced so that the input of the external signal exceeds a predetermined number of clock pulses of the second clock signal. Signal stop time detection means for resetting the count value of the counting means when the count value is stopped for a certain amount of time; and detection means for detecting that a predetermined external signal has been input when the count value of the counting means reaches a predetermined value. A signal input detection circuit comprising: (2) The signal input detection circuit according to claim 1, wherein the second clock signal has a shorter period than the first clock signal. (3) The signal stop time detection means includes a multi-stage data flip-flop circuit that delays the external signal by a shift operation using the second clock signal, and a signal between the delayed output of the data flip-flop circuit and the external signal. 2. The signal input detection circuit according to claim 1, further comprising an OR circuit that outputs a logical sum output as a reset signal to the counting means. (4) The signal stop time detection means resets the lower bits of the counting means equal to the number of clock pulses of the second clock signal counted during the input stop time of the external signal. The signal input detection circuit according to claim 1, characterized in that: (5) up-down counting means for up-counting the first clock signal when an external signal is input and down-counting the second clock signal when the input of the external signal is stopped; 1. A signal input detection circuit comprising: detection means for detecting input of a predetermined external signal when a count value reaches a predetermined value. (6) The signal input detection circuit according to claim 5, wherein the first and second clock signals have the same period. (7) The signal input detection circuit according to claim 5, wherein the second clock signal has a shorter period than the first clock signal.