JPH05276057A - Signal input detection circuit - Google Patents

Abstract

PURPOSE:To form the detection circuit with a simple digital circuit to be easily integrated in a microcomputer, to attain excellent noise-elimination effect and to easily adjust the characteristic of noise elimination. CONSTITUTION:A clock changeover circuit 15 selects and inputs one of a 1st clock CLK1 and a 2nd clock CLK2 based on an external signal inputted via an external terminal 12, an output of an inverter 17 and an output of a 3-input OR gate 14 and selects the selected clock signal as to whether or not it is outputted to a 3-bit up-down counter 10. The 3-bit up-down counter 10 counts up an output of a clock changeover circuit 15 when an external signal is at a high level and counts down the output of the clock changeover circuit 15 when the external signal is at a low level. An output of a 2-input AND gate 18 is a detection signal of this signal input detection circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal input detecting circuit, and more particularly to a signal input detecting circuit for detecting a signal having a constant pulse width for a signal input detecting circuit for reception in a remote control device utilizing infrared rays or the like. ..

[0002]

2. Description of the Related Art A conventional signal input detection circuit is shown in FIG.
There is a reader pulse detector 3 used in a conventional remote controller transceiver as shown in FIG. FIG. 3 is a block diagram showing the configuration of a receiver in a conventional remote control transceiver using infrared rays or the like used in audio equipment, video equipment and various consumer equipment. The remote control receiver shown in FIG. 3 is composed of an infrared ray receiving diode 1, an amplifier 2, a reader pulse detector 3 and a decoder integrated circuit 4.

FIG. 4 is a timing chart showing signal waveforms of various parts in the conventional receiver shown in FIG. The infrared ray receiving diode 1 receives infrared rays obtained by modulating a carrier wave of several tens KHz as shown by the waveform A in FIG. 4 and outputs a weak voltage of several tens μV as shown by the waveform A in FIG. An amplifier 2 provided next to the infrared ray receiving diode 1 selectively amplifies the output of the infrared ray receiving diode 1, removes a carrier wave, and shapes the waveform to modify the waveform.
The signal as shown by the waveform B in is output. It should be noted that the remote control signal received by the receiver shown in FIG. 3 has a 10 mS waveform as shown by waveforms A and B in FIG. 4 in order to distinguish the original data signal from noise generated by ambient light.
A degree of leader pulse is added to the first half of the data signal.

The reader pulse detector 3 is mainly composed of a CR charging / discharging circuit. Leader pulse detector 3
Inputs the output of the amplifier 2 to the reader pulse detector 3
When the electric potential of the internal circuit of FIG. 4 increases with time from the rise of the leader pulse and reaches a certain threshold value VTH as shown by the waveform C in FIG. 4, it is judged that a leader pulse having a width exceeding the certain time T is input. Then, the waveform D in FIG. 4, which is a signal indicating this determination, is output.

The decoder integrated circuit 4 usually comprises a microcomputer chip, receives a data signal at the L terminal and then receives a data signal at the Code terminal, and decodes the data signal.

Further, unlike the other example of the receiver in the conventional remote controller transceiver shown in FIG. 5, the signal shown by the waveform B in FIG. 4 is supplied to the Code terminal of the decoder integrated circuit 4 without providing the reader pulse detector. There is also one that detects both the data signal and the reader pulse by inputting and determining the width of the reader pulse by software.

[0007]

However, in the above-mentioned conventional signal input detecting circuit, the reader pulse detecting section 3 is used.
Is set to an optimum time constant so that it does not react to noise other than the leader pulse, for example, a noise pulse in the period before the leader pulse as shown by the waveform E in FIG. 4 and so-called hollow noise in the leader pulse. Therefore, resistance of several 100 KΩ and 0.01 μF to 0.1 μ
An F-level capacitor or the like is required as an external component of this circuit. Recently, in order to reduce the number of parts of the device and to reduce the size of the device, incorporation of peripheral circuits into a microcomputer has been promoted. Therefore, a resistance of several 100 KΩ and a resistance of 0.
The reader pulse detection unit 3 having an external capacitance of 01 μF to 0.1 μF or the like is difficult to integrate, and there is a problem that the incorporation of peripheral circuits is alienated.

On the other hand, if the reader pulse detector 3 can be constructed by a simple digital circuit, the reader pulse detector 3 can be built in the integrated circuit. In this case, noise removal by CR is performed. However, there is a problem in that noise having a short pulse width before or during reception of the reader pulse cannot be effectively removed by an arbitrary removal characteristic.

In the following specific examples, only the reader pulse will be described. Similarly, even if input from the Code terminal in the decoder integrated circuit 4 shown in FIGS. 3 and 5, noise removal in the amplifier 2 is insufficient. If so, it becomes difficult to discriminate data by software. Therefore, the above-described conventional signal input detection circuit has a problem that it is necessary to integrate means for removing noise of the data signal together with the reader pulse.

The present invention has been made in view of the above problems, and a signal input detection circuit for reception in a remote control device using infrared rays or the like is provided by a simple digital circuit which can be incorporated in a microcomputer. An object of the present invention is to provide a signal input detection circuit that can be configured, has an excellent noise removal effect, and can easily adjust the noise removal characteristics.

[0011]

A signal input detection circuit according to the present invention counts up a first clock signal when an external signal is input and outputs a second clock signal when the input of the external signal is stopped. In the signal input detection circuit having up-down count means for down-counting, and detection means for detecting that the count value of the up-down count means has reached a predetermined value, the up-down count means is When the maximum countable value in the up / down counting means is reached, the count value is held for further input of the external signal.

[0012]

In the signal input detection circuit according to the present invention, when an external signal is input, the up / down counting means starts up counting of the first clock signal. When the external signal is due to noise, the pulse width of the external signal due to the noise is very short, so the input of the external signal is stopped before the count value of the up / down counting means reaches a predetermined value. Then, during a period in which no external signal is input, the up / down count means counts down the second clock signal, so that no signal to be detected is input to the detection means. Further, when the down-count is performed and the count value becomes the minimum value, the count-down is not further performed, so that the up-down counting means does not become an abnormal value other than the minimum value and erroneously detected.

In the period in which the external signal is not input, if noise occurs in the pulse in the external signal and a pulse dropout occurs, the up / down counting means counts down during the dropout period and the count value decreases. However, since the pulse dropout period due to the noise is short, the count value only slightly decreases. After the end of the void period, the up / down counting means restarts the up counting, and when the count value reaches a predetermined value, the detecting means,
The signal input detection circuit determines that the signal is detected and outputs the detection signal.

Further, in order to save the counter, the count value becomes the maximum value so that the count value does not overflow and become zero when receiving a pulse of a count value or more in the up / down counting means. Further upcounting is prohibited.

As described above, according to the signal input detection circuit of the present invention, it is possible to eliminate the influence of noise and reliably detect a pulse having a fixed length or a width equal to or longer than a fixed length. Note that the noise removal characteristic can be arbitrarily determined by appropriately changing the clock cycle when the external signal is input and the clock cycle when the external signal is stopped, without changing the hardware. Further, the signal input detection circuit according to the present invention can be configured by a simple digital circuit, and thus can be integrated.

[0016]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a signal input detection circuit according to an embodiment of the present invention. As shown in FIG. 1, the 3-input AND gate 11 has the first input terminal of the second clock C
LK2 is input, the second input terminal is connected to the output terminal of the inverter 16, and the third input terminal is connected to the output terminal of the 3-input OR gate 14. The 3-input AND gate 19 has a first
Input terminal receives the first clock CLK1, and the second input terminal is commonly connected to the external terminal 12, the input terminal of the inverter 16 and the up / down switching terminal U / D ′ of the 3-bit up / down counter 10. The third input terminal is connected to the output terminal of the inverter 17. The two-input OR gate 13 has one input end connected to the output end of the three-input AND gate 11 and the other input end connected to the output end of the two-input AND gate 19. These 3-input AND gates 11,
The 2-input AND gate 19 and the 2-input OR gate 13 are
The clock switching circuit 15 is configured.

Further, the 3-bit up / down counter 10
The clock terminal CK is connected to the output terminal of the 2-input OR gate 13, the output terminal Q0 of each bit is connected to the first input terminal of the 3-input OR gate 14 and the first input terminal of the 3-input AND gate 20, and Output terminal Q1 is a 3-input OR gate 14
To the second input end of the 3-input AND gate 20 and one input end of the 2-input AND gate 18, the output terminal Q2 of each bit is connected to the third input end of the 3-input OR gate 14. And a third input terminal of the 3-input AND gate 20 and the other input terminal of the 2-input AND gate 18, respectively. The output terminal of the 3-input AND gate 20 is the inverter 1
7 is connected to the input terminal.

The signal input detection circuit according to this embodiment shown in FIG. 1 is integrated in an integrated circuit such as a microcomputer.

Next, the operation of the signal input detection circuit according to the present embodiment constructed as described above will be described. The clock switching circuit 15 includes an external signal input via the external terminal 12, the output of the inverter 17, and the 3-input OR gate 14.
Of the first clock CLK1 and the second clock CLK1
One of the clocks CLK2 is selected and input, and it is switched whether the selected clock signal is output to the 3-bit up / down counter 10 or not output.

The 3-bit up / down counter 10 counts up the output of the clock switching circuit 15 input from the clock terminal CK when the external signal input via the external terminal 12 is at a high level, and outputs the signal via the external terminal 12. If the external signal input as a low level is low, the output of the clock switching circuit 15 is down-counted. Three
The output of the 2-input AND gate 18 which receives the outputs of the output terminals Q1 and Q2 of each bit in the bit up / down counter 10 becomes the detection signal of the signal input detection circuit according to the present embodiment. That is, the signal input detection circuit according to this embodiment detects a signal when the count value of the 3-bit up / down counter 10 becomes 6 or more.

Next, in the signal input detection circuit according to this embodiment shown in FIG. 1, the case where there is an input as shown by the waveforms l, m and n in FIG. 2 will be described. FIG. 2 is a timing chart showing signal waveforms of various parts in the signal input detection circuit shown in FIG.

In the 3-bit up / down counter 10, the count value changes sequentially, but the waveform n in FIG.
If there is a void as shown in, the count operation becomes a down count operation. When the count value exceeds 6, a detection signal as shown by the waveform p in FIG. 2 is generated, and it is determined that the necessary signal has been input to the signal input detection circuit. As shown in FIG. 2, the external signal continues to be input even after the count value reaches 8, but the 3-input AND gate 20,
First by the inverter 17 and the 3-input AND gate 19.
Since the clock signal of 1 is prohibited, the count value does not become 8 or more, that is, 0.

The above-mentioned function of preventing the count value from becoming 8 or more is effective especially when the signal width to be judged is larger than the bit length of the counter in order to save hardware.

With these features, the signal input detection circuit according to the present embodiment can be incorporated in a microcomputer because it is composed of a simple digital circuit, has an excellent noise removal effect, and has a noise removal characteristic. Can be easily adjusted.

[0026]

As described above, according to the signal input detection circuit of the present invention, the signal input detection circuit for reception in the remote control device utilizing infrared rays or the like does not require external parts such as resistors and capacitors. Since the signal input detection circuit can be configured by a simple digital circuit without using it, a remote control receiver that can be incorporated in an integrated circuit and has a small number of parts can be configured. In addition, the signal input detection circuit according to the present invention has the first clock CLK1 with respect to the noise removal characteristic and the input signal dropout characteristic.
And, it can be easily adjusted by adjusting the cycle of the second clock CLK2 or the number of bits of the counting means.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a signal input detection circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing signal waveforms of various parts in the signal input detection circuit shown in FIG.

FIG. 3 is a block diagram showing an example of a receiver in a conventional remote controller transceiver.

FIG. 4 is a timing chart showing signal waveforms of various parts in the receiver shown in FIG.

FIG. 5 is a block diagram showing another example of a receiver in a conventional remote controller transceiver.

[Explanation of symbols]

 10; 3-bit up / down counter 11, 19, 20; 3-input AND gate 13; 2-input OR gate 14; 3-input OR gate 15; clock switching circuit 16, 17; inverter 18; 2-input AND gate

Claims (5)

[Claims] 1. Up-down count means for up-counting a first clock signal when an external signal is input and down-counting a second clock signal when the input of the external signal is stopped, and the up-down counting means. In a signal input detection circuit having a detection means for detecting that the count value of the means has reached a predetermined value, the up / down count means has a count value equal to the highest countable value in the up / down count means. A signal input detection circuit, which holds a count value with respect to a further input of the external signal when it reaches. 2. The up / down counting means holds the count value for the subsequent stop of the external signal when the count value reaches the maximum countable value in the up / down counting means. The signal input detection circuit according to claim 1, which is characterized in that. 3. The up-down counting means holds the count value for further input of the external signal when the count value reaches the maximum countable value in the up-down counting means, and the count value 2. The signal input detection circuit according to claim 1, wherein when the count value reaches the minimum countable value in the up / down count means, the count value is held for the subsequent stop of the external signal. 4. The signal input detection circuit according to claim 1, wherein the first clock signal and the second clock signal have the same cycle. 5. The signal input detection circuit according to claim 1, wherein the first clock signal and the second clock signal are the same signal.