JPH04270594A - Signal detection circuit - Google Patents

Abstract

PURPOSE:To reduce the cost and to attain accurate discrimination by discriminating a tone pause time of an input signal digitally. CONSTITUTION:Every time an EST signal 11 being a detection signal of an input signal is changed, a binary counter 1 is reset by an output of a D flip-flop 3 and implements count. When the signal input is consecutive till the result of count of the binary counter 1 overflows, an inverse of Q output of the D flip-flop 5 goes to a low level and the excess of the input signal over a discrimination time is informed externally by an inverse of IRQ signal 13.

Description

Detailed Description of the Invention [0001] [Industrial Application Field] The present invention relates to a dual tone multi-frequency
The present invention relates to a signal detection circuit for detecting a signal (equiency) signal, etc., and particularly to a signal detection circuit that digitally determines the signal period length and non-signal period length of an input signal. [0002] In recent years, with the development of advanced information communication networks such as ISDN, various data have come to be exchanged through telephone lines. The telephone selection signal (telephone number signal), which used to be the mainstream dial pulse signal system, has recently become dominated by the tone signal system (so-called touchtone signal), and the dual tone multi-frequency ( Below, “DTM
The signal (referred to as "F") has been used not only as a telephone number but also as an instruction signal for home automation using a telephone, for example. Against this background, there is a need to make signal detection circuits such as DTMF signals compact and highly reliable.Recently, semiconductors have been used to make signal detection circuits on a single chip. Increasingly, devices are constructed using integrated circuits. [0003] Here, the DTMF signal is a signal that simultaneously outputs two different frequencies on the row side (low group frequency side) and column side (high group frequency side) to a telephone line, etc., as shown in Table 1. Then, depending on the combination of the two types of frequencies, specify the alphanumeric characters "0" to "9", "A", "B", "C", "D" and the symbols "#" and "*". This signal is used as a telephone number signal for telephones. Usually, as shown in Table 1, four types of predetermined frequencies are used on each of the row side and column side. [0004] [Table 1] [0005] For example, a DTMF receiver that receives and detects this DTMF signal separates and detects the input DTMF signal on the row side and column side, and then detects the input DTMF signal on the row side and the column side, respectively, as shown in Table 1. Based on the frequencies detected on the side and column sides, a symbol corresponding to the frequency is output as a notification to the outside, for example, in the form of a 4-bit code. This DTMF
In order to prevent malfunctions due to received signal dropouts, etc., the receiver must check whether the duration of a tone signal, which is a received frequency signal, and the duration of a pause in which the frequency signal is in a no-signal state have reached a specified time, respectively. A circuit is provided to determine whether or not. Below, as an example of a conventional signal detection circuit,
The tone and pause time determination of the DTMF receiver shown in FIG. 3 will be explained with reference to the timing chart of FIG. 4. In FIG. 3, when no DTMF signal is input, both the ST terminal 17 and the EST terminal 18 are at a low level. The EST terminal 18 is connected to the ST terminal 17 via an external resistor 22, and the ST terminal 17 is
Since it is connected to the power supply VDD via the external capacitor 21, the external capacitor 21 is in a charged state. At this time, the "IRQ" terminal 19 is at a high level. (For convenience of explanation, logical negation is indicated by "'" instead of an overline.)
and ``''. For example, "IRQ"
The logical negation of is written as "IRQ". (However, in the figure, logical negation is indicated by an overline following the usual example.)) Next, the input terminal 20 is connected to the DTMF receiver 15.
The input DTMF signal is separated into a high group frequency signal on the column side and a low group frequency signal on the row side by two band pass filters (BPF) 23 and 24 with different frequency bands, and then processed using a digital counting method, etc. The presence or absence of each frequency signal is detected by a high group frequency detection circuit 25 and a low group frequency detection circuit 26 using the following. EST only when frequency signals are detected continuously in both high and low groups.
The generation circuit 27 sets the EST terminal 18 to a high level with a delay of time t1 from the input of the DTMF signal. At this time, when the DTMF signal is input continuously and the EST terminal 18 becomes high level, the charge stored in the external capacitor 21 is discharged, so the potential of the ST terminal 17 changes as shown in the T1 section of FIG. It gradually rises to . and,
When the DTMF signal continues to be input for a certain period of time t2, the potential of the ST terminal 17 reaches the threshold potential VTST.
reach. This is the tone/pause time determination circuit 16.
The ``IRQ'' terminal 19 becomes low level to notify the outside that the DTMF signal has been received for more than a specified time. After a certain period of time after the "IRQ" terminal 19 becomes low level, it returns to high level by the tone/pause time determination circuit 16. Furthermore, the ST terminal 17 receives the output from the tone/pause time determination circuit 16.
The "IRQ" terminal 19 becomes low level and simultaneously becomes high level (VDD level). [0008] Next, if the DTMF signal is interrupted due to dropout after the specified time has been determined, as shown in FIG.
As shown in the T2 section of , the potential of the EST terminal 18 is at a low level, but the potential of the ST terminal 17 is at the external capacitor 21.
Since charging requires time, if the DTMF signal is input again before the potential of the ST terminal 17 reaches VTST, the valid signal reception state of the previous DTMF signal is maintained, and the "IRQ" terminal 19 is The potential remains at a high level. Then, when the DTMF input signal stops, T4 in FIG.
As shown in the section, the EST terminal 18 changes from input stop to t3.
becomes low level with a delay of . At the same time, charging of the external capacitor 21 is started, and after a certain period of time t4, the potential of the ST terminal 17 reaches VTST, the tone/pause time determination circuit 16 recognizes the effective pause length, and the ST terminal 17 reaches VTST.
The potential of the T terminal 17 is set to low level. Once the tone/pause time determination circuit 16 recognizes a valid pause, the DTMF signal is input and the potential of the ST terminal 17 becomes VTS.
As long as it does not reach T, D through the IRQ terminal 19
The reception of the TMF signal is not notified to the outside. The tone effective time length TREC and pause effective time length TID in this case are expressed by the following equations 1 and 2. [Equation 1] TREC = t1 + t2 [Equation 2] TID = t3 + t4 In these Equations 1 and 2, t1 is the time required for detection after inputting the DTMF signal, and t3 is the time required for detecting the DTMF signal. This is the time required for detection after the signal has stopped, and each is approximately constant. t2 and t4 are calculated using the following formula 3 and formula using the resistance value R of the external resistor 22 and the capacitance value C of the external capacitor 21. 4, indicating that it changes depending on R and C. [Equation 3] t2 = R・Cln(VDD/(VDD−VTST)
) [Equation 4] t4 = R·Cln(VDD/VTST) (In the above Equations 3 and 4, lnX represents the natural logarithm of X.) [Problems to be Solved by the Invention] ] In the conventional signal detection circuit described above, in order to determine the time of the received tone and pause, a capacitor or resistor is connected outside the signal detection circuit and the charging/discharging time of these is used. When a detection circuit is constructed using an integrated circuit, external terminals and externally connected resistances and capacitors are required. For this reason, the conventional signal detection circuit has the drawbacks that the number of terminals increases and the cost of external components increases. In addition, in this case, the judgment time is determined using the external resistance value and external capacitance value, and because it is determined using a so-called analog judgment method, there may be variations in the external resistance and external capacitance during manufacturing. , and the usage environment of the signal detection circuit, such as changes in resistance value and capacitance value due to the influence of temperature, etc., which have the disadvantage that the determination time fluctuates. [0014] The present invention has been made in view of the above problems, and has the object of eliminating the need for external resistors and external capacitors, reducing the number of terminals, making it easy to integrate circuits, and achieving high precision. It is an object of the present invention to provide a signal detection circuit which is capable of performing a signal detection circuit and whose determination time does not change due to the influence of manufacturing variations or the influence of the usage environment even when integrated. Means for Solving the Problems The signal detection circuit according to the present invention is a signal detection circuit for detecting a frequency signal, in which the presence of the frequency signal is detected and the presence of the frequency signal is no longer detected, respectively. means for generating a detection signal whose value is inverted; means for generating a pulse signal each time the logical value of the detection signal is inverted; means for generating a reset signal each time the pulse signal is generated; and the reset signal. a binary counter that is reset by a clock signal and counts a clock signal input from the outside; means for holding a count-up signal of the binary counter each time the detection signal indicates the presence of a frequency signal; a logic gate that takes an AND of a count-up signal and a signal held by the count-up signal; and a logic gate that changes an output every time the output of the logic gate changes,
The apparatus is characterized by comprising means for notifying an external party that the frequency signal has been detected. [Operation] The signal detection circuit of the present invention uses a binary counter that digitally counts clocks to determine the tone time length and pause time length of the DTMF input signal. Even when configured with an integrated circuit, external resistors and external capacitors are not required, and the number of terminals can be reduced. In addition, the determination times for the tone time length and pause time length are determined by the frequency of the input clock signal of the binary counter and the number of stages of the binary counter, so they can be set with high precision, and are not affected by manufacturing variations. The determination time does not change due to the influence of the usage environment. Embodiments Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 shows the configuration of a tone/pause time determination circuit for a DTMF receiver constructed using a signal detection circuit according to an embodiment of the present invention. The determination circuit in FIG. 1 is similar to the tone/pause time determination circuit 16 and external capacitor 21 shown in FIG.
and is used in place of the external resistor 22 part. The determination circuit in FIG. 1 includes a binary counter 1,
D-flip-flops 2 to 5, AND gates 6, 10,
It has NOR gates 7 and 9 and an OR gate 8. Binary counter 1 counts tones and pause time lengths. However, at this time, the clock input CK of the binary counter 1 is connected to the clock signal 12 and the binary counter 1.
It is connected to the output of an OR gate 8 to which the count-up signal output from the CRY terminal of is input. D-flip-flop 2 receives the EST signal 11 as data input D
is input, and a clock signal 12 is input as clock input CK. AND gate 6 receives EST signal 1
1 and the "Q" output of D-flip-flop 2 are input, and every time the EST signal rises, a pulse (hereinafter "EST↑
signal). NOR gate 7 is ES
The T signal 11 and the "Q" output of the D-flip-flop 2 are input, and a pulse (hereinafter referred to as "
EST↓ signal). NOR gate 9
An EST↑ signal, which is a rising signal of the EST signal, and an EST↓ signal, which is a falling signal of the EST signal, are input to the EST signal. The D-flip-flop 3 receives the output signal of the NOR gate 9 as the data input D and the clock signal 12 as the clock signal CK, and provides its Q output to the reset input "R" of the binary counter 1. Further, the D-flip-flop 4 receives the output of the AND gate 6, which is a rising signal of the EST signal, as a clock input CK, and receives the count-up signal of the binary counter 1 as a data input D.
Output a signal. The 3-input AND gate 10 has EST
Signal 11, count up signal of binary counter 1,
A Q1 signal, which is the Q output of the D-flip-flop 4, is input. The D-flip-flop 5 is resettable and has a three-input AND gate 10 as a clock input CK.
output signal is input, and VDD is input as data input D.
When the level is input, the “Q” output is the “IRQ” signal 13
Output to the outside as . In addition, D-flip-flop 5
The reset input "R" is inputted from the outside as the "IRQ" reset signal 14. Note that, in FIG. 1, the DTMF signal detection section is not shown for the sake of simplification of explanation. Next, the operation of the circuit of this embodiment will be explained with reference to the timing chart shown in FIG. In the initial state, it is assumed that the D-flip-flop 5 is reset by the "IRQ" reset signal 14, and the "Q" output is at a high level. When no DTMF signal is input to the DTMF receiver, the EST signal 11 is at a low level, so the output of the AND gate 10 is at a low level.
Since the clock input CK of the D-flip-flop 5 remains at a low level, the output of the D-flip-flop 5 does not change, and the "IRQ" signal 13 remains at a high level. Further, the count up signal from the CRY terminal of the binary counter 1 is at a high level indicating a count overflow. Next, when a DTMF signal is input to this DTMF receiver, the DTMF signal is detected separately on the row side and the column side, and valid frequencies are detected on both the row side and the column side, respectively. Then, with a delay of ta1 from the input of the DTMF signal, the EST signal 11 changes from low level to high level. When the EST signal 11 changes to a high level, the D-flip-flop 2 and the AND gate 6 generate a rising pulse of the EST signal, ie, an EST↑ signal, as shown in the T1 section of FIG. EST
↑When the signal is generated, the output of the NOR gate 9 becomes low level, so a low level pulse is input to the reset input "R" of the binary counter 1 via the D-flip-flop 3, and the binary counter 1 reset,
At the same time, start counting. At this time, the D-flip-flop 4 holds the CRY output of the binary counter 1 at a high level at the rising edge of the EST↑ signal, so the Q1 signal becomes high level. The binary counter 1 counts up every time the clock signal 12 changes, and when it overflows after counting by a preset number, a high level is output to the CRY terminal. In this case, the time ta2 from when the binary counter 1 is reset until a high level is output to the CRY terminal is determined by the input clock frequency of the binary counter and the number of stages of the binary counter. For example, if the input clock frequency is 16.384kHz If the number of stages of the binary counter is 8, ta2 = 1/16.384
kHz×28 = 15.625ms. [0024] When the CRY terminal becomes high level, EST
signal, Q1 Since the signal is already at high level, A
The output of the ND gate 10 changes from low level to high level, the "Q" output of the D-flip-flop 5 changes from high level to low level, and the DTMF signal is input for more than a specified time via the "IRQ" signal 13. The system is designed to notify the outside world of what has happened. Thereafter, the D-flip-flop 5 is reset by the "IRQ" reset signal 14, and the "IRQ" signal 13 is kept at a high level. The tone effective time length TREC at this time is TREC =
It becomes ta1+ta2. Next, when a DTMF signal that is shorter than the specified time is input, as shown in the T5 section of FIG.
After the DTMF signal is input, the EST signal changes from low level to high level, and at the same time, the binary counter 1 is reset and starts counting. However, D.T.
Since the MF signal stops inputting before binary counter 1 overflows,
The RY terminal remains at low level, and the AND gate 10
maintains a low level, so the D-flip-flop 5
The clock input CK does not change, and as a result, the "IRQ" signal remains at high level. Next, determination of pause time will be explained. When the continuously input DTMF signal stops, the EST signal 11 changes as shown in section T4 in FIG.
changes from high level to low level with a delay of tb1 from the stop of DTMF signal input. At the same time, the EST↓ signal is generated by the D-flip-flop 2 and the NOR gate 7, and the output of the NOR gate 9 becomes low level, so a reset signal is input to the binary counter 1 via the D-flip-flop 3. The binary counter 1 starts counting at the same time as it is reset. The binary counter 1 sequentially up-counts the clock signal 12 by a preset count, and when it overflows, a high level is output to the CRY terminal. In this case, the time tb2 from when the binary counter 1 is reset until a high level is output to the CRY terminal is the same as the time ta2. If the CRY terminal of the binary counter 1 outputs a high level, the pause time is valid, and at this time, the valid pause time length TID is TID=tb1+tb2. At this time, as shown in the T5 or T7 section of FIG. 2, the next DTMF signal is input and the EST signal 1
1 changes from low level to high level and the EST↑ signal is generated, the D-flip-flop 4 receives the EST↑ signal.
The high level is held at the same time as the signal rises. Therefore, when the DTMF signal is input beyond the specified time (ta1+ta2) as in the T7 interval and the CRY terminal of the binary counter 1 becomes high level, the "IRQ" signal 13 of the D-flip-flop 5 becomes low level,
The input of the DTMF signal will be notified to the outside again. Finally, if the pause time is less than the specified time, the EST signal 11 changes from high level to low level at the same time as the input of the DTMF signal stops, as shown in the T2 period of FIG. An EST↓ signal is generated by the D-flip-flop 2 and the NOR gate 7, and a reset signal is input to the binary counter 1 through the NOR gate 9 and the D-flip-flop 3. Therefore, binary counter 1 is reset and starts counting anew, but if the pause time is shorter than time tb2, the CRY terminal of binary counter 1 remains at low level, so As shown, when the next DTMF signal is input and the EST signal 11 changes from low level to high level and the EST↑ signal is generated, the D-flip-flop 4 receives a low level signal at the same time as the EST↑ signal rises. will be retained. Therefore, even if the DTMF signal is input beyond the specified time (ta1+ta2) and the CRY terminal of the binary counter 1 becomes high level, the output of the AND gate 10 remains low level, so the D-flip-flop 5 The output does not change, and the "IRQ" signal 13 remains at a high level, meaning that the pause in the T2 period in FIG. 2 is determined to be invalid. Although the present embodiment has been described with respect to a DTMF receiver, it is clear that the present invention can be applied to other signal detection circuits in substantially the same manner. As mentioned above, in the signal detection circuit, D
Because a binary counter that counts digitally is used to determine the tone time length and pause time length of the TMF input signal, this method is not required in the past even when the signal detection circuit is configured with an integrated circuit. This eliminates the need for external resistors and external capacitors, and reduces the number of terminals, making it extremely easy to configure a single chip including this judgment circuit.As a result, the signal detection circuit and external components This has the effect of reducing the cost. In addition, since the determination time of tone time length and pause time length is determined by the frequency of the input clock signal of the binary counter and the number of stages of the binary counter, it can be set with high precision.For example, the signal detection circuit can be integrated into an integrated circuit. Even with this configuration, the determination time does not change due to the influence of manufacturing variations or the influence of the usage environment. [0033] As described above, according to the present invention, external resistors and external capacitors are not required, the number of terminals can be reduced, and integrated circuits can be easily integrated and high precision can be achieved. Moreover, it is possible to provide a signal detection circuit whose determination time does not change due to the influence of manufacturing variations or the influence of the usage environment even when it is integrated into an integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a tone/pause time determination circuit of a DTMF receiver configured using a signal detection circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart diagram for explaining the operation of the circuit in FIG. 1;

FIG. 3 is a block diagram showing the configuration of an example of a conventional DTMF receiver.

FIG. 4 is a timing chart diagram for explaining the operation of the circuit in FIG. 3;

[Explanation of symbols]

1; Binary counter 2-5; D-flip-flop 6,10;AND gate 7,9;NOR gate 8;OR gate 11, 12, 14; Input terminal 13; Output terminal

Claims (1)

[Claims] 1. A signal detection circuit for detecting a frequency signal, comprising: means for generating a detection signal whose logical value is inverted when the presence of the frequency signal is detected and when the presence of the frequency signal is no longer detected; means for generating a pulse signal each time a logical value is inverted; means for generating a reset signal each time the pulse signal is generated; and a binary counter that is reset by the reset signal and counts a clock signal input from the outside. , means for holding a count-up signal of the binary counter each time the detection signal indicates the presence of a frequency signal, and logic between the detection signal, the count-up signal of the binary counter, and the held signal of the count-up signal. 1. A signal detection circuit comprising: a logic gate that takes a product; and means for changing an output every time the output of the logic gate changes to notify the outside that the frequency signal has been detected.