JPH04243353A - Sequencer device - Google Patents

Abstract

PURPOSE:To fine-adjust a time constant with the software and also to prevent erroneous detection of a CI signal or the like. CONSTITUTION:This device is provided with a sequencer circuit 7 controlling two input signals with a different waveform to decide its output, and also provided with a time constant register 9 setting its time constant in response to the input signal and a counter circuit 8 controlled by a start and a stop signal from the sequencer circuit 7 and counting a prescribed period depending on the time constant written in the register 9. Thus, the sequencer circuit 7 is controlled by a count output of the counter circuit 8 to prevent erroneous detection of two input signals.

Description

[Detailed description of the invention]

0001

FIELD OF INDUSTRIAL APPLICATION The present invention relates to a sequencer device that controls two input signals with different time constants in order to avoid falsely detecting a CI (calling) signal when dialing an external telephone, for example, and particularly relates to a sequencer device that controls two input signals with different waveforms. This invention relates to a circuit for preventing erroneous detection of signals.

0002

2. Description of the Related Art FIG. 7 is a circuit diagram showing an example of a conventional sequencer device for preventing false detection of two input signals having different time constants.
A case is shown in which erroneous detection of I signals is prevented. In the same figure,
1 is a CI input signal, 2 is a DLO input signal, 3 is a CI output signal, 4 is a DLO output signal, 30 is a 2-input OR circuit, 31 and 32 are diodes, 33 and 34 are resistors, 35
, 36 are capacitors. Further, 37 is a two-input OR circuit, 38 is an inverter, and 39 is an SR flip-flop.

Next, in order to explain the operation of FIG. 7, it will be explained using FIGS. 8 and 9, which show waveforms of input and output signals of each part in the same figure. Figure 8 shows when dialing from an external telephone, Figure 9
7 shows the signal waveforms of each part in FIG. 7 when the CI signal is detected. Here, when dialing from an external phone,
The DLO signal becomes low level (hereinafter abbreviated as "L") to indicate that the line is not in an idle state. Furthermore, the time when a CI signal is detected is when the main body and the external telephone are on-hook and a calling signal is received.

The circuit shown in FIG. 7 detects CI signal 1 when the main unit and the external telephone are on-hook (DLO signal 2 is at a high level (hereinafter abbreviated as "H")), and when dialing by the external telephone, An operation is performed to detect that the DLO signal 2 is "L" (the dial waveform appears in the DLO signal 2 midway, but is ignored). That is, when dialing by an external telephone in FIG. 8, the DLO input signal 2 is as shown in the figure (
The “L” waveform shown in a) and the CI input signal 1 are shown in (e) of the same figure.
The waveform becomes "H" as shown in FIG. If it is output as is, the dial from the external telephone will be erroneously detected as a CI signal, so two integrating circuits 41 consisting of diodes 31 and 32, resistors 33 and 34, and capacitors 35 and 36 are used.
, 42 are used to blunt the waveforms, and the outputs I and II are made into waveforms as shown in FIGS. 8(b) and 8(c). this,
SR through 2-input OR circuit 37 and inverter 38
In addition to the flip-flop 39, the flip-flop is reset to output a DLO output signal 4 having a waveform shown in FIG. 8(f). Also, through the two-input OR circuit 30,
As shown in the waveform g), a CI output signal 3 of "H" is output without the influence of the dial signal from the external telephone.

Next, in FIG. 9, when the CI signal is detected, the DLO
The input signal 2 has the waveform shown in FIG. 12(a), and the CI input signal 1 has the waveform shown in FIG. 12(e). If this continues, the DLO signal 2 will be erroneously detected due to the influence of the CI signal 1, so as in the case of FIG. Input OR
Set the flip-flop in addition to the SR flip-flop 39 through the circuit 37 and the inverter 38;
DLO output signals 4 and 2 as shown in the waveform of FIG. 9(f)
C like the waveform of FIG. 9(g) through the input OR circuit 30.
Output I output signal 3

[0006]

[Problem to be Solved by the Invention] As described above, in conventional sequencer devices, the waveform is blunted by analog circuits such as resistors and capacitors to prevent false detection of two input signals with different time constants. Therefore, when making fine adjustments, the time constant of CR must be changed, which poses a problem in that it is necessary to change the hardware. The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a sequencer device in which the time constant can be finely adjusted by software, and in which erroneous detection of CI signals and the like can be prevented.

[0007]

[Means for Solving the Problems] A sequencer device according to the present invention includes a sequencer circuit that includes an AND circuit, an OR circuit, a flip-flop, etc., and controls two input signals having different waveforms to determine their output; A time constant setting register that sets the time constant according to a signal, and a counter circuit that is controlled by the start and stop signals sent from the sequencer circuit and counts a predetermined period according to the value of the time constant written in the register. The count output of this counter circuit is sent to the sequencer circuit to prevent erroneous detection of the two input signals based on the output.

[0008]

[Operation] In the present invention, the parts that were conventionally processed by analog circuits such as resistors and capacitors are now configured with digital circuits such as AND circuits, OR circuits, and flip-flops. You can make fine adjustments by changing the value written to . Therefore, the time constant can be easily changed, and erroneous detection of CI signals and the like can be prevented.

[0009]

Embodiments Hereinafter, embodiments of the present invention will be explained with reference to the drawings. FIG. 1 is a schematic block diagram showing one embodiment of a sequencer device according to the present invention, and FIG. 2 is a circuit configuration diagram showing a specific example of FIG. 1. In FIG. 1, 1 to 4 are exactly the same as the conventional example, 5 is an inverter, 6 is a two-input NAND circuit, 7 is a sequencer circuit, 8 is a counter circuit, and 9 is a time constant setting register. In addition, in FIG. 2, 1 to 6 are the same as in FIG.
The first clock is for latching the bit data (0...7) DA into the time constant setting register 9, φB is the second basic clock for the counter circuit 8 and the sequencer circuit 7, and RT is the reset signal. . 14 to 16 are inverters, 17 is a flip-flop circuit consisting of a 4-bit flip-flop (FF) constituting the time constant setting register 9, 18 and 19 are D-type flip-flops, 20 is a 3-input NAND circuit, and 21 and 22 are 2 input NAND circuit, 2
3 is a 3-input OR circuit. 24 and 25 are two input AND
26 is a two-input NOR circuit, and 28 and 29 are HCs 161 constituting the counter circuit 8.

That is, the DLO input signal 2 is sent through the inverter 14 to the D input of the flip-flop 18, and is also sent through the NAND circuits 20 and 22 to the D input of the flip-flop 19. The Q output of the flip-flop 18 is the NAND circuit 20 and the OR
It is sent to the circuit 23 and the AND circuit 25, and its inverted Q
The output is input to an AND circuit 24. The Q output of the flip-flop 19 is connected to the NAND circuit 21 and the AND circuit 25.
The inverted Q output thereof is taken out as the DLO output signal 4 and is input to the AND circuit 24 and the NAND circuit 6. Furthermore, the output signal (1) of the NOR circuit 26 into which the outputs of the AND circuits 24 and 25 are input is applied to each HC 161 (28), (
29) to the load (L) input of its CO output (
2) is sent to the OR circuit 23 through the NAND circuit 20 and inverter 15 of the sequencer circuit 7. Note that the CI input signal 1 is sent to the NAND circuit 6 through the inverter 5, and its output is taken out as the CI output signal 3.

Next, the operation of the configuration of the above embodiment will be explained with reference to FIG. FIG. 3 shows the changes in the input/output signal waveforms in each part of FIG. 1, and it is assumed that the CI input signal 1 and the DLO input signal 2 change as shown in the waveforms of FIGS. 3(a) and (b). . Here, these CI input signals 1
For the DLO input signal 2, the first half of the waveform shown in FIGS. 3(a) and 3(b) is assumed to be used when dialing from an external telephone, and the second half is assumed to be used when a CI signal is detected. First, reset the reset signal RT to “
"L" (FIG. 3(c)), and the sequencer circuit 7, counter circuit 8, and register 9 are brought to their initial states. Then, in the initial state, each flip-flop 18 of the sequencer circuit 7
, 19 are reset, and the waveform of the DLO output signal 4 shown in FIG. 3(g) and the waveform of the CI output signal 3 shown in FIG. 3(h) are both "H". Next, when dialing with an external telephone, when the DLO input signal 2 changes from "H" to "L", the sequencer circuit 7 operates and its flip-flop 18 latches at the rising edge of the clock φB shown in FIG. 3(d). In order to operate the counter circuit 8 at the same time, N
The output ■ of the OR circuit 26 is set to "L" as shown in FIG. 3(e). At this time, the time constant of register 9 is 2 of clock φB.
Assume that it is set to pulse minutes.

Next, in the counter circuit 8, the clock φB
After counting two pulses of , the CO output is shown in Figure 3 (f
) returns the pulse to the sequencer circuit 7. Then, the sequencer circuit 7 receives the pulse, and the flip-flop 19 is set at the rising edge of the clock φB, and the DLO output signal 4 becomes "L" as shown in the waveform of FIG. 3(g). In addition, in order to terminate the operation of the counter circuit 8, the NOR
The signal is set to "H" through the circuit 26 as shown in FIG. 3(e).

At this time, since the time constant of the register 9 is set to two clock pulses in the 4-bit flip-flop circuit 17, the DLO input signal 2 changes from "L" to "L" as shown in FIG. 3(b). The flip-flop 18 latches the data at the rising edge of the clock φB. As a result, after the load of HC161 (28), (29) of the counter circuit 8 is set to "L" through the AND circuits 24 and 25 and the NOR circuit 26, the load remains "L" until two falling pulses of the clock φB arrive. If so, output the carrier. Then, at the next rising edge of the clock φB, the flip-flop 19 latches the data, and the DLO output 4 changes from “L” to “H”.
”, but before the second pulse of clock φB arrives, D again
When the LO input signal 2 changes from "H" to "L", the load on the HCs 161 (28) and (29) is set to "H" through the same path as above, and the counter circuit 8 is reset.

That is, the DLO input signal 2 is as shown in FIG. 3(b).
Even if a pulse is input in the middle as shown in the waveform of , the DLO output signal 4 does not include a pulse in the middle as shown in FIG. 3(g), and the output waveform changes only when the input waveform becomes two or more pulses. For the waveforms at other points, the DLO input waveform is “H”
→ It moves in the same way as when it is turned on. Also, CI
When the DLO output waveform 4 is "L", the output waveform 3 remains "H" no matter what waveform is input. Conversely, when the waveform is in the latter half, the DLO output waveform 4 does not become "L" and the CI input waveform 1 is output as is as the CI output waveform 3.

FIG. 4 is a schematic block diagram corresponding to FIG. 1 showing another embodiment of the present invention, and FIG. 5 is a specific circuit diagram of FIG. 4. This embodiment differs from the one in FIG. 1 by using an ON time constant setting register 11 and an OFF time constant setting register 12 instead of the time constant setting register 9, and setting the By inputting the time constant to the counter circuit 8 through the selector 13, erroneous detection of the CI signal due to the dialing of an external telephone is prevented as in the above embodiment.

In this case, the ON time constant setting register 11 and the OFF time constant setting register 12 are composed of an 8-bit flip-flop 17, with the upper 4 bits being the ON time constant setting register 11 and the lower 4 bits being the OFF time constant setting register 12. It is used as In addition, the selector 13 is, for example, HC
158 is used, and the Q output of the flip-flop 19 in the sequencer circuit 7 is sent to its S input as a selection signal (3). Here, the on-time constant set in the on-time constant setting register 11 is the time from when the input signal changes from "H" to "L" until the output changes from "H" to "L".
The off time constant set in the off time constant setting register 12 is:
After the input signal changes from “L” to “H”, the output changes from “L” to
This is the time it takes to reach "H". Note that the same reference numerals in the figures indicate the same or corresponding parts.

Next, the operation will be explained using FIG. 6. FIG. 6 shows changes in the input/output signal waveforms of each part in FIGS. 4 and 5, and CI input signal 1 and DLO input signal 2 change as shown in FIGS. 6(a) and (b). shall be. Here, for these CI input signal 1 and DLO input signal 2, it is assumed that the first half of the waveform shown in FIGS. 6(a) and (b) is when dialing by an external telephone, and the second half is when CI signal is detected.

First, set the reset signal RT to "L" (
In FIG. 6(c)), the sequencer circuit 7, counter circuit 8, and registers 11 and 12 are set to the initial state. Then, in the initial state, each flip-flop 18, 1 of the sequencer circuit 7
9 is reset, and the DLO output signal 4 shown in FIG. 6(h)
and the waveform of the CI output signal 3 shown in FIG. 6(i) are both "H". Next, when dialing with an external telephone, when the DLO input signal 2 changes from "H" to "L", the sequencer circuit 7 operates and its flip-flop 18 latches at the rising edge of the clock φB shown in FIG. 6(d). In order to operate the counter circuit 8 at the same time, the output (1) of the OR circuit 26 becomes "L" as shown in FIG. 6(f). At this time, it is assumed that the on-time constant of the register 11 is set to two pulses of the clock φB. In the initial state, the selection signal (3) of the selector 13 is "L" from the flip-flop 19 in the sequencer circuit 7 as shown in FIG. 6(e),
The ON time constant side is selected.

As a result, after the counter circuit 8 counts two pulses of the clock φB, the pulse is returned to the sequencer circuit 7 as the CO output as shown in FIG. 6(g). Then, the sequencer circuit 7 receives the pulse, and the flip-flop 19 is set at the rising edge of the clock φB.
The LO output signal 4 is set to "L" as shown in the waveform of FIG. 6(h). Also, in order to terminate the operation of the counter circuit 8,
6(h) through the NOR circuit 26, and the selector 13 switches from the ON time constant register 11 to the OFF time constant register 12 side, so the waveform becomes "L" → as shown in FIG. 6(e). It becomes "H".

If the off time constant of the register 12 is set to two pulses of the clock φB, then DL
Even if the O input signal 2 has a pulse as shown in the waveform of FIG. 6(b), the DLO output signal 4 will be as shown in FIG. 6(h).
There are no intermediate pulses, and the output waveform changes only when the input waveform becomes two or more pulses. The waveforms at other points also move in the same way as when it is on. Further, when the DLO output waveform 4 is "L", the CI output waveform 3 remains "H" no matter what waveform is input. Conversely, when the waveform is in the latter half, the DLO output waveform 4 does not become "L" and the CI input waveform 1 is output as is as the CI output waveform 3. As described above, according to this embodiment, as in the embodiment of FIG.
Further, the selector 13 can switch the on time constant and the off time constant.

Although the above embodiment shows the case where the influence of the DLO signal and the CI signal is removed, the same effect can be expected even with two signals in the same situation.

[0022]

[Effects of the Invention] As described above, according to the present invention, parts that were conventionally processed by analog circuits such as resistors and capacitors are now configured with digital circuits such as logic elements and flip-flops, and when setting the time constant, Since the value written to the register is changed, erroneous detection of two input signals with different waveforms is eliminated, and the time constant can be set individually or separately for on and off using software. Therefore, there is an effect that fine adjustment is easy and highly accurate detection can be performed.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing an embodiment of a sequencer device according to the present invention.

FIG. 2 is a specific circuit configuration diagram of FIG. 1;

FIG. 3 is a diagram showing signal waveforms of various parts to explain the operation of the embodiment shown in FIGS. 1 and 2;

FIG. 4 is a schematic block diagram showing another embodiment of the invention.

FIG. 5 is a specific circuit configuration diagram of FIG. 4;

FIG. 6 is a diagram showing signal waveforms of various parts to explain the operation of the embodiment shown in FIGS. 4 and 5;

FIG. 7 is a circuit configuration diagram showing an example of conventional technology.

FIG. 8 is a diagram showing signal waveforms of various parts to explain the operation of the conventional example shown in FIG. 7;

FIG. 9 is a diagram showing signal waveforms of various parts to explain the operation of the conventional example shown in FIG. 7;

[Explanation of symbols]

1 CI input signal 2 DLO input signal 3 CI output signal 4 DLO output signal 6 NAND circuit 7 Sequencer circuit 8 Counter circuit 9 Time constant register 11 On time constant setting register 12 Off time constant setting register 13 Selector

Claims (2)

[Claims] 1. A sequencer circuit comprising an AND circuit, an OR circuit, a flip-flop, etc., which controls two input signals with different waveforms and determines their output, and a time constant setting which sets the time constant according to the input signal. It comprises a register, and a counter circuit that is controlled by start and stop signals sent from the sequencer circuit and counts a predetermined period according to the value of a time constant written in the register, and the count output of this counter circuit is controlled by the start and stop signals sent from the sequencer circuit. A sequencer device that prevents erroneous detection of the two input signals by sending the signals to a sequencer circuit and based on the output thereof. 2. A sequence circuit comprising an AND circuit, an OR circuit, a flip-flop, etc., which controls two input signals with different waveforms and determines their output, and a sequence circuit whose on time constant and off time constant are determined according to the input signal. an on-time constant setting register and an off-time constant setting register that respectively set the on-time constant setting register and off-time constant setting register, a selector that switches the on-time constant setting register and the off-time constant setting register, and a start and stop signal sent from the sequencer circuit, and and a counter circuit that counts a predetermined period according to the time constant values written in the on-time constant setting register and the off-time constant setting register, respectively, and sends the count output of this counter circuit to the sequencer circuit and outputs it. A sequencer device characterized in that erroneous detection of the two input signals is prevented based on the following.