JPH0653811A - Ic input circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction due to an external signal and to reduce the cost of an input circuit by forming a pulse signal synchronized with a prescribed clock from an external signal and when the signal length of the pulse signal is larger than a prescribed value, outputting the pulse signal from the output side. CONSTITUTION:An initializing circuit to be used at the time of turning on a power supply is constituted of a NOT circuit 26, a NAND circuit 25, an OR circuit and an internal clock CLK 1. A Schmitt output 6, a D-FF A 19 with a reset terminal, a DFF B20 with a reset terminal, an exclusive NOR circuit 21 and an AND circuit 22 constitute a synchronous circuit for synchronizing an external signal with an internal clock and a pulse forming circuit for forming a pulse at the time of changing the synchronous signal and an external signal synchronizing means is constituted of both circuits. At this time, D-F/F 23 with the reset and the reset D-F/FD 24 are counted with the pulse of the external synchronizing means. After the lapse of the prescribed time it goes to a timer outputted to the external signal processing circuit to prevent the input of the external signal having the pulse length or below decided by the counted number.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC input circuit, and more particularly to an IC input circuit capable of preventing malfunction due to an external signal.

[0002]

2. Description of the Related Art Conventional examples of the present invention are shown in FIGS.
FIG. 9 will be described. 7 and 8 are block diagrams showing an example of a conventional IC input circuit, and FIG. 9 is a timing chart showing the operation of FIGS. 7 and 8. Figure 7
, 1 is a switch for mechanically detecting an external action and converting it into an electric signal, 2 is connected to the switch 1,
It operates by receiving an electric signal that has converted the action from the outside.
7C and 3C are provided in the IC2, the switch 1 is connected to the input side of the IC2, and have different predetermined thresholds with respect to rising and falling of an electric signal input as an external signal. The Schmitt trigger circuit 4 for converting to a logic level is provided in the IC 2 and is connected to the output side of the Schmitt trigger circuit 3, and is an external signal processing circuit 5 for processing the signal converted by the Schmitt trigger circuit 3.
Is a switch output signal which is an output signal of the switch 1, and 6 is a Schmitt output which is an output signal of the Schmitt trigger circuit 3. Further, in FIG. 8, 7 is a sensor which has a function equivalent to that of the switch 1 and electrically detects an action from the outside. This sensor has a resistor R between the power source Vcc and the earth G.
1 and the photodiode 7a connected via the power source V
It is composed of a phototransistor 7b connected between cc and the ground G through a resistor R2. Reference numeral 8 denotes an output signal of the sensor 7, which is a sensor output signal equivalent to the switch output signal 5. In FIG. 9, CLK1 is an internal clock that creates the timing at which IC2 operates, and 10 is IC2.
Is a reset signal for controlling the internal operation of the IC 2 when the power is turned on and when a decrease in the power supply voltage is detected.

Next, the operation will be described. It is assumed that the power supply voltage of IC2 is 5V, and that the logic inside IC2 is 0, 0V, and 1 is 5V, positive logic. When the power of IC2 is turned on, the IC
A power supply voltage detection circuit 2 (not shown) detects the rising of the power supply voltage and outputs the reset signal 10 to 0 after a certain period of time.
Switch from 1 to 1. IC2 when reset signal 10 is 0
Stop the operation of, set the initial state of the internal logic,
When it is 1, it is a signal for operating the IC 2. Reset signal 1
When 0 changes from 0 to 1, the IC 2 completes the setting of the initial state, enters the operating state, and waits for processing of internal signals and waiting for signal input from the outside.

Since the signal processing operations of FIGS. 7 and 8 are the same,
The operation timing of FIG. 7 will be described with reference to FIG. When the switch 1 is opened / closed, the output is the switch output signal 5
Vibrates between 5V and 0V and becomes an analog electric signal. The switch output signal 5 which is the analog signal is input to the Schmitt trigger circuit 3 of the IC 2 as an external signal. The switch output signal 5 input to the Schmitt trigger circuit 3 is set to 1 by the low level threshold VTH- and the high level threshold VTH + of the Schmitt trigger circuit 3.
Or converted to a digital signal of 0, Schmitt output 6
Is input to the external signal processing circuit 4. From the above,
The processing of the external signal to the IC2 is completed, and the action from the outside is processed inside the IC2.

By the way, when the IC2 processes an external signal, a circuit which operates in synchronization with the rising or falling timing of the internal clock CLK1 or its frequency-divided output exists inside the IC2 and a circuit which is asynchronous. . The switch 1, which is an action from the outside, may cause opening and closing that vibrates in an environment such as vibration impact.
The Schmitt trigger circuit 3 that receives the vibrated switch output signal 5 detects that the switch output signal 5 has a threshold value VT.
When H- or VTH + is exceeded, the change is output as the Schmitt output 6. External signal processing circuit 4 of IC2
If the internal clock CLK1 includes a processing circuit that is not synchronized with the internal clock CLK1, the operation may be affected by the signal change of the Schmitt output 6 due to the vibration, resulting in a malfunction.

[0006]

The input circuit of the conventional IC is configured as described above, and since the internal clock CLK1 is asynchronous with respect to the action from the outside, the action from the outside and the internal clock CLK1 are synchronized with each other. The operation timing of the input pulse limiting circuit may be shifted depending on the timing. or,
In the case where the input pulse limiting circuit operates in synchronization with the internal clock CLK1, there is a problem that if the external action is input in a time shorter than the cycle of the internal clock CLK1, the external action cannot be accepted. It was Further, among the circuits of IC2, the internal clock CLK1
On the other hand, there is a problem that only the asynchronous circuit portion operates, which may cause a malfunction, resulting in a product with low reliability.

On the other hand, in order to prevent such malfunctions, all circuits are synchronized with the internal clock CLK1 or an external signal having a time shorter than the cycle of the internal clock CLK1 is supplied to the IC.
It is conceivable to provide an integrating circuit using a CR between the switch 1 and the Schmitt trigger circuit 3 so as not to input to the IC 2, but in this case, there is a problem that the cost of the IC 2 becomes high.

The present invention has been made to solve the above-mentioned problems, and an IC that does not cause a malfunction due to an external signal and does not cause a cost increase.
The purpose is to obtain the input circuit of.

[0009]

An input circuit of an IC according to a first aspect of the present invention is an external signal synchronizing means for forming an external signal input from an external circuit into a pulse signal synchronized with a predetermined clock and outputting the pulse signal. And an external signal selecting means which is connected to the output side of the external signal synchronizing means and which outputs the pulse signal from the output side when the pulse signal length formed by the external signal synchronizing means is a predetermined value or more. It is a thing.

[0010]

The input circuit of the IC according to claim 1 of the present invention is
The external signal synchronizing means forms an external signal input from an external circuit into a pulse signal which is synchronized with a predetermined clock. Then, the external signal selecting means outputs this pulse signal from the output side when the pulse signal length formed by the external signal synchronizing means is equal to or more than a predetermined value.

[0011]

EXAMPLES Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. 1 is a block diagram showing a first embodiment, FIG. 2 is a logic diagram of an input pulse limiting circuit in the first embodiment, and FIG. 3 is a logic symbol (A) to (G) used in FIG. 2 and a truth table thereof. 4 (H) to (N) and FIGS. 4 to 6 are timing charts showing the operation of the input pulse limiting circuit under each operating condition.

In the figure, reference numerals 1 to 3, 5, 6, 9, and 10 indicate the same or corresponding parts as those described with reference to FIGS. In the figure, 11 is connected to the output side of the Schmitt trigger circuit 3, and the Schmitt output 6
Input pulse limiting circuit that receives external signals and processes them, 4A
Is an external signal processing circuit connected to the output side of the input pulse limiting circuit 11, and 12 is an output of the input pulse limiting circuit output from the input pulse limiting circuit 11 and synchronized with the internal clock CLK1. In FIG. 2, reference numeral 18 denotes a divided internal clock obtained by dividing the internal clock CLK1, and 19
Is a D-type flip-flop circuit with reset (hereinafter referred to as DF / F with reset) A, and this DF / FA with reset 19 has a Schmitt output 6 input to its data terminal, Internal clock C on the clock terminal
LK1 is input and the reset signal 1 is input to the reset terminal.
0 is input. 20 has reset D on its data terminal
-The Q output terminal of F / FA19 is connected and its output Q1
In the D-F / FB with reset 9 to which 9 is input, the internal clock CLK1 is input to the clock terminal of the D-F / FB with reset 20, and the reset signal 10 is input to the reset terminal. 21 has one input terminal thereof connected to the Q output terminal of the DF / FA 19 with reset to input its output Q19, and has the other input terminal connected to the Q output terminal of the DF / FB 20 with reset. Exclusive NOR circuit to which the output Q20 is input, 2
2 is an exclusive NOR circuit 2 at one of its input terminals
1 output terminal is connected and its output Y21 is input,
This is an AND circuit in which the reset signal 10 is input to the other input terminal.

In FIG. 2, reference numeral 23 denotes a reset D-F / FC whose data terminal is connected to a power source and maintained at a high level.
3, the divided internal clock CLK2 is input to its clock terminal, the output terminal of the AND circuit 22 is connected to its reset terminal, and its output Y21 is input. 24 is a D with reset in which the Q output terminal of the DF / FC23 with reset is connected to its data terminal and the output Q23 is input.
-F / FD, and this D-F / FD24 with reset
The divided internal clock CLK2 is input to its clock terminal, the output terminal of the AND circuit 22 is connected to its reset terminal, and its output Y22 is input.

Further, in FIG. 2, 25 is a NAND circuit in which the Schmitt output 6 is input to one of its input terminals and the reset signal 10 is input to the other input terminal via the knot circuit 26, and 27 is one of them. Of the Schmitt output 6 is input to the input terminal of and the reset signal 10 is input to the other input terminal, and 28 is connected to the data output terminal of the Q output terminal of the DF / FA with reset 19 and Output Q19 is input D with set / reset
This is a flip-flop with this set / reset D
The flip-flop 28 has its clock terminal connected to the Q output terminal of the DF / FD 24 with reset to output its output Q.
24 is input, the output terminal of the NAND circuit 25 is connected to its set terminal and its output Y25 is input, and the output terminal of the OR circuit 27 is connected to its reset terminal and its output Y27 is input.

The operation of the first embodiment will be described below.
For convenience of description, the high level 5V of the signal is represented by 1, and the low level 0V of the signal is represented by 0. First, the power-on time will be described with reference to FIGS. 2 and 4. When the power of the IC2 is turned on, the power supply voltage detection circuit (not shown) of the IC2 detects the rising of the power supply voltage and the reset signal 1
0 is switched from 0 to 1 after a certain period of time. When the reset signal 10 is 0, the operation of the IC2 is stopped, and when the reset signal 10 is 1, the IC is stopped.
2 is a signal for operating. When the reset signal 10 changes from 0 to 1, since the switch 1 is not operating, it is in one of the open and closed states, and the switch output signal 5 is output to the Schmitt trigger circuit 3.

Since the voltage level of the switch output signal 5 is fixed in the Schmitt trigger circuit 3, the 0 or 1 signal is used as the Schmitt output 6 and the DF / FA with reset is supplied.
It outputs to the data terminal 19 and one input terminal of each of the NAND circuit 25 and the OR circuit 27. The reset signal 10 is applied to the other input terminals of the NAND circuit 25 and the OR circuit 27.
When the reset signal 10 is 0, the output Y27 is 0 if the Schmitt output 6 is 0, and the output Y25 is 0 if the Schmitt output 6 is 1.

The outputs Y25 and Y27 are connected to the set terminal and the reset terminal of the D / F / F28 with set / reset, respectively, so that when the output Y25 is 0, the D / F / F28 with set / reset is connected. Q output is 1, output Y2
When 7 is 0, it becomes 0. DF with set / reset
Since the Q output of 28 is the input pulse limiting circuit output 12, the initial state of the switch 1 when the power is turned on is output as the input pulse limiting circuit output 12 and input to the external signal processing circuit 4A. Further, since the reset signal 10 is input to the AND circuit 22, the output Y22 becomes 0 according to the change of the reset signal 10 and is output to the reset terminals of the reset D-F / FC 23 and the reset D-F / FD 24, respectively. To be done.

Since the reset DF / FC 23 and the reset DF / FD 24 form a timer circuit, they operate at the rising edge of the internal clock CLK2 input to each clock terminal after completion of each reset. ,
The output Q24 is changed from 0 to 1 after the second rising edge of the internal clock CLK2. Since the output Q24 is input to the clock terminal of the D / F / F with set / reset 28, the output Q19 input to the data terminal is output at the rising edge of the output Q24. Since the output Q19 at this time does not change, the input pulse limiting circuit output 12 maintains the conventional state. As described above, the setting of the initial state when the power is turned on is completed, and the switch output signal 5 is ready for input.

Next, when the switch output signal 5 changes from 1 to 0 (the time for maintaining the logic level of 0 after the change is assumed to be infinite), the Schmitt trigger circuit 3 makes the switch output signal 5 the threshold value. Until the value VTH- is reached, the Schmitt output 6 is kept at 1 and the switch output signal 5 becomes VTH.
-When the value is below, the Schmitt output 6 is changed to 0.
The DF / FA 19 with reset which has received the change of the Schmitt output 6 from 1 to 0 changes the output Q19 from 1 to 0 at the next rising edge of the internal clock CLK1. Further, at the next rising edge of the internal clock CLK1, the output Q20 of the DF / FB 20 with reset is similarly changed from 1 to 0. Output Q19 and output Q at this time
The logic of 20 does not match, and the output Y21 of the exclusive NOR circuit 21 which receives the two of them does not output Q19.
Is 0 from the change of 1 from 0 to the change of the output Q20 from 1 to 0. In the AND circuit 22 which receives the output Y21 and the reset signal 10, 0 is prioritized, so the output Y2
When 1 is 0, 0 is output as the output Y22.

Output Y22 is DF / FC23 with reset
And the D-F / FD24 with reset are input to the respective reset terminals, so that when the output Y22 is 0, the D-F / FC23 with reset and the D-F / FD24 with reset are input.
Outputs 0 as the output Q23 and the output Q24, respectively. Since the data terminal of the DF / FC 23 with reset is connected to the power supply, after reset, the internal clock C
At the rising edge of LK2, 1 is output as the output Q23. The output Q23 is input to the data terminal of the DF / FD 24 with reset, and since the output Q23 is 1 at the rising edge of the internal clock CLK2, 1 is output as the output Q24. Since the output Q24 is input to the clock terminal of the D-F / F28 with set / reset, at the rising edge from 0 to 1 of the output Q24, the input of the data terminal, that is, the 0 state of the output Q19, is input pulse limited It is output as the circuit output 12.

From the above, the switch output signal 5 is as shown in FIG.
Is transmitted to the external signal processing circuit 4A via the input pulse limiting circuit 11 shown in FIG.
2 is an output from the Q output terminal of the D / F / F 28 with set / reset shown in FIG. 2, and the timing of the clock to that clock terminal is generated by the rising edge of the internal clock CLK2. The input signal to the processing circuit 4A is a signal synchronized with the internal clock CLK1. The change of the switch output signal 5 is from 0 to 1.
At the time of, the IC2 operates in the same manner as described above.

Next, the operation of the input pulse limiting circuit 11 according to the operating state of the switch 1 after completion of the initial setting will be described with reference to FIGS. 2, 5, and 6. First, FIG. 5 will be described. FIG. 5 shows that when the switch output signal 5 changes from 1 to 0 and further changes to 1, the Schmitt trigger circuit 3
Time TB which exceeds the threshold values VTH- and VTH + of
The timing is shown when TB <T1 (one cycle time of the internal clock CLK1) and the rising edge of the internal clock CLK1 is not reached. The signal STB of the Schmitt output 6 does not depend on the rising edge of the internal clock CLK1 and the DF / FA with reset 19 which operates at the rising edge of the internal clock CLK1.
Outputs the data terminal input at the rising edge of the clock C input, the change ST of the data terminal input
B is ignored and output Q19 remains unchanged. Similarly output Q
Since 19 does not change, the output Q20 of the DF / FB 20 with reset does not change, and the exclusive OR circuit 21
Output Y21 of the AND circuit 22 and output Y22 of the AND circuit 22 do not change. The output Y22 is a counter circuit with reset D-
Since the reset terminals of the F / FC 23 and the DF / FD 24 with reset are input, each reset terminal does not become 0 except the initial setting when the power is turned on. Therefore, the output Q24 of the D-F / FD 24 with reset does not change to 1, and the D-F / F 28 with set / reset in which the output Q24 is connected to the clock terminal holds the conventional data as it is. The input pulse limiting circuit output 12 shown in FIG. Therefore, the signal change ST of the switch output signal 5
When B is less than TB <T1 and does not reach the rising edge of the internal clock CLK1, the switch output signal 5 is ignored by the input pulse limiting circuit 11 and is not output to the external signal processing circuit 4A.

Next, FIG. 6 will be described. In FIG. 6, when the switch output signal 5 changes from 1 to 0 and further changes to 1, the time TB that exceeds the threshold values VTH- and VTH + of the Schmitt trigger circuit 3 is T1 <TB <T2 (1 of the internal clock CLK2). The cycle time is shown in FIG. The signal STB of Schmitt output 6 is
Since T1 <TB, after the Schmidt output 6 changes from 1 to 0, the output Y22 of the AND circuit 22 outputs 0 for one period T1 from the rising edge of the next internal clock CLK1 to the next rising edge. To do. The DF / FC23 with reset and the DF / FD24 with reset that received 0 of the output Y22 are reset, and after two rising edges of the internal clock CLK2 for operating the counter circuit again, the output Q24 changes from 0 to 1 The DF / F 28 with set / reset outputs the signal Q19 input to the data terminal as the output 12 of the input pulse limiting circuit in FIG. Since the output Q19 at this time is 1, 1 is output as the input pulse limiting circuit output 12, and the change in the signal of the switch output signal 5 is ignored. The output Q19 is input to the data terminal of the D / F / F 28 with set / reset, and the output Q19 is a synchronizing signal of the internal clock CLK1 of the Schmitt output 6.
Therefore, even if the switch output signal 5 changes at the timing of the rising edge of the output Q24, the internal clock CL
Since the internal clock CLK2 is changing at the fall of K1, this is also ignored. Alternatively, DF / FA19 with reset and DF / FB with reset
When the output Q19 and the output Q20 of the respective 20 change, a signal of 0 is output as the output Y22. Therefore, the DF / FC23 with reset and the DF / FD24 with reset, which are the timer circuits, are reset to output Q24. Output becomes 0 and will be re-counted. Therefore, the signal change STB of the switch output signal 5 is T1 <TB <T2.
Also in the case of, the switch output signal 5 is the input pulse limiting circuit 1
It is ignored at 1 and is not output to the external signal processing circuit 4A.

As described above, the switch output signal 5 is output to the external signal processing circuit 4A by the input pulse limiting circuit 11 only when the signal change STB of the switch output signal 5 is T1 + T2 <TB, and the signal processing is performed. It Actually, the internal clock CLK1 and the internal clock CLK
The pulse width whose input is limited by the timing of 2 is
It varies from T1 + T2 to twice T1 + T2. In order to suppress this variation, DF / FC23 or DF / FC /
This is possible by increasing the number of flip-flops such as the FD 24 or increasing the frequencies of the internal clocks CLK1 and CLK2. In the description of the embodiment of the present invention, the case where the change of the signal of the Schmitt output 6 changes from 1 to 0 and then returns to 1 has been described, but the same applies to the case of the signal change of changing from 0 to 1 and then returns to 0. The effect of can be obtained.

As is clear from the above description, the knot circuit 26, the NAND circuit 25, the OR circuit 27 and the internal clock CLK1 constitute an initial setting circuit when the power is turned on, and the Schmitt trigger circuit 3 and the reset DF / F / The FA 19, the DF / FB 20 with reset, the exclusive NOR circuit 21, and the AND circuit 22 include a synchronizing circuit that synchronizes an external signal with an internal clock and a pulse forming circuit that forms a pulse when the synchronized signal changes. The external signal synchronization means in claim 1 is configured. In addition, DF / FC23 with reset, DF / FD24 with reset
Constitutes a timer circuit which starts counting by the pulse formed by the external signal synchronizing means and outputs it to the external signal processing circuit 4A after a fixed time. An external signal having a pulse length equal to or shorter than the pulse number determined by the count number of the timer circuit is an external signal. Since it is prevented from being input to the processing circuit 4A,
The external signal selecting means in claim 1 is configured.

Example 2. Although the first embodiment has been described above, since the input pulse limiting circuit 11 of the present invention is configured by general logic, the AND circuit can be changed to the NOR circuit by inverting the input.
Further, the circuit configured by the D-type flip-flop circuit can be configured by another flip-flop circuit such as T-type.

[0027]

As described above, in the input circuit of the IC according to the first aspect of the present invention, the external signal synchronization for forming and outputting the external signal input from the external circuit into the pulse signal synchronized with the predetermined clock is output. Means and an external signal selecting means connected to the output side of the external signal synchronizing means and outputting the pulse signal from the output side when the pulse signal length formed by the external signal synchronizing means is a predetermined value or more. As a result, the malfunction of the IC due to the asynchronousness of the external signal is prevented, and the input of the external signal for a shorter time than the internal clock is prevented. Since a highly reliable product can be obtained without being affected by disconnection and there is no need to increase the number of external circuits, the device can be inexpensive.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a logic diagram of an input pulse limiting circuit in the first embodiment.

3 is a logic symbol used in FIG. 2 and a truth table thereof. FIG.

FIG. 4 is a timing chart showing the operation of the input pulse limiting circuit.

FIG. 5 is a timing chart showing the operation of the input pulse limiting circuit.

FIG. 6 is a timing chart showing the operation of the input pulse limiting circuit.

FIG. 7 is a block diagram showing an example of a conventional IC input circuit.

FIG. 8 is a block diagram showing another example of an input circuit of a conventional IC.

9 is a timing chart showing the operation of FIG.

[Explanation of symbols]

 2 IC 11 Input pulse limiting circuit 19 DF / FA with reset 20 DF / FB with reset 21 Exclusive NOR circuit 22 AND circuit 23 DF / FC with reset 24 DF / FD with reset 25 NAND Circuit 26 Knot Circuit 27 OR Circuit

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[Procedure amendment]

[Submission date] April 19, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0002

[Correction method] Change

[Correction content]

[0002]

2. Description of the Related Art Conventional examples of the present invention are shown in FIGS.
9, 10 and 11 will be described. 7, 8,
FIG. 10 is a block diagram showing an example of a conventional IC input circuit, FIG. 9 is a timing chart showing the operation of FIGS. 7 and 8 , and FIG. 11 is a timing chart showing the operation of FIG. In FIG. 7, 1 is a switch for mechanically detecting an action from the outside and converting it into an electric signal, 2 is connected to the switch 1, and I7C, 3 which operates by receiving the electric signal with the action converted from the outside, The switch 1 is provided on the input side of the IC 2 and is connected to the input side thereof.
A Schmitt trigger circuit 4 for converting to a logic level of the IC2, each having a different predetermined threshold value, is provided in the IC2 and is connected to the output side of the Schmitt trigger circuit 3.
An external signal processing circuit for processing the signal converted by the Schmitt trigger circuit 3, 5 is a switch output signal which is an output signal of the switch 1, and 6 is a Schmitt output which is an output signal of the Schmitt trigger circuit 3. Also, in FIG.
Is a sensor that has the same function as the switch 1 and that electrically detects an external action. This sensor is a power source Vcc.
And a ground G via a resistor R1 and a phototransistor 7b connected between a power source Vcc and a ground G via a resistor R2. 8 is an output signal of the sensor 7, which is a switch output signal 5
Shows a sensor output signal equivalent to Further, in FIG. 9, CLK1 is an internal clock that creates the timing at which the IC2 operates, and 10 is a reset signal that controls the internal operation of the IC2 when the power of the IC2 is turned on and when a decrease in the power supply voltage is detected. In FIG. 10, 28 is the Schmitt output 6 input.
Delay time to output Y28 after being delayed for a certain time.
And 29 is the Schmitt output 6 and the output Y2 of the delay circuit 28.
An AND circuit that receives 8 and outputs Y29, 30 is an
The output Y29 of the output circuit 29 is input as data.
D-type flip-flop circuit (with reset)
It is referred to as DF / F. ), 31 is D-F / with reset
The clock signal of F30 is shown. Such a circuit is
For example, the one disclosed in Japanese Patent Publication No. 310974 of 1990
Is known.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0005

[Correction method] Change

[Correction content]

By the way, when the IC2 processes an external signal, a circuit which operates in synchronization with the rising or falling timing of the internal clock CLK1 or its frequency-divided output exists inside the IC2 and a circuit which is asynchronous. . The switch 1, which is an action from the outside, may cause opening and closing that vibrates in an environment such as vibration impact.
The Schmitt trigger circuit 3 that receives the vibrated switch output signal 5 detects that the switch output signal 5 has a threshold value VT.
When H- or VTH + is exceeded, the change is output as the Schmitt output 6. External signal processing circuit 4 of IC2
If the internal clock CLK1 includes a processing circuit that is not synchronized with the internal clock CLK1, the operation may be affected by the signal change of the Schmitt output 6 due to the vibration, resulting in a malfunction. next
The operation of FIGS. 10 and 11 will be described. IC2 power
When the power is turned on, the power supply voltage detection circuit of IC2
The rising edge of the pressure is detected, and the reset signal 10 changes from 0 to 1.
When it changes to, IC2 finishes setting the initial state and can operate.
The internal signal processing and signal input from the outside.
It will be in a waiting state. Reset signal 10 is with reset
Since it is input to R of D-F / F30, the reset signal
When the signal 10 becomes 0, the output Q30 becomes 0 and other signals
Is waiting for input. The reset signal 10 is 0
Since then, when switch 1 is closed, the switch output signal
5 is input to the Schmitt input 3, and the Schmitt output 6
And outputs 0. Since the Schmitt output 6 is 0,
The output Y29 of the AND circuit 29 becomes 0. With reset
The output Y29 input to D of the D-F / F30 is 0.
Therefore, the clock signal is input to C of D-F / F30 with reset.
Even if the rising edge of 31 is input, the output Q30 is
It remains 0 and does not change. After this, the external action
The switch 1 vibrates in an environment such as a vibration shock for a short time.
The switch output signal 5 causes the open state between
Rising from 0V to + 5V, Schmitt input 3 threshold
The Schmidt output 6 is set to 0 when the threshold value VTH + is exceeded.
Change from 1 to 1. After that, switch 1 is open
Is a short time, switch output signal 5 is from + 5V to 0V
Falling to the threshold VTH- of the Schmitt input 3
When it exceeds, the Schmidt output 6 is changed from 1 to 0.
The pulse of 0-1-0 at time T3 is the Schmitt output 6
Occurs in. T3 of this Schmitt output 6 is a delay circuit
28, and the pulse time is T4 after the delay time Td.
Is output to the output Y28. Schmidt output 6 and output Y
The AND circuit 29 to which 28 is input has both two inputs.
Output Y29 is set to 1 when both are 1, so the time of T3 is T
If it is shorter than d (T3 <Td), Y29 is set to 0.
keep. Output Y29 is 0, so DF / F with reset
The signal of the output Q30 of 30 also remains 0 and does not change. Also,
When the switch 1 changes from the closed state to the open state,
The switch output signal 5 rises from 0V to + 5V,
When the threshold value VTH + of the input 3 is exceeded,
The Schmidt output 6 is changed from 0 to 1. This Sumi
Output 6 is input to the delay circuit 28, and the delay time Td
After that, the output Y28 is changed from 0 to 1. AND circuit 2
9 is Schmitt when both inputs are 1
Change after Td time from the change of the output 6 signal from 0 to 1.
After the output Y28 changes from 0 to 1, the AND circuit 29
The output Y29 of is changed from 0 to 1. This Y29 belief
Issued at the rising edge of clock signal 31 after the change of signal.
Force Q30 changes from 0 to 1 and switch output 5
No. processing device 4 is transmitted. Then switch 1 opened
In a state, it vibrates in an environment such as vibration impact for a short time
Switch output signal 5 is +
The threshold of Schmitt input 3 falls from 5V to 0V
When the value VTH- is exceeded, the Schmitt output 6 is set to 1
Change from 0 to 0. After that, the open state of switch 1
Switch output signal 5 changes from 0V to + 5V because it is a short time
Rising, exceeding the threshold VTH + of Schmitt input 3
At that time, the Schmitt output 6 is changed from 0 to 1.
Then, the pulse of 1-0-1 time T5 is the Schmitt output 6
Occurs in. T5 of this Schmitt output 6 is a delay circuit
28, and the pulse time is T6 after the delay time Td.
Is output to the output Y28. Schmidt output 6 and output Y
The AND circuit 29 to which 28 is input has both two inputs.
When both are 1, the output Y29 is 1, so the logic is 0.
The pulse of T5 and T6 is directly output from the AND circuit 29.
It is output as Y29. Output Y29 logic is 1 to 0
Clock signal 3 during the time of T5 and T6 that changed to
When a rising edge of 1 is input, D with reset
-The output Q30 of the F / F30 changes from 1 to 0. Y2
9 changes to 1 again and the clock signal 31 rises
When an edge is input, Q30 changes to 1. Therefore
The instantaneous interruption of T5 of the switch output 5 is outside as T7 and T8.
It is input to the local signal processing device. In this way, switch out
It is possible to prevent a momentary interruption from the state where the logic of force 5 is 1.
do not come. In addition, switch 1 is open,
H When the output 5 logic is 1, the reset signal 10 logic
Becomes 0 and the operation of setting the initial state of the IC during the time T9
When the reset signal 10 changes from 1 to 0,
Q30 changes from 1 to 0. However, with reset
The logic of Y29 input to the input D of DF / F30 is
Since it is 1, the logic of the reset signal 10 changes from 0 to 1.
The first rising edge of the clock signal 31 after conversion.
Then, the logic of Q30 changes from 0 to 1. That is T9
When the time reset signal 10 becomes 0, only Q for T10
30 becomes 0, and the state that does not match the state of switch 1
Occur.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction content]

[0006]

FIG. 7, FIG. 8 of a conventional example,
In FIG. 9, the input circuit of the IC is configured as described above,
Since the internal clock CLK1 is asynchronous with respect to the action from the outside, the operation timing of the input pulse limiting circuit may be shifted depending on the action from the outside and the timing of the internal clock CLK1. Further, in the case where the input pulse limiting circuit operates in synchronization with the internal clock CLK1, there is a problem that if the external action is input in a time shorter than the cycle of the internal clock CLK1, the external action cannot be accepted. was there. Further, in the circuit of the IC2, only the circuit part asynchronous with the internal clock CLK1 operates, which may cause a malfunction, resulting in a low reliability product. Furthermore, in FIGS. 10 and 11 of the conventional example, the switch 1 is
Due to momentary opening and closing due to vibration and shock in the open state
To prevent the transmission of signal changes to the external signal processing device 4.
I can't. In the initial state after reset, the switch
It sometimes happens that the state of the switch 1 does not match. They are,
Unreliable products that may cause malfunction.
There was a problem that

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction content]

On the other hand, in order to prevent such malfunctions, all circuits are synchronized with the internal clock CLK1 or an external signal having a time shorter than the cycle of the internal clock CLK1 is supplied to the IC.
It is conceivable to provide an integrating circuit using a CR between the switch 1 and the Schmitt trigger circuit 3 so as not to input the signal to the switch 2. However, in this case, there is a problem that the device cost increases.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Name of item to be corrected] Fig. 10

[Correction method] Added

[Correction content]

FIG. 10 is a block diagram showing another example of a conventional IC input circuit.
FIG.

[Procedure correction 6]

[Document name to be amended] Statement

[Name of item to be corrected] Fig. 11

[Correction method] Added

[Correction content]

11 is a timing chart showing the operation of FIG .
It

[Procedure Amendment 7]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 10

[Correction method] Added

[Correction content]

[Figure 10]

[Procedure Amendment 8]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 11

[Correction method] Added

[Correction content]

FIG. 11

Claims (1)

[Claims] 1. An input circuit of an IC, which is connected to an external circuit and takes in a signal from the external circuit into the IC, wherein the external signal input from the external circuit is formed into a pulse signal synchronized with a predetermined clock. A signal synchronizing means and an external signal selecting means connected to the output side of the external signal synchronizing means and outputting the pulse signal from the output side when the pulse signal length formed by the external signal synchronizing means is equal to or more than a predetermined value. An input circuit for an IC, comprising: