JP2679481B2 - Self-propelled synchronous circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing circuit which operates by inputting a frame pulse signal and a clock signal having a constant period and outputs a counter value.

[0002]

2. Description of the Related Art A conventional synchronizing circuit will be described with reference to FIG. The conventional synchronizing circuit includes a frame pulse input terminal 11 for inputting an input frame pulse signal FP, a clock input terminal 12 for inputting an input clock signal CL,
It has a counter value output terminal 13 for outputting the counter value CV.

The conventional synchronizing circuit has an N-ary binary counter 14 capable of initializing a counter value CV, an AND gate 15, and an inverting gate 16. The N-ary binary counter 14 has a clock terminal 14a and an initial value setting terminal 14
b, a counter value output terminal 14c, a ripple carry terminal 14d, and a load terminal 14e.

The clock input terminal 12 is connected to the clock terminal 14a of the N-ary binary counter 14. The counter value output terminal 14 c of the N-ary binary counter 14 is connected to the counter value output terminal 13. The frame pulse input terminal 11 is connected to one input terminal of the AND gate 15, and the output terminal of the AND gate 15 is connected to the load terminal 14e of the N-ary binary counter 14. The ripple carry terminal 14d of the N-ary binary counter 14 is connected to the input terminal of the inverting gate 16, and the output terminal of the inverting gate 16 is connected to the other input terminal of the AND gate 15.

The operation of the conventional synchronous circuit will be described below with reference to FIGS. 3 and 4. The input frame pulse signal FP supplied to the frame pulse input terminal 11 is
It is a signal that becomes an active "low" level for one clock cycle at a constant cycle. The input clock signal CL supplied to the clock input terminal 12 is a periodic signal operating at a faster cycle than the input frame pulse signal FP.

The N-ary binary counter 14 operates in synchronization with the rising edge of the input clock signal CL supplied to the clock terminal 14a, counts the number of clock pulses of the input clock signal CL, and outputs a binary counter value CV. It is output from the counter value output terminal 14c. The N-ary binary counter 14 can set the initial value I (N ≧ I) of the counter value CV from the initial value setting terminal 14b.

FIG. 4 shows the timing for loading the initial value I. When the counter value CV reaches the maximum value N, the N-ary binary counter 14 outputs an active "high" level ripple carry signal RC for one clock cycle from the ripple carry terminal 14d.

Here, the initial value I is set so that the timing at which the input frame pulse signal FP becomes active in a certain cycle and the timing at which the ripple carry signal RC becomes active coincide with each other.

Inverting gate 1 for ripple carry signal RC
The ripple carry signal IV1 and the input frame pulse signal FP inverted in 6 are supplied to the AND gate 15. Normally, these two signals IV1 and FP become active "low" level at the same timing. Therefore, at this timing, the "low" level AND signal A
D is supplied from the AND gate 15 to the load terminal 14e of the N-ary binary counter 14 as a load signal. In response to this load signal, the N-ary binary counter 14 sets the initial value I from the initial value setting terminal 14b.

In this conventional synchronizing circuit, even if the input frame pulse signal FP is kept at the "high" level due to some abnormality, once the N-ary binary counter 14 starts to operate, the input clock signal CL is changed. As long as normal
The N-ary binary counter 14 has a ripple carry signal RC
Is output. Therefore, the load signal AD output from the AND gate 15 periodically outputs an active "low" level signal. As a result, the N-ary binary counter 14 can run by itself.

[0011]

However, in the above-mentioned conventional synchronizing circuit, the input frame pulse signal FP for setting the initial value I of the N-ary binary counter 14 becomes abnormal and becomes active "low" level. In the case of no occurrence, the "low" level load signal is continuously supplied to the load terminal 14e of the N-ary binary counter 14. Therefore, there is a drawback that the N-ary binary counter 14 cannot be synchronized.

Therefore, the problem to be solved by the present invention is that even if the input frame pulse signal for setting the initial value in the counter becomes abnormal and continues to be at the "low" level or "high" level, the synchronization The purpose is to provide a self-propelled synchronous circuit that can keep taking.

[0013]

A self-propelled synchronous circuit according to a first aspect of the present invention sets an initial value in response to a load signal in order to transmit and receive data between a plurality of circuit parts.
Then, in a synchronous circuit including a counter that inputs an input frame pulse signal and an input clock signal of a constant cycle and performs a count operation, and outputs a counter value, the input frame pulse signal becomes abnormal and becomes "low" level or
Even if the “high” level continues , the load signal
A feedback section capable of causing the counter to self- run only by the input clock signal and continuously synchronizing the plurality of circuit sections with each other by continuously supplying the clock to the counter. Is characterized by.

[0014] self-propelled synchronization circuit according to the second aspect of the present invention receives an input clock signal and the input frame pulse signal having a constant period, performs a counting operation in synchronization with the input clock signal, the counter value In a self-propelled synchronous circuit that outputs, in response to the input clock signal, a transition point detection circuit that detects a rising transition point of the input frame pulse signal and outputs a transition point detection signal, and in response to a load signal set the initial value, and outputs the counter value after a counting operation in synchronization with the input clock signal for one clock period when該Ka <br/> down data value reaches a maximum value " A counter for outputting a high-level ripple carry signal, an inverting gate for inverting the ripple carry signal and outputting an inverted ripple carry signal, and the change point detection signal The ANDs the inverted ripple carry signal, possess the AND gate provides a logic AND signal to the counter as the load signal, the said
Input frame pulse signal becomes abnormal and becomes "low" level
Or even if the high level continues,
By continuously supplying the counter signal to the counter periodically.
The counter is self-running only with the input clock signal.
It is characterized by having been made to let .

In the self-propelled synchronizing circuit according to the second aspect, the change point detecting circuit inverts the frame pulse signal and outputs an inverted frame pulse signal, and the input clock signal. In response, the inverted frame pulse signal is delayed by one clock cycle, a D-type flip-flop that outputs a signal obtained by inverting the delayed signal as a delayed inverted signal, and the inverted frame pulse signal It is preferable that the OR gate is configured to take a logical sum with the delayed inverted signal and output the logical sum signal as the change point detection signal.

[0016]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a free running synchronous circuit according to one embodiment of the present invention is shown in FIG. 3 except that it has an inverting gate 17, a D-type flip-flop 18 and an OR gate 19. It has the same configuration as that of Therefore, components having the same function are designated by the same reference numerals, and their description will be omitted.

The D-type flip-flop 18 has a clock terminal 18a, a data input terminal 18b, and a non-inverting output terminal 1
8c and an inverting output terminal 18d. Inversion gate 17
The input terminal is connected to the frame pulse input terminal 11. The output terminal of the inverting gate 17 is connected to the data input terminal 18b of the D-type flip-flop 18 and one input terminal of the OR gate 19. D-type flip-flop 1
The eight clock terminals 18 a are connected to the clock input terminal 12. The inverting output terminal 18d of the D-type flip-flop 18 is connected to the other input terminal of the OR gate 19. The output terminal of the OR gate 19 is connected to one input terminal of the AND gate 15.

As will be apparent from the following description, the combination of the inverting gate 17, the D-type flip-flop 18 and the OR gate 19 functions as a change point detection circuit 20 for detecting the rising change point of the input frame pulse signal FP.

That is, in the conventional synchronizing circuit (FIG. 3),
Input frame pulse signal FP is directly AND gate 1
5, the frame pulse signal FP is supplied to the AND gate 15 via the change point detection circuit 20 in the free-running synchronization circuit of the present invention.

The operation of the self-propelled synchronous circuit according to the present invention will be described below with reference to FIGS. Explanation
For simplification, the description of the same operation as that of the conventional technique is omitted.

In the present invention, the input frame pulse signal FP
Are supplied to the inversion gate 17. The inverted frame pulse signal IV2 from the inverting gate 17 is supplied to the data input terminal 18b of the D-type flip-flop 18. The D-type flip-flop 18 delays the inverted frame pulse signal IV2 by one clock cycle in response to the input clock signal CL. The D-type flip-flop 18 outputs a signal obtained by inverting the delayed signal from the inverting output terminal 18d as the inverting delay signal DF. The OR gate 19 takes the logical sum of the inverted frame pulse signal IV2 and the inverted delay signal DF, and supplies the logical sum signal OR to the AND gate 15 as a change point detection signal. The AND gate 15 and the change point detection signal OR and the inversion gate 16
ANDed with the inverted ripple carry signal IV1 from the above, and the AND signal AD is supplied to the load terminal 14e of the N-ary binary counter 14 as a load signal.

As described above, according to the present invention, as shown in FIG. 3, even if the input frame pulse signal FP continues to be at the "high" level or the "low" level due to some abnormality, once, If the N-ary binary counter 14 starts operating, the ripple carry signal RC output from the ripple carry terminal 14d of the N-ary binary counter 14 will be described.
Thus, the initial value I can be set in the N-ary binary counter 14 every predetermined period. Therefore, even if the frame pulse signal FP becomes abnormal, the self-propelled synchronizing circuit of the present invention can keep synchronizing.

[0024]

As described above, according to the present invention, the frame pulse signal for setting the initial value in the counter becomes abnormal and becomes "high" level or "low" level.
Even if it continues, it is possible to keep the synchronization.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a self-propelled synchronizing circuit according to an embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the self-propelled synchronous circuit of FIG.

FIG. 3 is a block diagram showing a conventional synchronizing circuit.

FIG. 4 is a time chart for explaining the operation of the synchronous circuit of FIG.

[Explanation of symbols]

 11 Frame pulse input terminal 12 Clock input terminal 13 Counter value output terminal 14 N-ary binary counter 15 AND gate 16 Inversion gate 17 Inversion gate 18 D-type flip-flop 19 OR gate 20 Change point detection circuit

Claims (3)

(57) [Claims] 1. A count operation, in which an initial value is set in response to a load signal, and an input frame pulse signal and an input clock signal of a constant cycle are input in order to transmit and receive data between a plurality of circuit units. was carried out, in synchronization circuit including a counter for outputting a counter value, the input frame pulse signal becomes abnormal "low" Les
Even in the case of continued become a bell or a "high" level, the
Continuing to periodically supply a load signal to the counter
Self-propelled synchronizing circuit, characterized by comprising the input clock signal only is free-running the counter, the feedback unit capable of a plurality of continuously taking the synchronizing circuit each other by. Wherein receiving an input frame pulse signal having a predetermined period and the input clock signal, performs a counting operation in synchronization with the input clock signal, the self-propelled synchronous circuit for outputting a counter value, said input clock signal In response to the load signal, a transition point detection circuit that detects the rising transition point of the input frame pulse signal and outputs a transition point detection signal, and sets an initial value in response to the load signal, and synchronizes with the input clock signal. converting mechanism and outputs the counter value after counting, the counter the counter value and outputs a ripple carry signal 1 during clock cycle "high" level when it reaches the maximum value, the ripple carry signal An inversion gate that inverts and outputs an inverted ripple carry signal, and a theory of the change point detection signal and the inverted ripple carry signal Taking a product, have a, an AND gate is supplied to the counter a logical product signal as the load signal,
When the input frame pulse signal becomes abnormal, a "low" level
If the bell or “high” level continues to
Continuing to periodically supply a load signal to the counter
By the input clock signal only
A self-propelled synchronous circuit characterized by being made to run . 3. The change point detection circuit inverts the frame pulse signal to output an inverted frame pulse signal, and an additional inversion gate; and inverts the frame pulse signal in response to the input clock signal. A D-type flip-flop which delays by one clock cycle and outputs a signal obtained by inverting the delayed signal as a delayed inverted signal; and a logical sum of the inverted frame pulse signal and the delayed inverted signal, An OR gate that outputs a logical sum signal as the change point detection signal, and the self-propelled synchronous circuit according to claim 2 .