KR102451264B1 - All-digital multiplying delay-locked loop with a delta-sigma dithering cell - Google Patents

Abstract

The present invention relates to a delta-sigma dithering cell-based all-digital multiplying delay locked loop circuit, which receives an input clock signal (clk _ref ) and receives a phase error between the input clock signal (clk _ref ) and the output clock signal (clk _out ) a digitally controlled multiplexed ring oscillator that reduces the frequency of the output clock signal to within a preset delay resolution and at the same time multiplies the frequency of the output clock signal by N times that of the input clock signal; a decoder for generating a control signal for controlling the operation of the digitally controlled multiplexed ring oscillator; a delta sigma modulator for generating a control signal of the decoder to control a dithering cell of the multiplexed ring oscillator; and a digital loop filter receiving the input clock signal clk _ref and generating a digital loop filter output signal for controlling the decoder and the delta sigma modulator. is provided

Description

All-digital multiplying delay-locked loop with a delta-sigma dithering cell

The present invention relates to an all-digital multiplying delay locked loop circuit, and more particularly, to achieve low jitter and large frequency multiplication factor using a dither jitter reduction method based on a delta-sigma dithering cell. It relates to a delta-sigma dithering cell-based all-digital multiplying delay locked loop circuit that can do this.

In the case of high-speed integrated circuits such as DRAM, microprocessors, and communication chips, a delay locked loop (DLL) as a driving clock generator of an I/O interface transceiver between a chip and a chip to improve power consumption and data transmission speed I use a phase locked loop (PLL).

Delay Locked Loop (DLL) is designed to improve synchronization and timing margin, which can improve data transfer rates at chip-to-chip I/O interfaces in high-speed integrated circuits such as DRAM. It is also used for the clock data recovery (CDR) circuit of the high-speed serial link.

The delay locked loop circuit is generally divided into analog or digital methods of adjusting the delay of the delay circuit, and is divided into two types, an analog delay locked loop circuit and a digital delay locked loop circuit, depending on the type of such a feedback loop.

The analog delay locked loop circuit uses a method of storing control information for adjusting the delay amount in the capacitor of the feedback loop. In general, the analog delay locked loop circuit has a simple structure, accurate delay control capability, and good jitter characteristics. However, due to the sensitive nature of the analog circuit to process changes, it is difficult to apply to various systems due to its low portability, and it responds sensitively to control signal noise. In addition, it is difficult to have a wide operating frequency due to a long locking time.

On the other hand, the digital delay locked loop circuit uses a method of storing the delay amount adjustment control information as digital bits through a finite state machine in the feedback loop, so it is strong in control signal noise and insensitive to changes in the digital block process, so portability is good in various systems. . In addition, it can have a relatively fast locking time compared to the analog method and at the same time have wide operating frequency characteristics. However, unlike the analog delay fixed loop circuit that uses continuous analog control information, since discontinuous digital control information is used, the resolution of the adjustable delay amount is low, so accurate delay adjustment is impossible.

In recent years, multiplying delay-locked loops (MDLLs), a type of injection-locked voltage-controlled oscillators (VCOs), have been developed in digital integrated circuits (ICs) due to their superior jitter and stability performance. ) and as an on-chip clock generator for high-performance systems.

A typical multiplying delay locked loop (MDLL) can produce an output frequency that is N times the input clock frequency, where N is an integer.

In many applications, digital multiplying delay locked loops (MDLLs) not only eliminate the problem of lock-state loss during power-down, but also deterministic jitter (DJ) caused by mismatch problems in analog components such as phase detectors (PDs) and charge pumps; It is often used to reduce the problem of increasing deterministic jitter.

Multiplying delay locked loops can reduce integration jitter by periodically injecting a clean reference clock, but as the frequency multiplication factor N increases, the jitter or phase noise performance degrades rapidly.

In a digitally multiplied delay-locked loop using a bang-bang phase detector (BBPD) and a digitally controlled multiplexed ring oscillator (MRO), dithering jitter as frequency multiplication factor N increases. Dithering jitter accumulation occurs where the problem becomes more serious.

When the digital multiplying delay-locked loop is locked, the non-linearity characteristics of the bang-bang phase detector (BBPD) and the finite resolution of the multiplexed ring oscillator (MRO) cause the output clock phase of the digital multiplying delay-locked loop to Lets you move back and forth on the reference clock edge. As a result, a digital code word (DCW), that is, a control signal of a multiplexed ring oscillator (MRO), is converted by at least one LSB (Least Significant Bit) by assuming that the loop latency is 0 for simplicity. Dithering is performed back and forth based on the locking point.

The problem is that during the limit cycle, even if the DCW changes only one LSB, the integrated phase of the multiplying delay locked loop (MDLL) output clock shifts by N × Δt, where Δt is the digitally controlled multiplexed ring. It is the time resolution of the oscillator (MRO). Consequently, as N increases or the reference clock period (T _REF ) increases, the magnitude of the deterministic jitter (DJ) of the digital multiplying delay locked loop (MDLL) increases rapidly in proportion to N. Therefore, it is difficult to design a digital MDLL with large N, and most digital multiplying delay locked loops (MDLLs) have only a frequency multiplication factor of N = 32 or less.

To overcome this limitation, one of the conventional digital multiplying delay locked loops (MDLL) is a scrambling time-to-digital converter (TDC) having a second order delta-sigma modulator (DSM). , reduce the limit cycle period to 1/64 and achieve N. However, this digital multiplying delay locked loop (MDLL) requires the use of an 8-bit current mode DAC with 255 current sources to drive the multiplexed ring oscillator (MRO), which has a large area and high power consumption. There is this.

Korean Patent Registration No. 10-0321732

The present invention is to overcome the above-mentioned conventional problems, and the problem to be solved by the present invention is to multiply low jitter and large frequency using a dither jitter reduction method based on a delta-sigma dithering cell. It is to provide a delta-sigma dithering cell-based all-digital multiplying delay-locked loop circuit that can achieve

In addition, it is to provide a delta-sigma dithering cell-based all-digital multiplying delay locked loop circuit that can reduce static phase offset and improve jitter performance by applying a stochastic phase detector. .

According to an exemplary embodiment of the present invention, a digital control that receives an input clock signal clk _ref and reduces the phase error between the input clock signal clk _ref and the output clock signal clk _out within a preset delay resolution. multiplexed ring oscillator;

a decoder for generating a control signal for controlling the operation of the digitally controlled multiplexed ring oscillator;

a delta sigma modulator for generating a control signal of the decoder to control a dithering cell of the multiplexed ring oscillator; and

Delta sigma dithering cell-based all-digital multiplying delay locked loop circuit including; a digital loop filter that receives the input clock signal (clk _ref ) and generates a digital loop filter output signal for controlling the decoder and the delta sigma modulator is provided

The method may further include a stochastic phase detector configured to compare phase difference information between the input clock signal clk _ref and the output clock signal clk _out .

The digital loop filter generates a digital loop filter output signal capable of increasing or decreasing a phase of the output clock signal clk _out according to an output signal Up/Dn of the stochastic phase detector, and the digital loop filter The output signal operates as an input signal for controlling the decoder and the delta sigma modulator.

The delta sigma modulator may receive the digital loop filter output signal and generate a control signal of a decoder for controlling a dithering cell of the digitally controlled multiplexed ring oscillator.

The decoder receives the output signal of the digital loop filter and generates a coarse control signal for controlling the coarse delay cell and a fine control signal for controlling the fine delay cell, and the decoder receives the output signal of the delta sigma modulator and may generate a dither control signal for controlling the dithering cell.

selection logic for controlling a multiplexer of the digitally controlled multiplexed ring oscillator ; and a frequency divider that receives the output clock signal clk _out as an input and generates a clock signal having a frequency divided by 1/N.

Among the bits of the digital loop filter output signal, some of the upper bits are controlled to generate a coarse control signal for controlling the coarse delay through a decoder, and the remaining bits of the upper bits are a fine control signal for controlling the fine delay through the decoder. and a least significant bit (LSB) among bits of the digital loop filter output signal is used as an input signal to the delta sigma modulator.

The delta sigma modulator includes an error feedback modulator (EFM) and an error cancellation logic (ECL).

The digitally controlled multiplexed ring oscillator includes: a multiplexer; and a delay line, wherein the delay line may be composed of four delay cells. Among these 4 delay cells, 2 digitally controlled delay cells are included, and the number of delay cells and digital delay cells can be adjusted according to the application.

Each digitally controlled delay cell includes a coarse delay cell, a fine delay cell and a dithering cell, and may be configured as a pseudo-differential inverter structure with a varactor.

The decoder includes a first decoder, a second decoder and a third decoder, wherein the first decoder receives the digital loop filter output signal and generates a course control signal for controlling the course delay of the coarse delay cell, The second decoder receives the digital loop filter output signal and generates a fine control signal for controlling the fine delay of the fine delay cell, and the third decoder receives the delta sigma modulator output signal output from the delta sigma modulator. By receiving the input, a dither control signal for controlling the dithering cell may be generated.

The coarse delay cell reduces a phase error between the input clock signal and the output clock signal to a preset first delay resolution, and the fine delay cell is disposed at a rear end of the coarse delay cell, and the clock signal input from the coarse delay cell and a phase error between the output clock signal and the output clock signal is reduced within a second delay resolution, and the fine delay cell may be configured to have a relatively high delay time resolution compared to the coarse delay cell.

The frequency divider includes a first frequency divider and a second frequency divider, wherein the first frequency divider divides an output clock signal clk _out frequency by 1/2 to output a div ₂ signal, and the second frequency divider may receive a div ₂ signal from the first frequency divider and divide the frequency by 1/128 to output a div ₂₅₆ signal.

The stochastic phase detector may include a plurality of arbiters; and a voting logic unit, wherein the same input signal (clk _ref and clk _out ) is applied to the plurality of arbiters, and the plurality is determined using the output of the voting logic unit to obtain phase error information between the two input signals. can

In the stochastic phase detector, the plurality of arbiters may include three identical first to third arbiters.

Each of the arbiters may include a sense amplifier and a sense amplifier flip-flop including a set reset latch.

According to the present invention, a multiplying delay locked loop circuit (MDLL) can achieve low deterministic jitter (DJ) and high frequency multiplication factor (N) using a novel dithering jitter reduction scheme based on a delta sigma dithering cell, High power efficiency can be achieved.

In addition, the multiplying delay locked loop circuit (MDLL) according to the present invention can reduce static phase offset (SPO) and improve jitter performance by applying a stochastic phase detector.

1 is a functional block diagram of a delta-sigma dithering cell-based all-digital multiplying delay locked loop circuit according to an embodiment of the present invention.
2 is a circuit diagram of a delta-sigma dithering cell-based all-digital multiplying delay locked loop circuit according to an embodiment of the present invention.
3 is a functional block diagram of a digitally controlled delay cell (DCDC) of a multiplexed ring oscillator (MRO).
4 is a circuit diagram of a digitally controlled delay cell (DCDC) of a multiplexed ring oscillator (MRO).
5 is a schematic configuration diagram of a probabilistic phase detector.
FIG. 6 is a circuit diagram of an arbiter of the stochastic phase detector shown in FIG. 5 .
7A and 7B are conceptual diagrams for explaining a dithering jitter reduction method proposed by the present invention.
8A and 8B are simulation results of an all-digital multiplying delay locked loop circuit (N = 256) operated using the dithering jitter reduction scheme according to the present invention.
9A and 9B are Monte-Carlo simulation results of the stochastic phase detector.
10A and 10B are diagrams illustrating simulated output clock jitter of the all-digital multiplying delay locked loop circuit of the prior art and of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a functional block diagram of a delta-sigma dithering cell-based all-digital multiplying delay locked loop circuit according to an embodiment of the present invention.

1, a delta-sigma dithering cell-based all-digital multiplexing delay locked loop circuit according to an embodiment of the present invention is a digitally controlled multiplexed ring oscillator (MRO) 100, a stochastic phase detector (stochastic phase detector) 200, digital loop filter (DLF) (300), decoder (400), delta-sigma modulator (DSM; delta-sigma modulator) (500), selection logic (select logic) ( 600 ) and a frequency divider 700 .

The digitally controlled multiplexed ring oscillator (MRO) 100 receives the input clock signal clk _ref , and corrects a phase error or skew between the input clock signal clk _ref and the output clock signal clk _out . It performs the function of reducing within the preset delay resolution, and at the same time it performs the function of multiplying the frequency of the output clock signal by N times compared to the input clock signal.

The probabilistic phase detector 200 compares the phase difference information between the input clock signal clk _ref and the output clock signal clk _out and operates as a sub-sampling bang-bang phase detector BBPD.

The digital loop filter (DLF) 300 serves as an accumulator, receives the input clock signal clk _ref , and increases by 1 according to the output signal Up/Dn of the stochastic phase detector 200 or Generates a digital loop filter output signal that is reduced. The digital loop filter output signal output from the digital loop filter 300 acts as an input signal for controlling the decoder 400 and the delta sigma modulator (DSM) 500 .

The decoder 400 generates a control signal for controlling the operation of the digitally controlled multiplexed ring oscillator (MRO) 100 . The decoder 400 receives the output signal of the digital loop filter 300 and generates a coarse control signal for controlling the coarse delay cell and a fine control signal for controlling the fine delay cell, and inputs the output signal of the delta sigma modulator. and generates a dither control signal for controlling the dithering cell.

The delta sigma modulator (DSM) 500 receives the output signal of the digital loop filter 300 and generates a control signal of the decoder 400 for controlling the dithering cell of the multiplexed ring oscillator (MRO).

Due to the non-linear nature of the stochastic phase detector 200 and the loop delay of the digital multiplying delay locked loop (MDLL), the output of the digital loop filter (DLF) 300 toggles around the locked position during the limit cycle period. do.

During the toggle, if the multiplexed ring oscillator (MRO) is directly controlled using the digital loop filter (DLF) 300, there is a problem in that the deterministic jitter (DJ) is greatly increased. To solve this, the present invention A dithering jitter reduction scheme is applied that uses the output of a delta sigma modulator (DSM) to control a multiplexed ring oscillator (MRO).

The selection logic 600 controls the multiplexer MUX of the digitally controlled multiplexed ring oscillator MRO, and performs a function of setting an enable period of the stochastic phase detector 200 .

The frequency divider 700 receives the output clock signal clk _out as an input and performs a function of generating a clock signal of a frequency divided by 1/N.

2 is a circuit diagram of a delta-sigma dithering cell-based all-digital multiplying delay locked loop circuit according to an embodiment of the present invention.

Referring to FIG. 2 , the function of each component will be described in more detail.

The digitally controlled multiplexed ring oscillator (MRO) 100 receives the input clock signal clk _ref , and adjusts the phase error between the input clock signal clk _ref and the output clock signal clk _out within a preset delay resolution. It performs a function of reducing, in this case, the frequency of the output clock signal has N times the value of the input clock signal.

A digitally controlled multiplexed ring oscillator (MRO) 100 consists of a multiplexer 110 and a delay line 120 . In this embodiment, a 2-to-1 differential multiplexer (MUX) is used as the multiplexer 110, and a four-stage pseudo-differential delay line (#1) is used as the delay line 120. ~ # 4), that is, the first to fourth digitally controlled delay cells (DCDC) are composed of (120a, 120b, 120c, 120d).

The probabilistic phase detector 200 performs a function of comparing the phase difference information between the input clock signal clk _ref and the output clock signal clk _out , and generates a probabilistic phase detector output signal Up/Dn to generate a digital loop It is input to the filter 300 .

The digital loop filter (DLF) 300 receives the probabilistic phase detector output signal (Up/Dn) generated from the stochastic phase detector 200, and increases or decreases the digital loop filter output signal LF [17] : 0]) is created. In this embodiment, an 18-bit output signal (LF[17:0]) is generated as a digital loop filter output signal.

Some of the upper bits of the output signal bits of the digital loop filter (DLF) 300 are controlled to generate a course control signal for controlling the course delay through the decoder, and the remaining bits of the upper bits are fine delay through the decoder. Controls to generate a controlling fine control signal.

In addition, the least significant bit (LSB) among the output signal bits of the digital loop filter (DLF) 300 is used as an input signal to the delta sigma modulator (DSM) 500, and the output signal of the delta sigma modulator (DSM) is It is input to the decoder and controls the decoder to generate a dither control signal that controls the dithering cell of the multiplexed ring oscillator (MRO).

The decoder 400 receives the digital loop filter output signal from the digital loop filter (DLF) 300 and receives a coarse control signal coarse[14: 0] and a fine control signal fine[62:0] to control the fine delay.

Also, the decoder 400 receives the output signal of the delta sigma modulator (DSM) and generates a dither control signal dither[2:0] for controlling the dithering cell of the multiplexed ring oscillator (MRO).

The decoder 400 includes a first decoder 410 , a second decoder 420 , and a third decoder 430 . In the present embodiment, the first decoder 410 uses a 4-to-15 thermometer decoder, the second decoder 420 uses a 6-to-63 decoder, and the third decoder 430 uses a 2-to-15 thermometer decoder. -3 decoder is used.

In this embodiment, LF[17:14], which is 4 bits among the upper 10 bits of the 18-bit digital loop filter output signal (LF[17:0]) generated by the digital loop filter (DLF) 300, is 4- Input to the two-15 thermometer decoder 410, the 4-to-15 thermometer decoder 410 is a coarse control signal ([14: 0) for controlling the course delay of the multiplexed ring oscillator (MRO) ]) is created.

LF[13:8], which is 6 bits among the upper 10 bits of the 18-bit digital loop filter output signal (LF[17:0]) generated by the digital loop filter (DLF) 300, is a 6-to-63 decoder ( 420), and the 6-to-63 decoder 420 generates a fine control signal ([62: 0]) for controlling the fine delay of the multiplexed ring oscillator (MRO).

The 2-to-3 decoder 430 receives the delta sigma modulator output signal output from the delta sigma modulator (DSM) 500, and in this embodiment, the 2-bit output signal, the multiplexed ring oscillator (MRO) A dither control signal (dither[2: 0]) for controlling the dithering cell is generated.

The delta sigma modulator (DSM) 500 includes an error feedback modulator (EFM) 510 and an error cancellation logic (ECL) 520 , and an error feedback modulator (EFM) 510 . is composed of a first error feedback modulator 511 and a second error feedback modulator 512 .

The delta sigma modulator (DSM) 500 includes a signal (div ₂ ) that is 1/2 of the frequency of the output clock signal (clk _out ) of the digital multiplying delay locked loop circuit, and a digital loop filter (DLF) 300 generated by By receiving the least significant bit (LSB) of the 18-bit digital loop filter output signal (LF [17: 0]) and the 8-bit LF [7: 0], the 2-to-3 decoder 430 operates the multiplexed ring oscillator ( It is controlled to generate a dither control signal (dither[2:0]) that controls the dithering cell of the MRO).

Since the delta sigma modulator (DSM) 500 operates at half the frequency of the output clock signal (clk _out ) of the digital multiplying delay locked loop circuit, the multiplexed ring controlled by the dither control signal ([2:0]) The dithering cell of the oscillator (MRO) operates at a frequency 128 times higher than the operating frequency of the stochastic phase detector 200 . To reduce power consumption, a true single-phase clock (TSPC) flip-flop is used as a register in the delta sigma modulator (DSM).

The frequency divider 700 includes a first frequency divider 710 and a second frequency divider 720 . The first frequency divider 710 divides the frequency of the output clock signal clk _out of the digital multiplying delay fixed loop circuit by 1/2 to output a div ₂ signal.

The second frequency divider 720 receives the div ₂ signal from the first frequency divider 710 and divides the frequency by 1/128 to output a div ₂₅₆ signal.

The selection logic 600 receives the div ₂₅₆ signal from the second frequency divider 720, controls the multiplexer (MUX) 110 of the digitally controlled multiplexed ring oscillator (MRO), and a stochastic phase detector ( 200) to set the enable section.

3 is a functional block diagram of a digitally controlled delay cell (DCDC) of a multiplexed ring oscillator (MRO), and FIG. 4 is a digitally controlled delay cell (DCDC) of a multiplexed ring oscillator (MRO) It is a circuit diagram.

3 and 4, among the first to fourth digitally controlled delay cells (DCDC) 120a, 120b, 120c, and 120d, the second and third digitally controlled delay cells are formed in the same structure, and hereinafter, the 2 The digitally controlled delay cell 120b will be described as an example.

The second digitally controlled delay cell 120b includes a coarse delay cell 121b, a fine delay cell 122b and a dithering cell 123b.

The coarse delay cell generates a relatively large delay time compared to the fine delay cell to have a wide range of operating frequencies. That is, the coarse delay cell functions to reduce the phase error between the input clock signal and the output clock signal to a preset first delay resolution.

The fine delay cell reduces the phase error between the input clock signal and the output clock signal to within the second delay resolution. The fine delay cell is configured to have a relatively high delay time resolution compared to the coarse delay cell.

This digitally controlled delay cell (DCDC) is based on a pseudo-differential inverter structure with a varactor (variable capacitance capacitor). The value of the coarse delay resolution of the multiplexed ring oscillator (MRO), which can be adjusted with the coarse control signal ([14: 0]), and the fine delay resolution using the fine control signal ([62: 0]) are different for each application. can be adjusted accordingly.

The delta sigma modulator (DSM) 500 generates a dither control signal ([2: 0]) that precisely controls the delay of the dithering cell at high frequencies, and the dithering delay resolution becomes the same as the fine delay resolution.

FIG. 5 is a schematic configuration diagram of a stochastic phase detector, and FIG. 6 is a circuit diagram of an arbiter of the stochastic phase detector shown in FIG. 5 .

5 and 6 , the probabilistic phase detector 200 includes an arbiter 210 and a voting logic unit 220 . In this embodiment, the arbiter 210 includes three arbiters, that is, a first arbiter 210a, a second arbiter 210b, and a third arbiter 210c, and the three arbiters are configured by the same arbiter. The three arbiters have the same structure. Hereinafter, the first arbiter 210a will be described as an example.

The first arbiter 210a includes a sense-amplifier (SA) 211a and a sense-amplifier flip-flop (SAFF) including a set-reset (SR) latch 212a. ) is composed of

The sense amplifier (SA) 211a operates only during the high pulse of the sel signal, and by determining which edge of the two input signals (in1, in2) arrives first, the stochastic phase detector 200 is a sub-sampling bang-bang phase detector. (BBPD).

In general, due to a phase detector mismatch due to a process variation, a static phase offset (SPO) occurs, thereby increasing the deterministic jitter (DJ) of the multiplying delay locked loop circuit (MDLL).

In the present invention, a method of reducing deterministic jitter of a far-flying delay locked loop circuit by reducing a phase detector offset is applied using a stochastic approach.

The same input signals clk _ref and clk _out are applied to three identical arbiters, namely the first arbiter 210a, the second arbiter 210b and the third arbiter 210c, and a voting logic 220 ) to determine the majority, it is possible to obtain accurate phase error information between the two input signals.

This multiple voting task involves choosing the median value of the time offset, which makes the properties of the proposed probabilistic phase offset (SPO) closer to the ideal arbiter with reduced static phase offset (SPO).

The stochastic phase detector according to the present invention is designed for a phase detector having a reduced static phase offset (SPO), and has a small area because only a small number of arbiters are used. In addition, each arbiter operates only for a very short cell pulse duration, which has the effect of very low power consumption.

7A and 7B are conceptual diagrams for explaining the dithering jitter reduction method proposed by the present invention, and FIGS. 8A and 8B are all-digital multiplying delay locked loop circuits operated using the dithering jitter reduction method according to the present invention ( N = 256).

As shown in Figure 7a, when the delta sigma modulator (DSM) is turned off, during the limit period (= 2 * T _REF ), the digital code word (DCW) of the multiplexed ring oscillator (MRO) is repeatedly toggled, and the loop The latency is assumed to be zero.

Here, the digital code word (DCW) dithers only one least significant bit (LSB), but misalignment between the clk _ref and clk _out edges affects the multiplexed ring oscillator (MRO) output at each reference clock injection. Expressed as periodic error, it shows that the multiplexed ring oscillator period (T _MRO ) can deviate significantly from the ideal period. This appears as reference spurs in the output spectrum, and the deterministic jitter (DJ) increases significantly, and the deterministic jitter (DJ) increases in proportion to N and the limit cycle interval.

On the other hand, as shown in Fig. 7b, when the delta sigma modulator (DSM) is turned on, the digital code word (DCW) is 128 times higher than the above case (when the DSM is off) due to the operation of the secondary delta sigma modulator (DSM). toggles quickly

A delta sigma modulator (DSM) generates a high-frequency 2-bit pseudo-random output pattern, with an average value equal to the low-frequency 8-bit input LF [7:0]. The multiplexed ring oscillator period (T _MRO ) does not deviate significantly from the ideal value by continuously controlling the dithering cell at high frequencies.

As a result, if the dithering jitter reduction technique proposed in the present invention is implemented, the jitter accumulation time is reduced to 1/128 in proportion to the operating period (T _DSM ) of the delta sigma modulator, and excellent deterministic jitter characteristics even when N is as large as 256. to achieve effectively

8a and 8b show the simulation results of a digital multiplying delay locked loop (MDLL) using the proposed dithering jitter reduction scheme with N = 256 at 2.4 GHz, the digital code word (DCW) is toggled to 3 LSB, It can be seen that the clutter of the output clock signal clk _out is less than about 1.5 ps maximum for a given period.

9A and 9B are Monte-Carlo simulation results of the stochastic phase detector.

9A and 9B , it can be seen that the stochastic phase detector using one arbiter has a standard deviation of 0.295 ps as an input reference time offset due to device mismatch, and the probabilistic phase detector using three arbiters It can be seen that the standard deviation of the phase detector is 0.185 ps.

Therefore, the mismatch-induced time offset of the stochastic phase detector using three arbiters can be reduced by 37.3% compared to the one-arbiter structure.

10A and 10B are diagrams illustrating simulated output clock jitter of the all-digital multiplying delay locked loop circuit of the prior art and of the present invention.

Figures 10a and 10b show the simulated output clock jitter when an all-digital multiplying delay locked loop in accordance with the prior art and the present invention is operated at 2.4 GHz with N = 256, respectively.

Figure 10a shows the jitter values when the delta sigma modulator (DSM) is off and a prior art bang bang phase detector (BBPD) is used, showing a jitter of 39.38 ps p-p (RMS jitter = 10.87 ps).

On the other hand, Figure 10b shows the jitter value when the delta sigma modulator (DSM) of the present invention is turned on and the stochastic phase detector of the present invention is used, and the p-p jitter is only 6.43 ps (RMS jitter = 0.98 ps). It can be seen that 83% or more is reduced compared to the prior art.

What has been described above is only an exemplary embodiment of a delta sigma dithering cell-based all-digital multiplying delay locked loop circuit according to the present invention, and the present invention is not limited to the above-described embodiment, and is claimed in the claims below. As such, without departing from the gist of the present invention, it will be said that the technical spirit of the present invention exists to the extent that various modifications can be made by anyone with ordinary knowledge in the field to which the present invention belongs.

100: digitally controlled multiplexed ring oscillator
200: stochastic phase detector
300: digital loop filter
400 : decoder
500 : Delta Sigma Modulator
600: selection logic
700: frequency divider

Claims (13)

In a delta-sigma dithering cell-based all-digital multiplying delay locked loop circuit,
Receives the input clock signal clk _ref , reduces the phase error between the input clock signal clk _ref and the output clock signal clk _out within a preset delay resolution, and reduces the frequency of the output clock signal by N times the input clock signal digitally controlled multiplexed ring oscillator that multiplies;
a decoder for generating a control signal for controlling the operation of the digitally controlled multiplexed ring oscillator;
a delta sigma modulator for generating a control signal of the decoder to control a dithering cell of the multiplexed ring oscillator;
a digital loop filter receiving the input clock signal clk _ref and generating a digital loop filter output signal for controlling the decoder and the delta sigma modulator; and
a stochastic phase detector that compares the phase difference information between the input clock signal (clk _ref ) and the output clock signal (clk _out );
The probabilistic phase detector includes a plurality of arbiters and voting logic,
The same input signal (clk _ref and clk _out ) is applied to the plurality of arbiters, and the plurality is determined using the output of the voting logic unit to obtain phase error information between the two input signals, wherein the plurality of arbiters are 3 the same first to third arbiters,
Each of the arbiters comprises a sense amplifier and a sense amplifier flip-flop including a set reset latch,
The digital loop filter generates a digital loop filter output signal capable of increasing or decreasing the phase of the output clock signal (clk _out ) according to the output signal (Up/Dn) of the stochastic phase detector,
The digital loop filter output signal operates as an input signal for controlling the decoder and the delta sigma modulator,
The delta sigma modulator receives the digital loop filter output signal and generates a control signal of a decoder for controlling a dithering cell of the digitally controlled multiplexed ring oscillator,
The delta sigma modulator includes an error feedback modulator (EFM) and an error cancellation logic (ECL), wherein the error feedback modulator (EFM) includes a first error feedback modulator and a second error feedback modulator All-digital multiplying delay-locked loop circuit based on sigma dithering cells.
delete delete delete According to claim 1,
The decoder receives the output signal of the digital loop filter and generates a coarse control signal for controlling the coarse delay cell and a fine control signal for controlling the fine delay cell,
The decoder receives the output signal of the delta sigma modulator and generates a dither control signal for controlling the dithering cell.
According to claim 1,
selection logic for controlling a multiplexer of the digitally controlled multiplexed ring oscillator ; and
A delta sigma dithering cell-based all-digital multiplying delay locked loop circuit further comprising a; a frequency divider that receives an output clock signal (clk _out ) as an input and generates a clock signal of a frequency divided by 1/N.
According to claim 1,
Among the bits of the digital loop filter output signal, some of the upper bits are controlled to generate a coarse control signal for controlling the coarse delay through the decoder, and the remaining bits of the upper bits are fine control signals for controlling the fine delay through the decoder control to create
A delta sigma dithering cell-based all-digital multiplying delay locked loop circuit, characterized in that a least significant bit (LSB) among bits of the digital loop filter output signal is used as an input signal to the delta sigma modulator.
delete According to claim 1,
The digitally controlled multiplexed ring oscillator comprises:
multiplexer; and
delay line;
and the delay line includes first to fourth digitally controlled delay cells.
10. The method of claim 9,
Each digitally controlled delay cell is
A delta-sigma dithering cell-based all-digital multiplying delay locked loop circuit comprising a coarse delay cell, a fine delay cell and a dithering cell, and comprising a pseudo-differential inverter structure with a varactor.
11. The method of claim 10,
The decoder comprises a first decoder, a second decoder and a third decoder,
The first decoder receives the digital loop filter output signal and generates a course control signal for controlling the course delay of the coarse delay cell,
The second decoder receives the digital loop filter output signal and generates a fine control signal for controlling the fine delay of the fine delay cell,
The third decoder receives the delta sigma modulator output signal output from the delta sigma modulator, and generates a dither control signal for controlling the dithering cell. .
11. The method of claim 10,
the coarse delay cell reduces the phase error between the input clock signal and the output clock signal to a preset first delay resolution,
The fine delay cell is disposed at the rear end of the coarse delay cell, and reduces the phase error between the clock signal input from the coarse delay cell and the output clock signal within a second delay resolution, and the fine delay cell A delta-sigma dithering cell-based all-digital multiplying delay-locked loop circuit, characterized in that it is configured to have a comparatively high delay time resolution.
7. The method of claim 6,
The frequency divider includes a first frequency divider and a second frequency divider, and the first frequency divider divides an output clock signal (clk _out ) frequency by 1/2 to output a div ₂ signal,
The second frequency divider receives the div ₂ signal from the first frequency divider, divides the frequency by 1/128 and outputs the delta-sigma dithering cell-based all-digital multiplying delay locked loop circuit.

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