KR100705514B1 - Strategy for integer-N frequency Synthesis using Limited Delay Stages - Google Patents

Abstract

 The present invention relates to a DL-based frequency synthesis, and in particular, by passing the input clock through the number of annular variable delays corresponding to a predetermined synthesis coefficient, an output clock having a synthesized frequency that is twice the synthesis coefficient compared to the reference clock is obtained. The present invention relates to a DL-based frequency synthesizing apparatus and method using an annular variable delay device.

The present invention does not have a variable delay stage proportional to the conventional frequency synthesis coefficient N, and can minimize the burden of hardware since the frequency can be synthesized by repeating operation by providing only an even number of unit delay stages in a ring shape. It is a DL-based frequency synthesizing apparatus and method using an annular variable delay. The present invention is a DL-based frequency synthesizer using a method of interpolating using a phase of a clock in a plurality of unit delay stages having a ring-shaped variable delay unit using the same even number of unit delay stages. It has the advantage of jitter compared to the base frequency synthesizer.

Frequency synthesizer, variable delay, synthesis coefficient,

Description

 DL-based frequency synthesizing apparatus and method using cyclic variable delayer {Strategy for integer-N frequency Synthesis using Limited Delay Stages}             

1 shows a conventional DL-based frequency synthesizer,

FIG. 2 is an example of a waveform diagram of synthesizing a desired N times frequency by receiving an output clock of a unit delay stage provided in the phase interpolation unit of FIG.

3 is a configuration diagram of a cyclic variable delay unit in which a plurality of unit delay stages of the present invention are connected;

4 is a view illustrating an external appearance of the unit delay end of FIG.

5 is a detailed circuit diagram and a timing diagram of a unit delay stage used in the annular variable delay device of FIG.

Figure 6 shows the configuration and operation timing diagram of the DL-based frequency synthesizer used in the present invention,

7 is a flowchart illustrating a DL-based frequency synthesizing apparatus using the annular variable delay device of the present invention.

 <Description of Major Symbols in Drawing>

1: variable delay unit 2, 36: unit delay stage

3, 63: phase comparator 64: analog voltage adjuster

5: phase interpolator 30: annular variable delay unit

60: control unit 61: synthesized frequency generator

62: input clock generator

The present invention relates to a DL-based frequency synthesis, and in particular, by passing the input clock through the number of annular variable delays corresponding to a predetermined synthesis coefficient, an output clock having a synthesized frequency that is twice the synthesis coefficient compared to the reference clock is obtained. The present invention relates to a DL-based frequency synthesizing apparatus and method using an annular variable delay device.

The present invention relates to a DL-based frequency synthesizing apparatus and method using an annular variable delay device for synthesizing a desired clock frequency using an input frequency in an electronic device.

In general, PLL (PLL) is a circuit that detects the phase difference between the reference input signal and the oscillating output of the voltage controlled oscillator (VCO) to determine the frequency and phase of the VCO. This circuit is used to create a random frequency oscillating circuit with high stability.

The PL-based synthesizer is mainly used as the frequency synthesizer, and recently, a DL-based frequency synthesizer with excellent jitter characteristics has been tried.

The DL-based frequency synthesizer generates a desired frequency by synthesizing many kinds of phases through a logic processing operation using a clock output from each variable delay stage having a plurality of variable delay stages.

Conventional DL based frequency synthesis will be described in detail with reference to the accompanying drawings.

1 illustrates a conventional DL-based frequency synthesizer, and FIG. 2 illustrates an example of a waveform diagram of synthesizing a desired N-times frequency by receiving an output clock of a unit delay stage provided in the phase interpolator of FIG. 1. will be.

1 shows a DL-based frequency synthesizer.

Referring to the operation when the synthesis coefficient N = 8 in the operation of the general DL-based frequency synthesizer as shown in FIG. 1, the reference clock CKref and the variable delay unit 1 in the phase comparator 3 of FIG. A delayed output clock is input to perform phase comparison.

When the analog voltage Vc is adjusted by the charge pump unit 4 and the adjusted voltage Vc is supplied to the variable delay unit 5 according to the phase comparison result of the phase comparison unit 3, the variable delay unit 1 constitutes the variable delay unit 1. The plurality of unit delay stages 8 are delayed to output pulses, and the output clocks of the last stages are fed back to the phase comparator 3 and supplied, and the phase comparator 3 is then compared in phase. It works.

By repeating this operation, the charge pump section 4 corrects the value of the voltage Vc until the phase of the output clock of the variable delay section 1 is equal to the phase of the reference clock CKref.

When the value of Vc no longer increases or decreases, the phases are coincident and locked.

Meanwhile, as shown in FIG. 2, the phase interpolator 2 receives output clocks from a plurality of unit delay stages and synthesizes desired N times frequencies through logic operations of the 'high' and 'low' portions of the clock. .

The number of stages of the variable delay unit 1 involved in frequency synthesis is determined according to the value of the synthesis coefficient N to be input.

However, in the conventional DL-based frequency synthesizer, the number of the variable delay units 1 must be proportionally provided by the input program N. As the N value increases, the number of the variable delay units 1 increases accordingly. This has an increasing result.

That is, as the number of frequency synthesis coefficients N increases, the number of variable delay units 1 must increase proportionally.

Therefore, there is a problem in that it is expensive and difficult to manufacture a synthetic value N of a large value in reality.

2 shows an example of a waveform diagram of the final synthesized clock NCKin obtained by synthesizing the desired N times the frequency by receiving the output clock of the variable delay unit 1 in the phase interpolation unit 5 of FIG.

The phase interpolator 5 has a duty ratio representing the ratio of 'high' and 'low' of the output clocks of the plurality of unit delay stages Ck1 to Ck8 constituting the variable delay unit 1 exactly. By interpolating to 50% to obtain the synthesized frequency of NCKin, there are various problems that are difficult to implement circuitry in the implementation.

As described above, in the conventional general DL-based frequency synthesizing apparatus, the number of the variable delay units 1 needs to be increased proportionally as the frequency synthesizing coefficient N increases, which causes a high cost of hardware. In addition, the phase interpolator 5 has a problem that it is difficult to accurately interpolate the duty ratio of the high and low of the output clock.

The present invention has been made to solve the above-mentioned problems, and does not have a variable delay stage proportional to the conventional frequency synthesis coefficient N, and only a constant even number of unit delay stages are provided in a ring form to synthesize frequencies in a repeating manner. It is an object of the present invention to provide a DL-based frequency synthesis apparatus and method using a ring-shaped variable delay that can minimize the burden of hardware.

In addition, the present invention provides a DL-based frequency synthesizing apparatus and method using a ring-shaped variable delay that can synthesize the desired frequency irrespective of the duty ratio of the clock generated from a plurality of unit delay stages by applying an appropriate frequency logic operation It aims to do it.

In addition, the present invention uses an even number of unit delay stages that adjust the magnitude of the clock delay by the analog voltage, and if the input clock input to the loop variable delay passes through a constant unit delay stage less than the number of synthesis coefficients N The supply of the clock is cut off and the loop is maintained until the clock of the ring type variable delay unit is circulated and passed through so that the number of unit delay stages becomes the synthesis coefficient N.

When the number of passed unit delay stages reaches the synthesis coefficient N, the output clocks output from the unit delay stages are compared by the input reference clock and the phase comparator, and the analog voltage Vc is adjusted according to the result. The above-described process is repeated in such a manner that the input clock generated by the clock generator is input again to the unit delay stage, and the clocks output from the plurality of unit delay stages are collected to generate the final frequency synthesized output clock. It is an object to provide a synthesis apparatus and method.

In addition, by generating pulses having a period corresponding to the delay magnitude of the clock rising edge with respect to the rising edge of the clock in the unit delay stage, and synthesizing these pulses, the final synthesized output clock generates a plurality of unit delay stages. It is an object of the present invention to provide a DL-based frequency synthesizing apparatus and method using a limited unit delay stage that is independent of the duty ratio of a passing clock.

The DL-based frequency synthesizing apparatus using the limited unit delay stage of the present invention,
A phase comparison unit for comparing and determining a reference clock signal and a clock signal received from the outside; An analog voltage adjuster for adjusting a voltage according to an output signal of the phase comparator; A cyclic variable delay unit configured to delay the input signals by the adjustment voltage of the analog voltage adjusting unit and to connect a plurality of unit delay stages configured to ring with each other by an even number of analog voltages; And a control unit configured to provide a selection signal to the annular variable delay unit and to control an output pulse output from the annular variable delay unit through a frequency synthesizer to a desired synthesis coefficient.

In addition, the cyclic variable delay unit is provided with a plurality of even-numbered unit delay stage, the unit delay stage is characterized in that the start and end connected in a ring, the control unit outputs the output pulse output from the cyclic variable delay unit It further comprises a frequency synthesizer to synthesize.

In addition, the control unit of the present invention, if the frequency synthesis coefficient is greater than the number of unit delay stages provided in the annular variable delay unit by changing the operation signal Si to control to generate the desired output pulse by repeating the annular variable delay unit The control unit may control the unit delay terminal of the annular variable delay unit by selecting a desired unit delay terminal using the operation signal Si.

In addition, the unit delay stage of the present invention operates according to the signal received from the control unit and receives an input clock stage, an output clock receiving stage for receiving the output clock of the previous unit delay stage, and the received analog voltage And a pulse output stage for outputting a pulse by changing the magnitude of the delay according to the change, and an output clock stage for outputting the output clock to the phase comparator by changing the magnitude of the delay according to the change of the analog voltage.

The DL-based frequency synthesizing method using the annular variable delay device according to the present invention comprises a step of inputting an input clock to the annular variable delay unit according to the selection operation signal Si provided by the control unit, and a unit delay in which the input clocks are sequentially connected. 2 steps to pass the stage and stop the provision of the input clock at the point less than the total number of unit delay stages, and to keep the coefficient of the unit delay stage passing through to reach the synthesis coefficient, and the pulse output of the unit delay stage. In step 3 of counting the frequency synthesizer, and when the number of unit delay stages passed by the control unit reaches a synthesis coefficient N, the output clock of the unit delay stage is provided to the phase comparator to compare with the reference clock to determine a mismatch. Four steps of adjusting the supplied analog voltage, and the control unit changes the selection operation signal Si to feed back to the first step Characterized by comprising the 5 steps of generating a species of the frequency synthesizer output clock.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a configuration diagram of a cyclic variable delay unit connecting a plurality of unit delay stages according to the present invention, FIG. 4 is a view illustrating an external shape of the unit delay stage of FIG. 3, and FIG. 5 is used for the cyclic variable delay stage of FIG. 3. 6 is a schematic diagram and a timing diagram of the DL-based frequency synthesizer used in the present invention, and FIG. 7 is a DL-based frequency using the cyclic variable delay device of the present invention. The operation flowchart of the synthesis apparatus is shown.

3 shows an annular variable delay device 30 in which eight unit delay stages 36 are connected in a ring form without distinction between a start stage and a last stage. The operation when the synthesis coefficient N = 8 is described in detail as follows.

In the conventional case, although the unit delay stages are connected in a straight line, the unit delay stages 36 constituting the annular variable delay unit 30 of the present invention are connected evenly, and the unit delay stages are connected to the start and end. The number of 36 can be varied.

The analog variable voltage Vc 31 for adjusting the delay of the unit delay stage 36 to a continuous value is input to the annular variable delay unit 30 of FIG. 3.

The unit delay stage 36 may be designed in such a way that the magnitude of the delay of the unit delay stage 36 decreases as the input analog control voltage Vc 31 increases.

The annular variable delay unit 30 has a delay in which the high voltage region of the input reference clock (CKref) 35 is a signal that is appropriately adjusted so that the high voltage region is not larger than the total delay of the total number of unit delay stages 36. However, an input clock (CKin) 34 is input to the input terminal b of the unit delay stage 36 selected by the Si signal 33 among the plurality of unit delay stages 36, and the unit delay stage 36 selected for the Si signal. Output c is connected to the output clock stage CKout.

The pulse output Pi is output to the pulse output terminals of the plurality of unit delay stages 36. The select signal Si keeps only one signal high.

An output clock and an output waveform can be obtained by arbitrarily selecting a unit delay stage by the Si signal provided from the control unit to the annular variable delay unit 30.

FIG. 4 illustrates the external shape of the unit delay stage of FIG. 3.

Figure 4 is a simplified view of the appearance of the individual unit delay stage 36 constituting the annular variable delay stage 30 of the present invention, the unit delay stage 36 receives an input clock Ckin (node) b) 43, an output clock receiver (node a) 44 for receiving the output clock CKout of the previous unit delay stage, a pulse output stage 45 for outputting a pulse, and an analog regulation voltage stage for inputting an analog control voltage Vc. And an operation signal input terminal 42 for inputting an Si signal for selecting an operation and a desired unit delay stage, and an output clock stage 40 for outputting the output force CKout2 of the unit delay stage 36.

The desired frequency is synthesized by using the output clock CKout and the pulse output Pi of one unit delay stage in a plurality of unit delay stages.

5 is a detailed circuit diagram and timing diagram of the unit delay stage 36 used in the annular variable delay stage 30 of FIG.

According to the Si signal input to the operation signal input terminal 42, CKout, which is the output force of the previous unit delay stage, is input to the output clock receiver stage (node a) 43 of the unit delay stage 36, or the unit delay stage 36 The input clock CKin generated by the clock generator is provided to the input clock stage (node b) 43.

The delayed output clock CKout is output through the c-noord through two delay devices 38 and 39 provided in the unit delay stage 36. Pi in FIG. 4 shows a pulse output and is provided to the synthesized frequency generator.

5 is an example of a timing diagram in which an output pulse Pi having a period corresponding to a delay magnitude of an input clock and an output clock in the detailed view of the unit delay stage 36 is generated.

In FIG. 5, the period of the output pulse Pi changes depending on the magnitude of the analog control voltage Vc.

FIG. 6 shows a configuration diagram when the synthesis coefficient N = 8 as a DL-based frequency synthesizer of the present invention.

The DL-based frequency synthesizer of the present invention is based on the comparison result of the phase comparator 63 and the phase comparator 63 for comparing and determining the reference input clock CKref and the output clock CKout of the annular variable delay unit 30. Vc is adjusted by the analog regulation voltage section 64.

The adjusted voltage Vc is input to the plurality of unit delay stages 36 constituting the annular variable delay unit 30 to correct the period of the output pulse Pi by modifying the magnitude of the delay.

The input clock generator 62 generates an input clock CKin and provides the input clock CKin to the annular variable delay unit 30.

When the synthesis coefficient N is input to the control unit 60, the N value is stored in a register inside the control unit 60. The control unit 60 provides a signal Si for controlling the operation and the unit delay stage to the annular variable delay stage 30.

The initially set Si signal is transmitted to the cyclic variable delay unit 30, and the input clock CKin is input to the selected unit delay terminal to the unit delay stage 36 constituting the cyclic variable delay unit 30. The loop is broken.

Each time the input clock passes through the unit delay stage 36 of CKin, an output pulse Pi is generated, which is summed by the synthesis frequency generator 61 and input to the controller 60.

The output pulse counter existing inside the control unit 60 counts the number of input pulses Pi.

The Si value is reset so that the number of output pulses passes through the unit delay stage 36 corresponding to the number of N just before the programmed number of Pi is reached.

The output clock passing through the N unit delay stages 36 is connected to the output clock CKout through the output node of the unit delay stage selected by the newly set Si.

The newly set Si means passing through the entire unit delay stage 36 constituting the cyclic variable delay unit 30 once, and when the number of the unit delay stages 36 passed is smaller than the programmed number N, The output clock and the output waveform are obtained by repeating the above operation by the number N of the unit delay stages 36 passing through the unit delay stage 36 newly.

The output CKout is applied to the input terminal of the phase comparator 63 to perform phase comparison with the reference clock CKref, thereby correcting the analog voltage Vc.

Since the modified Vc corrects the magnitude of the delay of the plurality of unit delay stages 36 constituting the annular variable delay unit 30, the period of the output pulse Pi is adjusted to obtain the desired clock output waveform and the output clock. do.

In addition, the delay stage input clock CKin is input again to the newly selected unit delay stage, and the above process is repeated.

In the present invention, the output pulse and the output clock are selected by selecting one unit delay stage 36 as the Si signal generated and provided by the control unit from the plurality of unit delay stages 36 constituting the annular variable delay unit 30. You can get it.

6 shows the shape of the waveform of the final synthesized clock NCKref modified as the above process is repeated.

The pulse 70 of the output waveform in the initial state shows the form of the pulse 71 of the second output waveform through the correction process of Vc described above, and when the lock pulse becomes closer to the desired pulse period, the third pulse is obtained. (72) A frequency pulse of N times is output as in the waveform.

7 is a flowchart illustrating a DL-based frequency synthesizing apparatus using the annular variable delay device of the present invention.

The input clock is input to the annular variable delay unit 30 according to the selection operation signal Si provided by the control unit 60 (S80).

The input clock passes through the sequentially connected unit delay stages 36 and stops providing the input clocks at a point less than the total number of unit delay stages, and the coefficients of the unit delay stages 36 through which the input clock passes are combined coefficients. Keep to reach (S81).

The pulse output of the unit delay stage 36 is counted by the frequency synthesizer 61 (S82).

When the number of unit delay stages 36 passes through the synthesis coefficient N, the control unit 60 provides the phase comparator 63 with an output clock of the unit delay stages 36 to compare with the reference clock, and does not match. The power supply Vc supplied to the supplied analog voltage adjusting unit 64 is adjusted (S83 to S84).

The control unit 60 changes the selection operation signal Si and feeds it back to the above step S80 to generate the final frequency synthesized output clock NCKin as shown in the third waveform 72 of FIG. 6 (S85).

As described above, the present invention is to provide 100 unit delay stages in the conventional case, for example, when making a 100M clock using an input frequency of 1M, but the present invention provides a ring-shaped variable that forms 10 unit delay stages. By repeating the delay stage about 10 times, it is possible to generate a 100M clock by comparing the input clock and the output clock, adjusting the Vc, and adjusting the output waveform. Savings.

As described above, the present invention provides a DL-based frequency synthesizing apparatus using a method of interpolating by using a phase of a clock in a plurality of unit delay stages having an annular variable delay unit using an even number of unit delay stages. As a result, the jitter characteristic has an advantage over the Piel-based frequency synthesizer.

In particular, the use of a ring-shaped variable delay unit makes it possible to easily implement any large value of the frequency synthesis coefficient N with a limited number of unit delay stages.

In addition, by generating a pulse of a period corresponding to the delay between the clock rising edge in the unit delay stage, the operation is independent of the duty ratio of the clock passing through the unit delay stage.

Claims (7)

A phase comparison unit for comparing and determining a reference clock signal and a clock signal received from the outside; An analog voltage adjuster for adjusting a voltage according to an output signal of the phase comparator; A cyclic variable delay unit configured to delay the input signals by the adjustment voltage of the analog voltage adjusting unit and to connect a plurality of unit delay stages configured to ring with each other by an even number of analog voltages; The DL using the annular variable delay unit comprising a control unit for providing a selection signal to the annular variable delay unit and controlling the output pulses output from the annular variable delay unit to a desired synthesis coefficient through a frequency synthesizer. Based Frequency Synthesis Device. delete delete The method of claim 1, wherein the control unit controls to repeatedly generate a desired output pulse through the annular variable delay unit by changing the operation signal Si when the frequency synthesis coefficient is greater than the number of unit delay stages provided in the annular variable delay unit. DL-based frequency synthesis apparatus using a ring-shaped variable delay, characterized in that. delete 2. The apparatus of claim 1, wherein the unit delay stage comprises: an input clock stage for operating in response to a signal received from a control unit and receiving an input clock, and an output clock receiving stage for receiving an output clock preceding the unit delay stage; A pulse output stage for outputting a pulse by changing a magnitude of a delay according to a change in an analog voltage received by the unit delay stage; And an output clock stage configured to change an amplitude of the delay according to the change of the analog voltage and output an output clock to the phase comparator. A first step of inputting an input clock to the annular variable delay unit according to the selection operation signal Si provided by the control unit; After the first step, the input clock passes through the sequentially connected unit delay stages and stops the provision of the input clock at a point less than the total number of unit delay stages, and the input clock passes the unit delay stages to reach the synthesis coefficient. Maintaining a second step; Counting, by the frequency synthesizer, the pulse output of the unit delay stage after the second step; After the third step, when the number of unit delay stages passed by the control unit reaches the synthesis coefficient N, the output clock of the unit delay stage is provided to the phase comparator, compared with the reference clock signal, and then the analog voltage supplied is adjusted. Performing a fourth step; After the fourth step, the control unit changes the selection operation signal Si, feeds back to the first step, and generates a final frequency synthesized output clock. Way.

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