CN207732751U - A kind of ultra wide band simulation frequency multiplication excitation system - Google Patents

Abstract

The utility model discloses a kind of ultra wide bands to simulate frequency multiplication excitation system,Including FPGA controller and data processing circuit,The signal end of the FPGA controller is connected with counter by the synchronous circuit that pre-processes,The counter is internally provided with amplification modulate circuit,The signal end of the FPGA controller is also associated with data processing circuit,The data processing circuit includes data register and difference channel,The signal end of the data register is connected with data selector,The signal end of the data selector is connected with difference channel,The signal output end of the data selector is connected with serial-parallel conversion circuit,The signal end interactive connection of the counter has arbitrary modulus frequency divider,The output end of the arbitrary modulus frequency divider is connected by enable signal with FPGA controller,The system locking phase time is short,There is no analogous circuit simultaneously,Non-jitter,Without internal oscillator,The advantages that low in energy consumption,Enhance the precision of frequency multiplication,Expand octave coverage.

Description

A kind of ultra wide band simulation frequency multiplication excitation system

Technical field

The utility model is related to frequency multiplication excitation system field, specially a kind of ultra wide band simulates frequency multiplication excitation system.

Background technology

In recent years, more and more scientific research institutions were dedicated to developing novel frequency multiplication excitation system, no matter were gone back in number It is simulation field, has fine new breakthrough, but there is also following shortcomings inside frequency doubling system：

For example, application No. is 201720426912.4, patent name swashs for a kind of multichannel based on linear frequency modulation system Encourage the utility model patent of source emission system：

MIMO technology and linear frequency modulation continuous wave are combined by it, based on linear frequency modulation wave, pass through transmitted wave body Multi-channel synchronous Detection Techniques are realized in system and the innovative design of driving source, are realized multi channel signals synchronized transmissions and are received, and are Marine echo detection provides a kind of new launch scenario design.

But existing ultra wide band simulation frequency multiplication excitation system has the following defects：

(1) existing frequency multiplication excitation system, using the frequency multiplier circuit based on DPLL, which is system phase locks It is carried out at the same time with clock multiplier, therefore during frequency multiplication, is necessarily restricted by DPLL oneself factors；

(2) most of at present being all based on PHASE-LOCKED LOOP PLL TECHNIQUE exploitation for frequency multiplier circuit, therefore inevitably also can Existing contradiction will be designed in phaselocked loop bring into Multiple frequency design, though the range of system frequency multiplication is very wide, but due to PLL itself The shortcomings of purity of frequency spectrum caused by defect is poor, shake is apparent, noise is big is inevitable.

Invention content

In order to overcome the shortcomings of that prior art, the utility model provide a kind of ultra wide band simulation frequency multiplication excitation system, It can effectively solve the problem that the problem of background technology proposes.

Technical solution adopted by the utility model to solve its technical problems is：

A kind of ultra wide band simulation frequency multiplication excitation system, including FPGA controller and data processing circuit, the FPGA controls The signal end of device is connected with counter by the synchronous circuit that pre-processes, and the counter is internally provided with amplification modulate circuit, The signal end of the FPGA controller is also associated with data processing circuit, and the data processing circuit includes data register and difference The signal end of parallel circuit, the data register is connected with data selector, the signal end and differential electrical of the data selector Road is connected, and the signal end of the difference channel is also associated with Gaussian filter, and the signal output end of the data selector connects It is connected to serial-parallel conversion circuit, the signal output end of the serial-parallel conversion circuit is connected with transcoder, the signal of the counter End interactive connection has arbitrary modulus frequency divider, the output end of the arbitrary modulus frequency divider to pass through enable signal and FPGA controller phase Connection.

Further, the amplification modulate circuit includes signal amplifier, the reverse input end point of the signal amplifier It is not connected with first resistor and 3rd resistor, the other end of the first resistor is directly grounded.

Further, output end of the other end feedback link of the 3rd resistor to signal amplifier.

Further, the in-phase input end of the signal amplifier is connected separately with second resistance and the 4th resistance, described The other end of second resistance is connected with input signal end, and the other end of the 4th resistance is connected with digital analog converter.

Further, the signal output end of the signal amplifier is connected with digital analog converter input terminal.

Compared with prior art, the utility model has the beneficial effects that：

(1) the frequency multiplication excitation system of the utility model, according to the operation thought of FPGA assembly lines, the locking phase time is short, simultaneously Have many advantages, such as no analogous circuit, non-jitter, without internal oscillator, low in energy consumption, enhances the precision of frequency multiplication, expand frequency multiplication model It encloses, in the range of system resource allows, reasonably utilizes the relationship of chip area and speed, with less logic unit, if Count out high speed frequency doubling system；

(2) the frequency multiplication excitation system of the utility model is internally provided with arbitrary modulus frequency divider, is divided and is calculated using arbitrary number Method so that the highest frequency that the frequency range of output signal can be from 0Hz to system clock after frequency multiplication simplifies system clock Frequency dividing problem, and system synchronization procedure and frequency multiplication process are two independent processes, the relations of dependence are not present between each other, therefore Two processes can be done optimization processing respectively.

Description of the drawings

Fig. 1 is the overall structure diagram of the utility model；

Fig. 2 is the amplification modulate circuit figure of the utility model.

Figure label：

1-FPGA controllers；2- synchronizes pretreatment circuit；3- counters；4- amplifies modulate circuit；5- data processing circuits； 6- data registers；7- data selectors；8- serial-parallel conversion circuits；The arbitrary modulus frequency dividers of 9-；10- Gaussian filters；11- difference Circuit；12- transcoders.

Specific implementation mode

The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are without making creative work The every other embodiment obtained, shall fall within the protection scope of the present invention.

As depicted in figs. 1 and 2, the utility model provides a kind of ultra wide band simulation frequency multiplication excitation system, including FPGA controls The signal end of device 1 and data processing circuit 5 processed, the FPGA controller 1 is connected with counter 3 by the synchronous circuit 2 that pre-processes, The counter 3 is internally provided with amplification modulate circuit 4, and the signal end of the FPGA controller 1 is also associated with data processing Circuit 5, the data processing circuit 5 include data register 6 and difference channel 11, and the signal end of the data register 6 connects It is connected to data selector 7, the signal end of the data selector 7 is connected with difference channel 11, the letter of the difference channel 11 Number end is also associated with Gaussian filter 10, and the signal output end of the data selector 7 is connected with serial-parallel conversion circuit 8, described The signal output end of serial-parallel conversion circuit 8 is connected with transcoder 12, and the signal end interactive connection of the counter 3 has arbitrary number The output end of frequency divider 9, the arbitrary modulus frequency divider 9 is connected by enable signal with FPGA controller 1.

In the present embodiment, FPGA controller 1 synchronizes processing to input reference clock (CLK_IN), to input signal into Row replicates so that input signal reaches synchronous (even if signal and input reference clock after replicating with global clock (SYSCLK) There are error, again smaller than one SYSCLK periods of error), then CLK_IN is counted on the basis of SYSCLK, if letter Number CLK_IN shake very little or constant period, then with n (n>1) a period is that unit is counted, if shake is very big, with A cycle is that unit is counted, and sends count value to algoritic module as input, and algoritic module passes through a series of calculations After method flow, an enable signal (/EN) is obtained, finally utilizes the characteristic of settling time (Tsu) and retention time (Th), so that Energy signal/EN is low effectively to be selected to export to SYSCLK, obtains required frequency-doubled signal.

In the present embodiment, 9 inside of arbitrary modulus frequency divider divides algorithm using arbitrary number so that the frequency of output signal after frequency multiplication Rate range can be from 0Hz to system clock highest frequency, simplify the frequency dividing problem of system clock.

The amplification modulate circuit 4 includes signal amplifier S, and the reverse input end of the signal amplifier S is separately connected There are first resistor R1 and the other end of 3rd resistor R3, the first resistor R1 to be directly grounded GND, the 3rd resistor R3's For other end feedback link to the output end of signal amplifier S, the in-phase input end of the signal amplifier S is connected separately with second The other end of resistance R2 and the 4th resistance R4, the second resistance R2 are connected with input signal end Vi, the 4th resistance R4's The other end is connected with the signal output end and digital analog converter DAC input terminal phases of digital analog converter DAC, the signal amplifier S Connection.

In the present embodiment, center bias voltage is adjusted using high precision operating amplifier in 4 inside of amplification modulate circuit Section so that the signal of input signal end Vi draws the refout of A/D chip by second resistance R2 access amplification modulate circuits Foot output 2.5V is connected on resistance R4, and resistance R1, R4 are connected, and using homophase input negative-feedback circuit, has input impedance height, The features such as phase of output signal is constant.

In the present embodiment, local replica clock is, and all with system clock synchronous signals synchronous with system clock It is inevitable synchronous with replica signal, then to the frequency multiplication problem of local replica signal, so that it may to be reduced to the frequency dividing to system clock Problem.

In the present embodiment, locking phase problem is converted into " synchronization " problem to consider, in synchronizing process most by frequency multiplication excitation system Important concept is exactly " reference system ", local to estimate that signal is carried out for reference with input reference clock for phaselocked loop What operation was got, and if using system clock as reference, local replica signal is inevitable synchronouss with system clock, and with input reference The same phase of clock, it is fast that advantage of this is that PGC demodulations, improves chip system speed.

In the present embodiment, the frequency doubling system of design, system synchronization procedure and frequency multiplication process are two independent processes, mutually Between the relations of dependence are not present, therefore two processes can be done optimization processing respectively.

It is obvious to a person skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and And without departing substantially from the spirit or essential attributes of the utility model, it can realize that this practicality is new in other specific forms Type.Therefore, in all respects, the present embodiments are to be considered as illustrative and not restrictive, this practicality is new The range of type is indicated by the appended claims rather than the foregoing description, it is intended that containing in the equivalent requirements of the claims will be fallen All changes in justice and range are embraced therein.Any reference numeral in claim should not be considered as limitation Involved claim.

Claims (5)

1. a kind of ultra wide band simulates frequency multiplication excitation system, including FPGA controller (1) and data processing circuit (5), feature exists In：The signal end of the FPGA controller (1) is connected with counter (3), the counter by the synchronous circuit (2) that pre-processes (3) modulate circuit (4) is amplified in be internally provided with, and the signal end of the FPGA controller (1) is also associated with data processing circuit (5), the data processing circuit (5) includes data register (6) and difference channel (11), the letter of the data register (6) Number end is connected with data selector (7), and the signal end of the data selector (7) is connected with difference channel (11), the difference The signal end of parallel circuit (11) is also associated with Gaussian filter (10), and the signal output end of the data selector (7) is connected with The signal output end of serial-parallel conversion circuit (8), the serial-parallel conversion circuit (8) is connected with transcoder (12), the counter (3) signal end interactive connection has arbitrary modulus frequency divider (9), the output end of the arbitrary modulus frequency divider (9) to pass through enable signal It is connected with FPGA controller (1).

2. a kind of ultra wide band according to claim 1 simulates frequency multiplication excitation system, it is characterised in that：The amplification conditioning electricity Road (4) includes signal amplifier (S), the reverse input end of the signal amplifier (S) be connected separately with first resistor (R1) and The other end of 3rd resistor (R3), the first resistor (R1) is directly grounded (GND).

3. a kind of ultra wide band according to claim 2 simulates frequency multiplication excitation system, it is characterised in that：The 3rd resistor (R3) output end of the other end feedback link to signal amplifier (S).

4. a kind of ultra wide band according to claim 2 simulates frequency multiplication excitation system, it is characterised in that：The signal amplifier (S) in-phase input end is connected separately with second resistance (R2) and the 4th resistance (R4), the other end of the second resistance (R2) It is connected with input signal end (Vi), the other end of the 4th resistance (R4) is connected with digital analog converter (DAC).

5. a kind of ultra wide band according to claim 2 simulates frequency multiplication excitation system, it is characterised in that：The signal amplifier (S) signal output end is connected with digital analog converter (DAC) input terminal.