CN108549205A - Two-step time-to-digital converter based on time amplifier - Google Patents
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Abstract
The invention provides a two-step time-to-digital converter based on a time amplifier, which comprises: the system comprises a first-stage Coarse TDC module, a delay unit, a multiplexer Mux, a time amplifier and a second-stage Fine TDC module; the first-stage Coarse TDC module performs Coarse quantization on two input signals of a start signal and a stop signal; the delay unit is used for delaying the start [ i ] signal and the stop signal and eliminating a time error t between the Mux output signal of the multiplexer and the actual signal; the output end of the delay unit is connected to the multiplexer Mux; the output end of the multiplexer Mux is connected to the time amplifier; and the output end of the time amplifier is connected to the TDC module of the second stage Fine, and the signals passing through the time amplifier are subjected to Fine quantization. The invention greatly reduces the complexity of the circuit and reduces the power consumption.
Description
Technical Field
The invention belongs to the technical field of all-digital phase-locked loops of frequency synthesis, and particularly relates to a two-step time-to-digital converter based on a time amplifier.
Background
The TDC (time to digital converter) performs the function of quantizing the rising edge time interval of the two input signals with a certain time precision. As shown in fig. 1, two paths of input signals are quantized with a rising edge time interval T, and the time interval between two vertical dotted lines is TLSB, which represents quantization precision and is also called resolution, and the smaller TLSB, the higher resolution. In designing the TDC, resolution is the most important design index, and many new structures are designed for the purpose of improving resolution.
The basic method for realizing the TDC is to quantize the time interval by using a gate delay method, wherein the quantization precision is the delay time of a single logic gate. As shown in fig. 2, the start signal of the two input signals enters a delay chain, and the delay unit is formed by a buffer formed by cascading two inverters. Buffer b1 has an input that is a start signal, an output that is connected to buffer b2, and so on. The delayed start signal at each stage is compared in phase with the stop signal, and the phase comparator is usually implemented by a D flip-flop whose output is 1 when the start signal leads the stop signal and becomes 0 when the start signal lags the stop signal. The input end of the D0 flip-flop is connected with a start signal and a stop signal, the clock end of the D1 flip-flop is also connected with the stop signal, and the input end of the D0 flip-flop is connected with a start [1] signal. The position where the output of the D flip-flop changes from 1 to 0 is the position where the phase of the start signal changes from leading to lagging, the output word 1111 … 000 … of the D flip-flop is called thermometer code and is input into a decoder Encoder, and after the code is converted into binary code by the decoder, the time interval value of the input signal can be obtained.
This structure is limited by the delay of the inverter or buffer, which is determined by the fabrication process, so that the overall TDC resolution cannot reach a level lower than the gate delay. To achieve sub-gate delay level resolution, it can be implemented by a two-step TDC based on a time amplifier. The first-stage CTDC (coarse TDC) and the second-stage FTDC (fine TDC) have the same resolution, the time amplifier is used for amplifying the quantization margin of the first-stage CTDC and then sending the amplified quantization margin into the second-stage FTDC for second quantization, so that the resolution of the final TDC is tau/A, wherein t is the resolutions of the CTDC and the FTDC, and A is the TA gain of the time amplifier.
Fig. 3 is a schematic circuit diagram of a two-step TDC based on a time amplifier. The Start signal is input into c1 and D0, the later Start [ i-1] signal input ci is simultaneously input into Di-1, each path of Start signal is also used as the input of a time amplifier TA with the same number, the other input of TA is a stop signal, the outputs Q0 and Q1 … Qi of the D trigger are connected to a decoder to generate a high-order effective bit, the signals are used as the judgment signal of a multiplexer Mux and input into a Transition detector (judgment device), the input of the multiplexer is the output of each time amplifier, the output is connected to FTDC, and the result after second-stage quantization of FTDC enters the decoder to generate a low-order effective bit.
A significant problem with the conventional two-step TDC based on the time amplifier is that the time margin is amplified and then sent to the second FTDC for further quantization after being gated by the multiplexer, which requires a series of time amplifiers to amplify the time margin delayed by each stage of the CTDC. Therefore, if the TDC needs to expand the dynamic range or increase the number of bits of the final output word for improving the resolution, the number of time amplifiers used needs to be increased. The extensive use of time amplifiers results in a large loss of performance, both in terms of circuit complexity and power consumption.
Disclosure of Invention
Technical problem to be solved
In view of the above technical problem, the present invention provides a two-step time-to-digital converter based on a time amplifier.
In the invention, the time margin after the CTDC quantization is extracted through the gating unit, and then is sent to the second-stage FTDC after being amplified by the time amplifier, so that the original use of a series of time amplifiers is improved to use of only one time amplifier, and the complexity of the circuit is greatly reduced. After the number of time amplifiers is reduced, due to the setup and hold time of the D flip-flop and the rise or fall time of the signal from 1 to 0 or from 0 to 1, the MUX will also cause a certain delay, which will cause an error of time length t between the output signal of the final multiplexer and the actual signal in the first pulse, as shown in fig. 4. The value of the error t is equal to the rising and falling time of the D trigger and the delay time of the multiplexer circuit, which causes the output error of the gating unit, so that the output result of the time amplifier is not equal to the amplification result of the time margin of the CTDC, and further causes the final output error of the TDC.
The invention aims to eliminate the error t of the output of the multiplexer and the actual signal caused by using a time amplifier.
(II) technical scheme
According to one aspect of the present invention, there is provided a two-step time-to-digital converter based on a time amplifier, comprising: the system comprises a first-stage Coarse TDC module, a delay unit, a multiplexer Mux, a time amplifier and a second-stage Fine TDC module; wherein,
the first-stage Coarse TDC module performs Coarse quantization on two paths of input signals of a start signal and a stop signal;
the delay unit is used for delaying the start [ i ] signal and the stop signal and eliminating a time error t between the Mux output signal of the multiplexer and the actual signal;
the output end of the delay unit is connected to the multiplexer Mux; the output end of the multiplexer Mux is connected to the time amplifier;
and the output end of the time amplifier is connected to the TDC module of the second stage Fine, and the signals passing through the time amplifier are subjected to Fine quantization.
Preferably, the delay unit comprises i delays; wherein,
each path of start signal of the first-stage Coarse TDC module is provided with a branch, the delayer is positioned on the branch, and each path of start signal is input to the delayer on the corresponding branch.
Preferably, the two-step time-to-digital converter has the following work engineering:
the Start signal is input into c1 and D0 of a first-stage Coarse TDC module, then a Start [ i-1] signal input ci is simultaneously input into Di-1, each path of Start signal is also used as the input of a Delay with the same number in a corresponding branch, the other input of the Delay i is a stop signal, the inputs of D0 and D1 … Di are Start signals with the same number, the stop signal is input at the clk end, each output Q0 and Q1 … Qi is connected to a decoder to generate a high-order effective bit, and simultaneously the high-order effective bit is input into a Transition detector as a judgment signal of a multiplexer Mux, the input of the multiplexer is the output of each Delay, the input of a time amplifier is the output of the multiplexer, the output of the time amplifier is connected to FTDC, and the result enters the decoder to generate a low-order effective bit after second-stage quantization of the FTDC.
Preferably, the delay unit comprises k delays, wherein,
k is larger than or equal to 2, the k delayers are positioned on the original delay chain, no additional branch is added, and the stop signal and each start signal pass through the k delayers.
Preferably, a total of k stages of delay devices are added to the original delay chain, and another k stages of delay devices are also passed before the stop signal is input into the multiplexer Mux.
Preferably, the two-step time-to-digital converter works as follows:
the Start signal is input into c1 and D0, then the Start [ i-1] signal input ci is input into Di-1 at the same time, the input of the D flip-flop is the same Start signal with the same number, the clk end is input into the stop signal, each output Q0 and Q1 … is output to the decoder to generate the high-order effective bit, and simultaneously the signals are input into the Transition detector as the decision signal of the multiplexer Mux, at this time, the inputs of the multiplexer are respectively the stop signal delayed by k stages and the Start [ k ] … Start [ i + k ] signal delayed by k stages, the output is connected to the time amplifier, the output of the time amplifier is connected to FTDC, and the result enters the decoder to generate the low-order effective bit after the second-stage quantization of the FTDC.
(III) advantageous effects
According to the technical scheme, the two-step time-to-digital converter based on the time amplifier has at least one of the following beneficial effects:
(1) the invention changes the original use of a series of time amplifiers into the use of only one time amplifier, and eliminates the error t between the output of the multi-path selector and the actual signal caused by the use of one time amplifier by adding the delay unit, thereby greatly reducing the complexity of the circuit;
(2) the invention reduces the number of the used time amplifiers to one by adding at least two delayers, greatly reduces the complexity of the circuit and reduces the power consumption.
Drawings
Fig. 1 is a schematic diagram of the quantization principle of TDC.
Fig. 2 is a schematic circuit diagram of the TDC.
Fig. 3 is a schematic circuit diagram of a two-step TDC based on a time amplifier.
Fig. 4 is a schematic diagram of the time error of the Mux output signal according to the present invention.
Fig. 5 is a schematic circuit diagram of a two-step TDC based on a time amplifier according to a first embodiment of the present invention.
Fig. 6 is a schematic circuit diagram of a two-step TDC based on a time amplifier according to a second embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.
Certain embodiments of the invention now will be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. Indeed, various embodiments of the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements.
In a first exemplary embodiment of the present invention, a two-step time-to-digital converter based on a time amplifier is provided. Fig. 5 is a schematic circuit diagram of a two-step TDC based on a time amplifier according to a first embodiment of the present invention. As shown in fig. 5, the two-step time-to-digital converter based on the time amplifier of the present invention comprises: the system comprises a first-stage Coarse TDC module, i delayers, a multiplexer Mux, a time amplifier and a second-stage Fine TDC module; wherein,
the first-stage Coarse TDC module performs Coarse quantization on two paths of input signals of a start signal and a stop signal;
the i time delays are used for eliminating the time error t between the output signal of the multiplexer Mux and the actual signal; each path of start signal of the first-stage Coarse TDC module is provided with a branch, the delayer is positioned on the branch, and each path of start signal is input to the delayer on the corresponding branch;
the output ends of the i delayers are connected to the multiplexer Mux; the output end of the multiplexer Mux is connected to the time amplifier;
the output end of the time amplifier is connected to the second-stage Fine TDC module, and the signals passing through the time amplifier are subjected to Fine quantization;
the value of i is related to the number of bits of the output word, for example, i is 32 when the number of bits of the output word is 5 bits.
The working process of the two-step time-to-digital converter based on the time amplifier comprises the following steps:
the Start signal is input into c1 and D0 of a first-stage Coarse TDC module, then a Start [ i-1] signal input ci is simultaneously input into Di-1, each path of Start signal is also used as the input of a Delay with the same number in a corresponding branch, the other input of the Delay i is a stop signal, the inputs of D0 and D1 … Di are Start signals with the same number, the stop signal is input at the clk end, each output Q0 and Q1 … Qi is connected to a decoder to generate a high-order effective bit, and simultaneously the high-order effective bit is input into a Transition detector as a judgment signal of a multiplexer Mux, the input of the multiplexer is the output of each Delay, the input of a time amplifier is the output of the multiplexer, the output of the time amplifier is connected to FTDC, and the result enters the decoder to generate a low-order effective bit after second-stage quantization of the FTDC.
In this embodiment, the error t is eliminated by adding a delay unit. Because the error t is caused because the gating signal leads the decision signal, so that the gating signal is output after the decision signal arrives, and the pulse output by the gating signal is cut off by t. The time delay device on each branch delays the start [ i ] signal and the stop signal, the delay time is ensured to be larger than the sum of the rising and falling time of the D trigger and the delay time of the multiplexer, and the purpose is to lead the gating signal to lag behind the decision signal after the delay, thereby eliminating the output error of the gating signal caused by the late arrival of the decision signal.
In a second exemplary embodiment of the present invention, a two-step time-to-digital converter based on a time amplifier is provided. Fig. 6 is a schematic circuit diagram of a two-step TDC based on a time amplifier according to a second embodiment of the present invention. As shown in fig. 6, compared with the two-step time-to-digital converter based on the time amplifier of the first embodiment, the present embodiment is different in that:
the system comprises k delayers, wherein k is more than or equal to 2, the k delayers are positioned on an original delay chain, no additional branch is added, and a stop signal and each start signal pass through the k delayers.
That is, in this embodiment, i delays before the start [ i ] signal and the stop signal enter the multiplexer Mux are eliminated, but a total k stages of delays are added to the original delay chain, and the k stages of delays are also passed before the stop signal enters the Mux.
In this embodiment, the operation process of the two-step time-to-digital converter based on the time amplifier is as follows:
the Start signal is input into c1 and D0, the subsequent Start [ i-1] signal is input into ci and Di-1 at the same time, the input of the D flip-flop is also the Start signal with the same number, the clk end is input into the stop signal, each output Q0 and Q1 … is output to the decoder to generate a high-order effective bit, and simultaneously the signals are input into the Transition detector as the decision signal of the multiplexer Mux.
The number of the used delayers can be reduced to two at least through the circuit structure, and the original delayers which are added to the branches of each level output of the delay chain are changed into the delayers which are directly added on the original delay chain. Considering that the delayer of the added delay branch is not different from the delayer in the delay chain in nature, the singly added delay branch can be completely omitted, and the gating signal is only required to pass through a section of delay in the delay chain and be gated out. For example, the gating signal is a start [ i ] signal, the gating signal is finally sent to the multi-channel gate to be a start [ i + k ] signal, the stop signal is sent to the multi-channel gate together with the start [ i + k ] signal through k delayers at the same time, and the stop signal enters the second-stage FTDC to further quantize the amplified time margin after being amplified by the time amplifier. The number k of the added delay units is required to satisfy that the delay between the start [1] signal and the start [1+ k ] signal is larger than t. The minimum value of the number of the delays which are theoretically added is 2.
For the purpose of brief description, any technical features that can be applied to the same in the above embodiment 1 are described herein, and the same description need not be repeated.
Up to this point, the present embodiment has been described in detail with reference to the accompanying drawings. From the above description, the two-step time-to-digital converter based on a time amplifier of the present invention should be clearly recognized by those skilled in the art. In the invention, the number of the used time amplifiers is reduced to one at the cost of adding at least two delayers, thereby greatly reducing the complexity of the circuit and reducing the power consumption.
It is to be noted that, in the attached drawings or in the description, the implementation modes not shown or described are all the modes known by the ordinary skilled person in the field of technology, and are not described in detail. Further, the above definitions of the various elements and methods are not limited to the various specific structures, shapes or arrangements of parts mentioned in the examples, which may be easily modified or substituted by those of ordinary skill in the art.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. A two-step time-to-digital converter based on a time amplifier, comprising: the system comprises a first-stage CoarseTDC module, a delay unit, a multiplexer Mux, a time amplifier and a second-stage Fine TDC module; wherein,
the first-stage Coarse TDC module performs Coarse quantization on two paths of input signals of a start signal and a stop signal;
the delay unit is used for delaying the start [ i ] signal and the stop signal and eliminating a time error t between the Mux output signal of the multiplexer and the actual signal;
the output end of the delay unit is connected to the multiplexer Mux; the output end of the multiplexer Mux is connected to the time amplifier;
and the output end of the time amplifier is connected to the TDC module of the second stage Fine, and the signals passing through the time amplifier are subjected to Fine quantization.
2. The two-step time-to-digital converter of claim 1, wherein the delay unit comprises i delays; wherein,
each path of start signal of the first-stage Coarse TDC module is provided with a branch, the delayer is positioned on the branch, and each path of start signal is input to the delayer on the corresponding branch.
3. The two-step time-to-digital converter of claim 2, wherein the two-step time-to-digital converter is engineered to:
the Start signal is input into c1 and D0 of a first-stage Coarse TDC module, then a Start [ i-1] signal input ci is simultaneously input into Di-1, each path of Start signal is also used as the input of a Delay with the same number in a corresponding branch, the other input of the Delay i is a stop signal, the inputs of D0 and D1 … Di are Start signals with the same number, the stop signal is input at the clk end, each output Q0 and Q1 … Qi is connected to a decoder to generate a high-order effective bit, and simultaneously the high-order effective bit is input into a Transition detector as a judgment signal of a multiplexer Mux, the input of the multiplexer is the output of each Delay, the input of a time amplifier is the output of the multiplexer, the output of the time amplifier is connected to FTDC, and the result enters the decoder to generate a low-order effective bit after second-stage quantization of the FTDC.
4. The two-step time-to-digital converter of claim 1, wherein the delay unit comprises k delays, wherein,
k is larger than or equal to 2, the k delayers are positioned on the original delay chain, no additional branch is added, and the stop signal and each start signal pass through the k delayers.
5. A two-step time-to-digital converter as claimed in claim 4, characterized in that a total of k stages of delay are added to the original delay chain, while another k stages of delay are passed before the stop signal is input to the multiplexer Mux.
6. The two-step time-to-digital converter according to claim 5, wherein the two-step time-to-digital converter operates by:
the Start signal is input into c1 and D0, then the Start [ i-1] signal input ci is input into Di-1 at the same time, the input of the D flip-flop is the same Start signal with the same number, the clk end is input into the stop signal, each output Q0 and Q1 … is output to the decoder to generate the high-order effective bit, and simultaneously the signals are input into the Transition detector as the decision signal of the multiplexer Mux, at this time, the inputs of the multiplexer are respectively the stop signal delayed by k stages and the Start [ k ] … Start [ i + k ] signal delayed by k stages, the output is connected to the time amplifier, the output of the time amplifier is connected to FTDC, and the result enters the decoder to generate the low-order effective bit after the second-stage quantization of the FTDC.
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| CN110376872A (en) * | 2019-05-29 | 2019-10-25 | 西安电子科技大学 | A kind of time-to-digit converter applied to TADC based on asynchronous reset |
| CN110824889A (en) * | 2019-11-08 | 2020-02-21 | 中山大学 | Time-to-digital converter based on novel time amplifier |
| CN111025884A (en) * | 2019-12-08 | 2020-04-17 | 复旦大学 | Two-step high-speed dynamic time-to-digital converter |
| CN112506029A (en) * | 2020-12-11 | 2021-03-16 | 重庆邮电大学 | TDC circuit system adopting multiple annular delay chains |
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