CN111131730A - Circuit and method for controlling start time of counter - Google Patents
Circuit and method for controlling start time of counter Download PDFInfo
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- CN111131730A CN111131730A CN201911023026.7A CN201911023026A CN111131730A CN 111131730 A CN111131730 A CN 111131730A CN 201911023026 A CN201911023026 A CN 201911023026A CN 111131730 A CN111131730 A CN 111131730A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/129—Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling ; Out-of-range indication
- H03M1/1295—Clamping, i.e. adjusting the DC level of the input signal to a predetermined value
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
- H03M1/0604—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
- H03M1/0607—Offset or drift compensation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
- H03M1/123—Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
- H03M1/56—Input signal compared with linear ramp
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/63—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to dark current
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/63—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to dark current
- H04N25/633—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to dark current by using optical black pixels
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/745—Circuitry for generating timing or clock signals
Abstract
The invention relates to a circuit and a method for controlling the starting time of a counter. An analog-to-digital conversion (ADC) circuit includes a ramp circuit coupled to output a ramp signal, and the ramp signal is offset from a starting voltage by an offset voltage. The ramp signal ramps up toward the starting voltage. A counter circuit is coupled to the ramp circuit to initiate a count after the ramp signal returns to the starting voltage, and a comparator is coupled to the counter circuit and a bit line to compare the ramp signal to a pixel signal voltage on the bit line. The comparator stops the counter in response to the ramp signal being equal to the pixel signal voltage.
Description
Technical Field
The present invention relates generally to electronic devices and particularly, but not exclusively, to analog-to-digital converters.
Background
Image sensors have become ubiquitous. They are widely used in digital still cameras, cellular phones, surveillance cameras, and also in medical, automotive, and other applications. Many of those applications require High Dynamic Range (HDR) image sensors. The human eye typically possesses a dynamic range of up to about 100 dB. For automotive applications, image sensors with higher than 100dB dynamic range may be necessary to handle different driving conditions, such as driving through dark tunnels into bright sunlight.
When using an image sensor, photo-generated electrons in each of a plurality of pixel cells are transferred from the photodiode to the floating diffusion for subsequent readout. The image signal on the floating diffusion is amplified by a source follower transistor. When the row select transistor is enabled, the amplified image signal is transferred to an output line (referred to as a bit line) of the pixel cell.
The image signals on the bit lines are typically fed into an analog-to-digital converter (ADC) to be converted into digital image signals. Ramp type ADCs are typically used in association with image sensors.
Disclosure of Invention
In one aspect, the present invention provides an analog-to-digital converter (ADC) circuit comprising: a ramp circuit coupled to output a ramp signal, wherein the ramp signal is offset from a starting voltage by an offset voltage, and wherein the ramp signal ramps toward the starting voltage; a counter circuit coupled to the ramp circuit to initiate a count after the ramp signal returns to the starting voltage; and a comparator coupled to the counter circuit and a bit line to compare the ramp signal to a pixel signal voltage on the bit line and to stop the counter in response to the ramp signal being equal to the pixel signal voltage.
In another aspect, the present invention provides an analog-to-digital conversion method, including: shifting the ramp signal from the start voltage by an offset voltage; ramping up the ramp signal toward the starting voltage with a ramp circuit; starting a counter after the ramp signal returns to its starting voltage; comparing the ramp signal to a pixel signal voltage using a comparator coupled to the ramp circuit; and stopping the counter in response to the ramp signal being equal to the pixel signal voltage.
Drawings
Non-limiting and non-exhaustive examples of the present invention are described with reference to the following drawings, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.
FIG. 1 shows two timing diagrams of an analog-to-digital converter according to the teachings of this disclosure.
Figure 2A shows a portion of an analog-to-digital converter circuit that can generate the waveform of figure 1 according to the teachings of this disclosure.
Figure 2B shows a portion of an analog-to-digital converter circuit that can generate the waveform of figure 1, according to the teachings of this disclosure.
Figure 3 depicts a block diagram of an imaging system according to the teachings of this disclosure.
Figure 4 depicts an analog-to-digital conversion method according to the teachings of this disclosure.
Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of various embodiments of the present invention. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present invention.
Detailed Description
Examples of apparatus and methods for controlling counter start times are described herein. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the examples. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.
Reference throughout this specification to "one example" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present invention. Thus, the appearances of the phrases "in one example" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more examples.
Figure 1 shows two timing diagrams for an analog-to-digital converter of a "double ramp" structure (e.g., for correlated double sampling) according to the teachings of this disclosure. Here, the counter starts counting when the ramp signal starts to ramp up (see, e.g., "counter 1"), and the counter stops counting when the ramp signal voltage equals the voltage on the bit line from the image sensor pixel. The power consumed by the counter is roughly proportional to the number of counts produced by the counter. Thus, the less time the counter needs to count, the more power will be saved.
As shown in fig. 1, here, the system adds an offset ("Voffset") on Vramp to cover the non-linearity caused by the delay of the comparator and Vramp. This causes the counter to consume additional power (see, e.g., "counter 1" to start counting at the start of the ramp signal). The number of counts covering the offset voltage with the ramp signal is typically about 300 to 700 counts (depicted here as three counts for simplicity). The ratio of the count output to cover Voffset to the total number of counts is not small compared to the active signal count range 1023 in a 10-bit counter. In an image sensor, there is a counter for each column, and all columns are counted in parallel (see, e.g., fig. 3). The total power consumption of these parallel counters is a significant portion of the total power consumption of the image sensor system. Thus, the system according to the teachings of this disclosure herein eliminates counting due to offset voltage, saving power (see, e.g., "counter 2" only starting counting after Vramp returns to the starting voltage).
According to the teachings of this disclosure, the system starts a counter (see, e.g., "counter 2") at a later time to account for the offset voltage. This saves considerable power. Both the ramp reference signal (Vref) and the ramp image signal ("Vsignal") from the pixel may be delayed by the same amount of time so that the delay counter _ en does not affect the final readout data. Thus, in one example, for a 300DN delayed counter en, the system saves about 1/3 counter power in dark conditions (e.g., when the image sensor is not receiving light).
As mentioned, the power consumption of a counter is almost proportional to its final number of counts. In the dark condition, the power consumption of the image data follows a gaussian (bell-shaped curve-like) distribution. When plotted as a histogram, the output data will have a Median count "Mediandark"(i.e., the value at the center of the bell curve) and a minimum value" Mindark"(i.e., the value at the beginning of the bell curve). Power consumption of counter and MediandarkAnd (4) in proportion. Here, the system starts counting at a later time, so that MindarkIs almost 0. Power consumption of new time sequence and (Median)dark-Mindark) And (4) in proportion. And the average power saving ratio is (Min) compared to the previous timing (e.g., "counter 1")dark)/(Mediandark)。
As an example, when the median is 390 and the minimum is 300, the system here saves 76% of the count power of the first ramp. For an image average of about 512, the system here saves about 300/(390+512) — 33% of the count power for the second ramp. For digital Correlated Double Sampling (CDS) operations, the average power savings for both count reference and count signals is: (300+300)/(390+390+512) ═ 46.4%. Thus, if the digital power is 50% of the total power and the count power is 20% of the digital power, then under dark conditions, the system can save 4.6% of the total power here.
As shown, the techniques disclosed herein may be used in conjunction with correlated double sampling such that the counter later initiates a count for both the black level reference voltage (e.g., "Vref" in fig. 1) and for the image signal voltage indicated in Vpixel (e.g., "Vsignal" in fig. 1). After analog-to-digital conversion, the reference signal may be subtracted from the image signal to generate an image signal that has been corrected for dark current or the like.
Figure 2A shows a portion of an analog-to-digital converter circuit 201A that can generate the waveform of figure 1 according to the teachings of this disclosure. The analog/digital converter circuit 201A includes a first flip-flop 203, a second flip-flop 205, a clocked delay unit 207, an AND gate 209, a counter 211, a comparator 213, AND a ramp circuit 215. The output of the first flip-flop 203 is coupled to the input of the second flip-flop 205, and the output of the second flip-flop 205 is coupled to the input of the clocked delay unit 207. The output of the clocked delay unit 207 is coupled to an AND gate 209. The output of AND gate 209 is coupled to counter 211. The ramp circuit 215 is coupled to a first input of the comparator 213, and a bit line ("Vpixel") is coupled to a second input of the comparator 213. Counter 211 is coupled to receive a reset signal prior to a count event (e.g., prior to the first ramp and the second ramp in fig. 1).
As described, the circuit diagram 201A may generate the count _ en and ramp _ en signals of FIG. 1. The synchronous ramp eni is delayed (using the timing delay unit 207) by a number of system clock cycles defined by the register reg _ dly < k:0>, which may be included in the timing delay unit 207. The system clock sys _ clk is a low frequency clock compared to the count _ clk _ i. The register is adjusted accordingly so that the counter 211 starts later than the time at which the ramp starts. The register values may be determined by chip testing, and the values may be stored in a one-time programmable memory. The number of flip-flops within the timing delay unit 207 is the maximum number of system clock cycles that the counter can be delayed. Longer delays may require many flip-flops.
Figure 2B shows a portion of an analog-to-digital converter circuit 201B that can generate the waveform of figure 1 according to the teachings of this disclosure. As shown, the analog-to-digital converter circuit 201B includes a first flip-flop 203, a second flip-flop 205, an AND gate 209, a counter 211, a comparator 213, a ramp circuit 215, a first divider 217, a second divider 219, a third flip-flop 221, AND a fourth flip-flop 223. The output of the first flip-flop 203 is coupled to the input of the second flip-flop 205, and the output of the second flip-flop 205 is coupled to the input of the third flip-flop 221. First divider 217 and second divider 219 are coupled to inputs of a third flip-flop 221. The output of the third flip-flop 221 is coupled to the input of the fourth flip-flop 223, AND the output of the fourth flip-flop 223 is coupled to the AND gate 209. The output of AND gate 209 is coupled to counter 211. The ramp circuit 215 is coupled to a first input of the comparator 213, and a bit line ("Vpixel") is coupled to a second input of the comparator 213. Counter 211 is coupled to receive a reset signal prior to a count event (e.g., prior to the first ramp and the second ramp in fig. 1).
As shown, instead of using a delay unit (e.g., timing delay unit 207 in fig. 2A), here the system uses dividers (e.g., dividers 217 and 219) for similar functionality, and reduces the number of stages. The system may divide the clock by K11,2,3,4 and K2＝1,2,3,4。K1And K2May be adjusted to delay count clk by the desired clock cycle to save power. The divided clock clk _ dly is used to synchronize ramp _ eni. The fourth flip-flop 223 is clocked clk _ div to have a synchronous count _ clk so that the delay between count _ clk and ramp _ en is well defined. The delay may be (K)1*K2+1)*Tclk。
In one example, instead of using one-time programmable memory to store register values based on chip testing, an on-chip histogram algorithm block may be used to generate a delay (which may be dynamically calculated) for count _ en. Additional optical black rows (including black pixels-e.g., pixels in which light is blocked from reaching the pixel) are used for Black Level Calibration (BLC), and the data of these additional rows is used to determine a minimum count. In some examples, the system may only apply the delay count en for normal BLC and image lines. One benefit of this approach is that count _ en can be dynamically adjusted, but it also consumes additional power.
Figure 3 depicts a block diagram of an imaging system 300 according to the teachings of this disclosure. Imaging system 300 includes pixel array 305, control circuitry 321, readout circuitry 311 (including analog-to-digital converter 317), and functional logic 315. In one example, the pixel array 305 is a two-dimensional (2D) photodiode or image sensor pixel (e.g., pixel P1, P2 …, Pn) array. As illustrated, the photodiodes are arranged to rows (e.g., rows R1-Ry) and columns (e.g., columns C1-Cx) to acquire image data of a person, location, object, etc., which can then be used to render a 2D image of the person, location, object, etc. However, the photodiodes need not be arranged into rows and columns and may take other configurations.
In one example, after each image sensor photodiode/pixel in the pixel array has acquired its image data or image charge, the image data is read out by readout circuitry 311 and then transferred to function logic 315. In various examples, readout circuitry 311 can include amplification circuitry, analog-to-digital conversion 317 circuitry (e.g., analog-to-digital conversion circuitry from fig. 2A, 2B, etc.), and the like. Function logic 315 may simply store the image data or even manipulate the image data by applying post-image effects (e.g., crop, rotate, remove red-eye, adjust brightness, adjust contrast, or otherwise). In one example, readout circuitry 311 may readout a row of image data at a time along readout column lines (illustrated), or may readout the image data using a variety of other techniques (not illustrated), such as serial readout or readout of all pixel cells all in parallel at the same time.
In one example, control circuitry 321 is coupled to pixel array 305 to control the operation of a plurality of photodiodes in pixel array 305. For example, the control circuit 321 may generate a shutter signal for controlling image acquisition. In one example, the shutter signal is a global shutter signal that is used to simultaneously enable all pixel cells within pixel array 305 to simultaneously capture their respective image data during a single acquisition window. In another example, the shutter signal is a rolling shutter signal such that each row, column, or group of pixels is sequentially enabled during successive acquisition windows. In another example, image acquisition is synchronized with lighting effects (e.g., flashes).
As shown, the image sensor may include one or more rows of black pixels (e.g., pixels that are blocked from receiving light by means of a metal shield or the like), and the length of the delay between the start ramp signal and the start counter may be dynamically determined by reading out the black pixel voltage from the one or more black pixels.
In one example, the imaging system 300 may be included in an automobile or the like. In addition, the imaging system 300 may be coupled to other hardware parts, such as a processor (general purpose or otherwise), memory elements, outputs (USB port, wireless transmitter, HDMI port, etc.), lighting/flashing lights, electrical inputs (keyboard, touch display, track pad, mouse, microphone, etc.), and/or a display. Other hardware parts may deliver instructions to the imaging system 300, extract image data from the imaging system 300, or manipulate image data supplied by the imaging system 300.
Figure 4 illustrates an example analog-to-digital conversion method 400 according to the teachings of this disclosure. The order in which some or all of the process blocks appear in method 400 should not be considered limiting. Rather, persons of ordinary skill in the art having benefit of the present disclosure should appreciate that portions of method 400 may be performed in a variety of orders not illustrated, or even in parallel. Moreover, the method 400 may omit certain process blocks in order to avoid obscuring certain aspects. Alternatively, method 400 may include additional process blocks that may not be necessary in some embodiments/examples of the invention.
As shown, the method 400 repeats itself to read out the pixel signal voltage a second time (i.e., to read out the second pixel signal voltage; see, e.g., the second ramp of fig. 1). The second pixel signal voltage is an image signal voltage (e.g., a voltage read out from a pixel that has generated image charges). Stated another way, the second ramp signal (see, e.g., the second ramp signal in fig. 1) may be offset from the starting voltage by an offset voltage, and the second ramp signal may ramp up toward the starting voltage. The counter starts when the second ramp signal returns to the start voltage, and compares the second ramp signal with a second pixel signal voltage (e.g., an image signal voltage) using a comparator. In response to the second ramp signal being equal to the second pixel signal voltage, the counter is stopped.
Once the method 400 repeats itself, the first pixel signal voltage (e.g., the black level reference voltage) may be subtracted from the second pixel signal voltage (e.g., the image signal voltage) to perform black level correction. As shown in fig. 1, the second pixel signal voltage has a greater absolute magnitude than the pixel signal voltage.
The above description of illustrated examples of the invention, including what is described in the abstract of the specification, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific examples of the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.
These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific examples disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
Claims (20)
1. An analog-to-digital converter (ADC) circuit, comprising:
a ramp circuit coupled to output a ramp signal, wherein the ramp signal is offset from a starting voltage by an offset voltage, and wherein the ramp signal ramps toward the starting voltage;
a counter circuit coupled to the ramp circuit to initiate a count after the ramp signal returns to the starting voltage; and
a comparator coupled to the counter circuit and a bit line to compare the ramp signal to a pixel signal voltage on the bit line and to stop the counter in response to the ramp signal being equal to the pixel signal voltage.
2. The ADC circuit of claim 1, wherein the pixel signal voltage is a black level reference voltage.
3. The ADC circuit of claim 2, wherein:
a second ramp signal output from the ramp circuit is offset from the starting voltage by the offset voltage, and wherein the second ramp signal ramps up toward the starting voltage;
the counter circuit initiates counting when the second ramp signal returns to the starting voltage; and is
The comparator compares the second ramp signal to a second pixel signal voltage on the bit line, and in response to the second ramp signal being equal to the second pixel signal voltage, the comparator stops the counter.
4. The ADC circuit of claim 3, wherein the second pixel signal voltage is an image signal voltage, and wherein the second pixel signal voltage has a greater absolute magnitude than the pixel signal voltage and occurs after the pixel signal voltage.
5. The ADC circuit of claim 1, further comprising a circuit coupled to supply a length of delay between initiating the ramp signal and initiating the counter.
6. The ADC circuit of claim 5, wherein the circuit comprises at least one of:
a clock delay unit, wherein the length of the delay is stored in a one-time programmable memory; or
One or more dividers coupled to provide the delay of the length.
7. The ADC circuit of claim 1, wherein the bit lines are coupled to individual pixels in an image sensor.
8. The ADC circuit of claim 1, wherein the image sensor includes one or more black pixels, and wherein a length of a delay between initiating the ramp signal and initiating the counter is dynamically determined by reading out a black pixel voltage from the one or more black pixels.
9. The ADC circuit of claim 8, wherein the black pixel voltage is used to form a histogram of black pixel voltage data, and wherein the histogram of black pixel voltage data is used to dynamically determine the length of the delay.
10. The ADC circuit of claim 1, wherein the ramp signal is substantially linear, wherein there is a non-linear portion at the beginning of the ramp signal, and wherein the offset voltage has a magnitude such that the ramp signal becomes substantially linear before the ramp signal returns to the starting voltage.
11. A method of analog-to-digital conversion, comprising:
shifting the ramp signal from the start voltage by an offset voltage;
ramping up the ramp signal toward the starting voltage with a ramp circuit;
starting a counter after the ramp signal returns to its starting voltage;
comparing the ramp signal to a pixel signal voltage using a comparator coupled to the ramp circuit; and
stopping the counter in response to the ramp signal being equal to the pixel signal voltage.
12. The method of claim 11, wherein the pixel signal voltage is a black level reference voltage.
13. The method of claim 12, further comprising:
offsetting a second ramp signal from the starting voltage by the offset voltage;
ramping up the second ramp signal with the ramp circuit toward the starting voltage;
initiating the counter when the second ramp signal returns to the starting voltage;
comparing the second ramp signal with a second pixel signal voltage using the comparator; and
stopping the counter in response to the second ramp signal being equal to the second pixel signal voltage.
14. The method of claim 13, wherein the second pixel signal voltage is an image signal voltage, wherein the second pixel signal voltage has a greater absolute magnitude than the pixel signal voltage and occurs after the pixel signal voltage.
15. The method of claim 11, further comprising subtracting the pixel signal voltage from the second pixel signal voltage to perform black level correction.
16. The method of claim 11, wherein a length of delay between initiating ramping up the ramp signal and initiating the counter is programmed into a one-time programmable memory.
17. The method of claim 11, wherein a length of a delay between initiating ramping up the ramp signal and initiating the counter is dynamically determined by reading out a black pixel voltage from one or more black pixels.
18. The method of claim 17, wherein the black pixel voltage is used to form a histogram of black pixel voltage data, and wherein the histogram of black pixel voltage data is used to dynamically determine the length of the delay.
19. The method of claim 11, wherein the ramp signal is substantially linear, wherein there is a non-linear portion at the beginning of the ramp signal, and wherein the offset voltage has a magnitude such that the ramp signal becomes substantially linear before the ramp signal returns to the starting voltage.
20. The method of claim 11, wherein the comparator is coupled to a bit line of an image sensor to compare the ramp signal to the pixel signal voltage.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16/175,586 | 2018-10-30 | ||
| US16/175,586 US11128307B2 (en) | 2018-10-30 | 2018-10-30 | Circuit and method for control of counter start time |
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| CN111131730A true CN111131730A (en) | 2020-05-08 |
| CN111131730B CN111131730B (en) | 2022-04-05 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113660438A (en) * | 2020-09-29 | 2021-11-16 | 深圳市汇顶科技股份有限公司 | Image sensor with high resolution analog to digital converter |
| WO2023039841A1 (en) * | 2021-09-17 | 2023-03-23 | 迪克创新科技有限公司 | Analog-to-digital conversion unit, related image sensor, and electronic device |
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Also Published As
| Publication number | Publication date |
|---|---|
| TWI750512B (en) | 2021-12-21 |
| TW202027424A (en) | 2020-07-16 |
| US20200136630A1 (en) | 2020-04-30 |
| US11128307B2 (en) | 2021-09-21 |
| CN111131730B (en) | 2022-04-05 |
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