CN204272278U - For the high speed row level ADC based on TDC of imageing sensor - Google Patents

Abstract

The utility model belongs to analog to digital conversion circuit field, for the CIS of large pel array or high sweep speed, under the condition that little amplitude increases area and power consumption, reduces the change-over time of row level monocline ADC.For this reason, the technical scheme that the utility model is taked is, for the high speed row level ADC based on TDC of imageing sensor, be made up of a phase-locked loop circuit PLL, gate ring oscillator GRO, two inverters, AND circuit, two d type flip flops, counter, delay locked-loop circuit DLL, vernier delay chain VDL and code value arithmetic units.The utility model is mainly used in analog-digital commutator.

Description

For the high speed row level ADC based on TDC of imageing sensor

Technical field

The utility model belongs to electricity field, relates to a kind of analog-to-digital conversion, particularly relates to the realization of a kind of row level ADC applied in the image sensor.Specifically, the high speed row level ADC based on TDC for imageing sensor is related to

Background technology

Along with digital technology, the developing rapidly of semiconductor fabrication, the object that cmos image sensor (CIS) becomes current and future market is paid close attention to.At present, application analog to digital converter (ADC) in cmos image sensors mainly contains three kinds of frameworks: chip-scale, Pixel-level and row walk abreast level.An ADC is used for whole pel array by chip-scale ADC, therefore, necessarily requires ADC to have very high speed, thus reaches a high frame rate.Pixel-level ADC places an ADC in each pixel, thus reaches high frame rate, but this is to consume silicon area and power consumption for cost.Array class ADC is the ADC conversions of each row, thus in power consumption, frame rate, silicon area, fill factor, curve factor, reach a well compromise.Therefore, array class ADC has a wide range of applications in the image sensor.

Because array class framework has the lot of advantages of parallel processing, not high to A/D converter rate request, because this reducing power consumption and the design difficulty of chip, but row level A/D converter is also faced with following challenge:

(1) row level A/D converter is at chip area, especially on col width, is limited to Pixel Dimensions.Therefore, the design of row level ADC must when meeting col width index request, and chip area should be little as much as possible.

(2) not mating and can introduce row level fixed pattern noise between the column and the column in row level A/D converter.Therefore, in order to improve the impact that precision also needs reduction mismatch as far as possible to cause.

In existing row level ADC, common implementation has: successive approximation analog to digital C (SAR ADC), circulation A DC (Cyclic ADC) and monocline ADC (SS ADC).For the CIS of large pel array, often arrange in SAR ADC treatment circuit and all need introducing DAC, so that chip area is larger.Although Cyclic ADC is better than SAR ADC in switching rate and area, often all needs introducing high speed operation amplifier in row change-over circuit, result in the increase of power consumption and row inter-stage mismatch.SS ADC is by sharing ramp generator, and often row only need a comparator and a counter to carry out data processing, therefore simplicity of design, low in energy consumption, often row chip area is little and be easy to realize.In addition, monocline ADC relatively simply guarantees the consistency of row inter-stage, only has comparator to need to compensate, and complete by automatic compensatory technique in circuit.Therefore, monocline ADC is widely used in the CIS of row level framework.

For the analog-to-digital conversion of N position precision, successive approximation analog to digital C and circulation A DC only needs N number of cycle to complete, and monocline ADC needs 2N cycle to complete.Visible, along with the raising of conversion accuracy, change-over time is trend growth exponentially, this greatly limits the read-out speed of cmos image sensor.Therefore, switching rate is improved on the basis of traditional monocline ADC, to be applicable to the CIS of row level framework better, be extremely necessary.

Summary of the invention

For overcoming the deficiencies in the prior art, the utility model is intended to the CIS for large pel array or high sweep speed, under the condition that little amplitude increases area and power consumption, reduces the change-over time of row level monocline ADC.For this reason, the technical scheme that the utility model is taked is, for the high speed row level ADC based on TDC of imageing sensor, be made up of a phase-locked loop circuit PLL, gate ring oscillator GRO, two inverters, AND circuit, two d type flip flops, counter, delay locked-loop circuit DLL, vernier delay chain VDL and code value arithmetic units; Represent the Start signal that time interval Tin starts and be input to gate ring oscillator GRO, the output of gate ring oscillator GRO provides counting clock Clk through the first inverter for counter, represent Stop signal that time interval Tin stops after the second inverter with the Enable Pin representing Start signal that time interval Tin starts and jointly output to through AND circuit counter; Counter outputs to code value arithmetic unit; The D termination power positive pole of first d type flip flop, the Stop representing time interval Tin termination is input to first d type flip flop thus forms the initial signal that will quantize the time interval as VDL at the Q end of this trigger, the Stop representing time interval Tin termination is also input to the D end of second d type flip flop, and the output of gate ring oscillator GRO also outputs to second d type flip flop and forms the termination signal that will quantize the time interval as VDL at the Q end of second d type flip flop; Phase-locked loop circuit PLL outputs to gate ring oscillator GRO; Phase-locked loop circuit PLL also outputs to vernier delay chain VDL by delay locked-loop circuit DLL.

In thin quantification, the structure of VDL is, the delay chain different with two time of delay by several d type flip flop forms, wherein a delay chain adopts voltage control, is carried out the size of stabilisation delay cell delay time by control voltage Vc, and each delay cell correspondence is connected to the D end of Q trigger; The initial signal that VDL will quantize the time interval is connected to the D end of first Q trigger; Another delay chain is then made up of the buffer cell with fixed delay time, and the termination signal that VDL will quantize the time interval is connected to first Q trigger, and buffer cell also correspondence is connected to Q trigger; Article two, be respectively τ s and τ f the time of delay of delay chain, then fixing delay difference △ τ is τ slow-τ fast, is the resolution of TDC.

Compared with the prior art, technical characterstic of the present utility model and effect:

N ranks in grade ADC, and wherein the thick quantization digit of TDC is Nc, and thin quantization digit is Nf.

With the speed ratio of traditional monocline ADC comparatively:

The speed of tradition monocline ADC: 2 ⁿt _cLK

The speed of the ADC that the utility model proposes:

$\mathrm{Tc}=2^{N_c}\·T_{\mathrm{CLK}}+2^{N_f}\·{\mathrm{\τ}}_s=2^{N_c}\·T_{\mathrm{CLK}}+2^{N_f}\·\frac{T_{\mathrm{CLK}}}{2^{N_f}}\·m=(2^{N_c}+m)T_{\mathrm{CLK}}$

Wherein, τ s is the maximum delay time carefully quantizing buffer cell in delay chain, and can be represented as and m is a less positive integer be set.As can be seen here, exponentially promote compared to traditional monocline ADC conversion speed.

Accompanying drawing explanation

The principle assumption diagram of the N bits monocline ADC of Fig. 1 application TDC technology.

The sequential chart of Fig. 2 ATC.

The overall structure figure of Fig. 3 TDC.

The working timing figure of Fig. 4 TDC.

The structure chart of Fig. 5 VDL.

Embodiment

Basic thought of the present utility model utilizes the time to arrive digital translation (TDC) technology, and the conversion process of analog to digital is divided into two parts, and Fig. 1 is integrated stand composition of the present utility model.Part I is the conversion (ATC) of simulation to the time, and be made up of ramp generator and comparator, input analog voltage can be converted to the time quantum of direct proportionality, its sequential as shown in Figure 2.At ramp signal initiating terminal, produce one and start pulse signal Start, the comparator upset when input voltage is equal with ramp signal voltage, obtain a disabling pulse signal Stop, then the time interval Tin quantizing to get is poor by the delay be equivalent between Start and Stop two signal.Part II is then quantized time interval width by TDC, measures the conversion of digital quantity with the deadline.

Fig. 3 shows the overall structure of TDC, is made up of a phase-locked loop circuit (PLL), gate ring oscillator (GRO), two inverters, AND circuit, two d type flip flops, counter, delay locked-loop circuit (DLL), a vernier delay chain (VDL) and code value arithmetic units.Wherein the thick quantification of deadline to digital conversion process be responsible for by gate ring oscillator, and vernier caliper delay line has then been responsible for the thin quantification to balance.Except two input pulse signals, namely represent the Start signal that time interval Tin starts and the Stop signal representing time interval Tin termination, in transfer process, also need generation three control signals: Counter_enable signal, ST1 and ST2 signal.Wherein, Counter_enable signal be by Start and signal carries out the enable control signal of counter produced with operation, what ST1 signal was produced by d type flip flop DFF1 when being the arrival of Stop signal is used as the initial signal that VDL will quantize the time interval, ST2 signal is then that Stop signal and the next rising edge clock after it are produced by d type flip flop DFF2, and is used as the termination signal that VDL will quantize the time interval.

The detailed process that two step TDC quantize is: when Start signal rising edge arrives, trigger gate ring oscillator GRO and start vibration, its output signal through inverter anti-phase after, for counter provides counting clock Clk, Counter_enable signal is driven high simultaneously, and counter starts counting.When Stop signal arrives, first obtained by inverter signal, drags down Counter_enable signal subsequently, makes counter stop thick quantification.Meanwhile, Stop signal is by d type flip flop DFF1, and by the initialize signal ST1 that generation one carefully quantizes, and Stop signal and the next Clk rising edge after it will produce the termination signal ST2 carefully quantized by d type flip flop DFF2.Carrying out in the thin process quantized, two delay lines in VDL carry out delay to ST1 signal and ST2 signal respectively and transmit, and by the sampling of d type flip flop in VDL and detection whether ST1 and ST2 signal overlapped and judge, to obtain thermometer code value " 11 ... 1100 ... 0 ".Then, by the code system change-over circuit of a thermometer-code to binary code, obtain carefully quantizing code value accordingly.Finally, by code value arithmetic unit thick quantized result moved to left 4 and deduct thin quantized result, to complete whole quantizing process.

The time interval between Start and ST2 two signal as shown in Figure 4, is defined as Tc by the work schedule of two step TDC, and the time interval between ST1 and ST2 two signal is defined as Tf.After Tc being completed to thick quantification, then Tf is sent into vernier delay chain to complete meticulous measurement.Then actual input time interval T in=TC-TF.If setting analog-to-digital figure place is N bit, then N=Nc+Nf.Wherein, Nc is the thick figure place quantized, and Nf is the thin figure place quantized.To the numerical expression of time interval Tin quantized result be then:

$T_{\mathrm{in}}=D_c\·T_{\mathrm{CLK}}-D_f\·T_{\mathrm{CLK}}/2^{N_f}$

Wherein, Dc is the thick count results quantized, and Df is that vernier delay chain exports the numeral of the thin quantized result of time interval Tf.By above formula, then complete the whole conversions of time to numeral.

Fig. 5 shows the structure of VDL in thin quantification, and the delay chain different with two time of delay by several d type flip flop forms.Wherein a delay chain adopts voltage control, is carried out the size of stabilisation delay time by control voltage Vc, and adjustable to realize delay, another delay chain is then made up of the buffer cell with fixed delay time.Article two, be respectively τ s and τ f the time of delay of delay chain, then fixing delay difference △ τ is τ slow-τ fast, is the resolution of TDC.Quantize in transfer process thin, keep stable in order to delay difference △ τ fixing in VDL can be made, to ensure high-precision conversion, need the delay line control voltage VC providing to follow technique by delay phase-locked loop DLL, voltage, temperature (PVT) change to carry out accurate control lag difference △ τ, thus reach the effect suppressing PVT.And quantize in transfer process thick, because the method adopting GRO to combine with counter realizes, one is provided to stablize accurate counting clock Clk to enable GRO for counter, then need to be locked by the frequency of oscillation of phase-locked loop pll to GRO, this not only can suppress the impact of PVT change on GRO effectively, and more easily realizes the high-speed transitions of TDC.

For making the purpose of this utility model, technical scheme and advantage more clear, provide the specific descriptions of the utility model execution mode below in conjunction with example.For the row level ADC of 10 precision, its figure place slightly quantized is 6, and the thin figure place quantized is 4.The conversion of whole ADC completes within the time of 0.5us, and conversion speed reaches 2M.After completing the integral reset to circuit, the gatherer process of complete pair signals in 0.1us, resets to the integrating capacitor of ramp generator simultaneously.Thereafter, in 0.4us, two steps of complete pair signals quantize.Slightly quantize in order to 6 can be completed in 0.4us, then should be 6.25ns the cycle of oscillation (i.e. the counted clock cycle TCLK of counter) of GRO.For this reason, for the PLL of employing 6 two-dividers, provide the incoming frequency of 2.5M, thus produce the frequency of oscillation of 160M.When ramp generator produces ramp signal, initial signal Start triggers GRO and starts vibration, and unison counter starts the number of oscillation counting GRO; When comparator produces end signal Stop, by enable control end, make counter stop slightly quantizing, generation is simultaneously thin quantizes commencing signal ST1, at Clk next one clock along producing thin quantification end signal ST2 during arrival.4 carefully quantize to be completed by vernier delay chain, need 16 d type flip flops and 32 delay cells.Because the result of thin measures of quantization is thermometer-code, so need first to be converted into binary code, then combined by code value computing with thick quantized result, to complete whole quantizing process.Final required code value computing is that thick quantized result moves to left 4 and deducts thin quantized result.After this, slope terminates to trigger reset signal, and comparator starts to gather next analog signal.

Claims (2)

1. the high speed row level ADC based on TDC for imageing sensor, it is characterized in that, be made up of a phase-locked loop circuit PLL, gate ring oscillator GRO, two inverters, AND circuit, two d type flip flops, counter, delay locked-loop circuit DLL, vernier delay chain VDL and code value arithmetic units; Represent the Start signal that time interval Tin starts and be input to gate ring oscillator GRO, the output of gate ring oscillator GRO provides counting clock Clk through the first inverter for counter, represent Stop signal that time interval Tin stops after the second inverter with the Enable Pin representing Start signal that time interval Tin starts and jointly output to through AND circuit counter; Counter outputs to code value arithmetic unit; The D termination power positive pole of first d type flip flop, the Stop representing time interval Tin termination is input to first d type flip flop thus forms the initial signal that will quantize the time interval as VDL at the Q end of this trigger, the Stop representing time interval Tin termination is also input to the D end of second d type flip flop, and the output of gate ring oscillator GRO also outputs to second d type flip flop and forms the termination signal that will quantize the time interval as VDL at the Q end of second d type flip flop; Phase-locked loop circuit PLL outputs to gate ring oscillator GRO; Phase-locked loop circuit PLL also outputs to vernier delay chain VDL by delay locked-loop circuit DLL.

2. as claimed in claim 1 for the high speed row level ADC based on TDC of imageing sensor, it is characterized in that, in thin quantification, the structure of VDL is, the delay chain different with two time of delay by several d type flip flop forms, wherein a delay chain adopts voltage control, carried out the size of stabilisation delay cell delay time by control voltage Vc, each delay cell correspondence is connected to the D end of Q trigger; The initial signal that VDL will quantize the time interval is connected to the D end of first Q trigger; Another delay chain is then made up of the buffer cell with fixed delay time, and the termination signal that VDL will quantize the time interval is connected to first Q trigger, and buffer cell also correspondence is connected to Q trigger; Article two, be respectively τ s and τ f the time of delay of delay chain, then fixing delay difference △ τ is τ slow-τ fast, is the resolution of TDC.