CN110109085B - Low-power consumption wide-range array type photon timing reading circuit based on dual-mode switching - Google Patents
Low-power consumption wide-range array type photon timing reading circuit based on dual-mode switching Download PDFInfo
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Abstract
The invention discloses a low-power-consumption wide-range array type photon timing reading circuit based on dual-mode switching. The array pixel units comprise APD detector input ports, AQC interface circuits, array type TDCs and registers. The reading circuit works in a gating frame frequency detection mode, the short-distance detection and the long-distance detection are distinguished by judging the quantization value of the auxiliary pixel TOF of the current frame, and meanwhile, a corresponding control signal is generated to adaptively adjust the data quantization mode of the reading circuit of the next frame. The low-power single photon detection imaging under the wide-range condition can be realized through reasonably switching the reading circuit between different quantization modes.
Description
Technical Field
The invention relates to a low-power-consumption wide-range array type photon timing and reading circuit based on dual-mode switching, and belongs to the technical field of single photon timing and ranging imaging.
Background
A single photon timing ranging imaging technology based on photon flight Time (TOF) measurement is a modern high and new technology integrating light collection, electricity, microelectronics, image processing and computer technology, wherein, an integrated Avalanche Photodiode (APD) detector can sense a single photon and trigger a photocurrent signal, a read-out circuit (ROIC) converts the current signal into a voltage pulse signal, a threshold comparator detects a STOP signal representing the arrival Time of the photon, a Time-to-digital converter (TDC) in each pixel in the ROIC obtains a TOF quantized value of each pixel by combining the START Time of the photon emission, and the TOF quantized values of all the pixels are serially read out to an external computer, and processing the read data by a computer in combination with a related image processing algorithm to finally realize the distance detection and the contour imaging of the detected target. The APD detector working in the Geiger mode has the remarkable characteristics of single photon detection sensitivity, low dark counting rate, short response time, high gain, high signal-to-noise ratio, high stability, wide spectral response range, all-solid-state structure, small volume, light weight, low power consumption and the like, the single photon timing and ranging imaging formed by the method inherits the advantages of high sensitivity, high resolution, high speed, high efficiency and the like, is particularly suitable for weak light intensity detection, and has practical application potential in a plurality of research fields such as night vision systems, laser radar detection, unmanned aerial vehicle monitoring, robot vision and the like. In recent years, research on a novel single photon detector and a corresponding high-performance ROIC system has become a key focus area of many domestic and foreign research institutions and commercial companies.
As a front-end signal detection processing circuit between an APD detector and an image processing system, the ROIC directly determines the performance of the whole single photon timing and ranging imaging system, wherein a TOF (time of flight) measurement technology based on a TDC (time of flight) has the remarkable advantages of strong anti-interference capability, simple time sequence and the like, and has the advantage that an analog-digital converter is not replaceable. In order to cooperate with the normal detection and quenching of APDs in the geiger mode, APDs and their ROICs must work in the gated frame rate detection mode, and a complete gating period (i.e. a complete frame period) can be divided into two phases: the APD is enabled to detect photons within the active window of the gating signal EN, and the acquired TOF quantification is transmitted outside the active window of EN. Under a single-frame quantization mode, usually the effective window of the EN can not exceed the detection range of the TDC in the array pixels at most, the ROIC starts the TDC in each array pixel to count at high frequency in the effective window of the EN while emitting laser, STOPs the TDC quantization in the pixel immediately and latches the TOF quantization value of each pixel after the APD in each pixel detects photons reflected by the measured object and generates a STOP signal, and reads out the latched TOF quantization value outside the effective window of the EN, namely, obtains a complete TOF quantization value which is generated by one-time detection and contains the distance information and the depth-of-field information of the measured object in one frame.
For long-distance detection applications such as laser radar, the ability to capture a dynamic target track in a long distance is required, and the ROIC system is required to realize high-performance imaging of a target with a wide dynamic range. However, under the constraint of a specific time resolution index, the clock period for driving TDC counting in the array pixels is very small, and the ROIC in the single-frame quantization mode can only increase the detection range of the system by increasing the number of bits of the TDC counter in the array pixels, so that a considerable pixel area is consumed, the fill factor of the APD detector is reduced, the overall detection performance of the ROIC is reduced, and the detection range cannot be effectively expanded. In addition, with the increasing requirements for imaging quality, the array scale and imaging speed of the ROIC system are increasing. For the longer time TOF quantization, in the single frame quantization mode, the TDC in each array pixel in the ROIC will be in a high frequency counting state for a long time, and the system power consumption increases sharply. The excessive system power consumption not only seriously affects the detection performance of the APD detector and the reliability of the ROIC operation timing sequence, but also puts higher requirements on the packaging and heat dissipation of a system chip, thereby increasing the cost and the design complexity. It is obvious that too high system power consumption has become a primary limiting factor affecting the expansion of the ROIC system scale, and the continuous expansion of the ROIC array scale strongly depends on reducing the system power consumption of the ROIC. The wide-range low-power-consumption reading circuit system can adaptively and dynamically adjust the quantization mode of the system according to the distance of a measured target in consideration of the effects of reducing the power consumption of the system, saving the chip area, improving the detection performance and the like, and has obvious practical engineering application value.
Disclosure of Invention
In a single-frame quantization mode, ignoring TOF (time of flight) quantization values generated by forced triggering of falling edges of gating signals EN (enhanced signaling), defining the minimum TOF quantization value in all array pixels as a distance TOF value corresponding to the space distance of a measured target, defining the difference value between the TOF quantization value of each array pixel and the minimum TOF quantization value as depth of field TOF values corresponding to different positions of the surface of the measured target, wherein the distance TOF value plus the corresponding depth of field TOF value is a complete TOF value generated by the measured target in one-time detection. For long-distance detection, the distance TOF value is usually much larger than the maximum measurable depth of field TOF value of the detected target, and the common requirements of wide range and high resolution cannot be met in a single-frame quantization mode, so that the system power consumption is huge. In fact, for a photon timing ranging imaging system, only the depth of field TOF value is effective for imaging the profile of a measured target, so that if the distance TOF value with a wide dynamic range is only detected and quantized through one auxiliary pixel unit, and the TDC in the array pixel is only used for detecting the depth of field TOF value with a narrow dynamic range, the synchronous high-frequency counting time of the TDCs in the array pixel is greatly compressed, the quantization bit number can be obviously reduced, and the power consumption introduced by TOF quantization and data transmission is greatly reduced; however, since the accurate distance TOF value is difficult to obtain, the TOF values of all the array pixels need to be tested to obtain (the minimum value), and if the TOF value of one or more pixels is detected only by the auxiliary pixels, the actual size of the distance TOF value cannot be judged. Therefore, a strategy of performing distance TOF value estimation on a measured target and reserving a maximum measurable depth of field TOF value is adopted, a complete TOF value corresponding to each array pixel in a single-frame quantization mode is divided into two frames for quantization, a first frame adopts a middle-low frequency clock to drive a TDC in an auxiliary pixel unit to perform coarse quantization on the spatial distance of the measured target, the range is large but the requirement on time resolution precision is low at the moment, an approximate estimation value of the distance TOF is obtained, and the power consumption caused by the auxiliary pixel work accounts for extremely low proportion of the system power consumption and can be basically ignored; and in the second frame, laser emission is started firstly to enable photons to fly for a period of time in advance, the photon pre-flight time is configured to be slightly shorter than the distance TOF estimated value obtained by TDC quantization in the auxiliary pixel of the first frame under the control of a timing counting unit with a position end, ideally, the photon pre-flight time is the distance TOF estimated value minus the reserved maximum measurable depth of field TOF value, after the photon pre-flight time is finished, a mark signal is output by the timing counting unit to start the TDCs in all array pixels to work simultaneously, and the fine quantization of the depth of field TOF values corresponding to different positions on the surface of the measured object is finished. Meanwhile, in order to correctly quantize the TOF values of the depth of field at different positions of the surface of the measured target, the detection range of the TDC in the array pixel in a high-frequency counting state needs to be larger than the reserved maximum TOF value of the depth of field by more than 2 times, and serious error codes of the TOF quantized values of some array pixels caused by non-ideal factors such as distance TOF estimation, signal transmission delay and the like are avoided. Obviously, by adopting a distance TOF value pre-estimation strategy and reserving a proper maximum measurable field depth TOF value for the measured target, the detection of the distance and the field depth of the measured target can be completed step by step in a time domain, so that the serious opposite restriction of a detection range and time resolution is effectively solved, and the power consumption of an array system is reduced by times.
The invention aims to solve the problem that the detection range of a system cannot be effectively expanded due to array pixel area constraint in the traditional single-frame quantization mode and the problem of high power consumption caused by long-time synchronous high-frequency counting of an array TDC during the subdivision identification detection of a long-distance target by a large-scale array reading circuit under the condition of not influencing the area and time resolution indexes of the array reading circuit. For a long-distance measured target, the reading circuit is configured in a double-frame multiplexing quantization mode, data detected in different modes in two continuous adjacent frames are comprehensively processed, a complete TOF (time of flight) quantization value containing distance information and depth of field information of the measured target generated by one-time detection is obtained, the common requirement between the detection range and the time resolution is met, the chip area is reduced, and the system power consumption is reduced; for a short-distance measured object (with the same magnitude of the maximum measurable depth of field as the measured object), the reading circuit is configured in a single-frame quantization mode, a complete TOF quantization value containing the distance information and the depth of field information of the measured object and generated by one-time detection in one frame is obtained, and meanwhile, a quantization blind area in a double-frame quantization mode is eliminated. In the two quantization modes, the array type TDC in the array pixel works for a short time at the same time, and the system detection and quantization have the characteristic of low power consumption.
In order to achieve the purpose, the invention specifically adopts the following technical scheme:
the low-power consumption wide-range array type photon timing reading circuit based on dual-mode switching comprises a two-dimensional area array formed by a plurality of array pixel units, auxiliary pixel units additionally arranged on the periphery of the area array, a quantization mode configuration module, a time sequence control module and an on-chip clock generation circuit;
the array pixel units comprise APD detector input ports, AQC interface circuits, array type TDC and a register;
the APD detector is used for detecting single photons in an effective window of a gate control signal EN, and the single photon signals which arrive randomly in the window can rapidly trigger APD avalanche in a Geiger mode and generate pulse current signals;
the AQC interface circuit is used for carrying out I-V conversion on avalanche current generated by the APD, generating a voltage pulse signal STOP capable of representing the moment when photons reach the APD, and controlling an MOS (metal oxide semiconductor) switching tube to pull up the anode potential of the APD by using the immediately generated STOP and related signals thereof so as to reduce the reverse bias voltage of the APD, quench the avalanche current and finish single photon detection of a current frame;
the array TDC adopts a counting TDC structure formed by an asynchronous binary counter and a synchronous pseudo-random counter, and is driven by a stable high-frequency counting clock and used for carrying out periodic counting quantization on each array pixel TOF;
the register is used for latching the multi-phase clock state data from the shared phase equalization to realize the subdivision identification effect on TOF of each array pixel, and the complete TOF quantized data latched by each array pixel is read out in a serial mode outside an effective window of a gating signal EN;
the auxiliary pixel units are used for sharing APD detectors and AQC interface circuits in a plurality of array pixel units adjacent to the auxiliary pixel units, no additional APD detector is needed, a counting type TDC structure formed by a binary synchronous addition counter is adopted in the pixels, and the auxiliary pixel TOF is subjected to periodic counting quantization under the drive of a low-frequency clock to obtain an approximate estimated value of a distance TOF corresponding to a measured target space distance;
the quantization mode configuration module is used for adaptively selecting a data quantization mode of a reading circuit of the next frame according to the quantization value of the TOF of the auxiliary pixel of the current frame;
the time sequence control module is used for generating a system time sequence control signal, completing the detection of the TOF quantized value of each pixel and orderly transmitting the TOF quantized value;
and the on-chip clock generating circuit is used for generating clock signals of various frequencies required by the read-out circuit system to normally work.
The low-power consumption wide-range array type photon timing reading circuit based on dual-mode switching comprises the following steps:
Further, as a preferred technical solution of the present invention: the on-chip clock generation circuit selects a closed-loop high-stability multi-phase clock based on a PLL or a DLL to provide various clock signals of high, medium and low frequencies, wherein the clock signals of the medium and low frequencies are used for driving the TDC in the auxiliary pixel unit to count, and meanwhile, the provided high-frequency multi-phase clock has the characteristic of uniform phase splitting and is used for realizing the functions of periodic counting quantization and fine resolution of the TDC in the array pixel.
By adopting the technical scheme, the invention can produce the following technical effects:
firstly, on the premise of not influencing the time resolution performance of a reading circuit system, ultra-wide range detection is realized at the cost of additional hardware resource consumption which is approximately 0, and the theoretical range can be infinitely expanded by increasing the number of counter bits in auxiliary pixels;
the TOF distance of the measured target is independently quantized by the auxiliary pixels, so that the counting bit number of the TDC in the array pixels can be greatly compressed, the area limitation of the array pixels is relieved, the data transmission bit number of the array pixels is also greatly compressed, and the data transmission time and the data transmission power consumption of the reading circuit are greatly reduced;
the range of the TDC in the array pixel is only in the same order of magnitude as the TOF (time of flight) of the maximum measurable depth of field of the measured target, so that during long-distance detection, the power consumption of the system can be further reduced by the double-frame multiplexing quantization mode compared with a classical single-frame quantization mode, and the larger the scale of a reading circuit is, the longer the detection distance is, and the more remarkable the energy consumption reduction benefit brought by the double-frame multiplexing quantization mode is; in addition, based on the quantization mode configuration module, the reading circuit system can adaptively adjust the data quantization mode according to the distance of the detected target, so that the quantization blind area under the double-frame quantization mode is eliminated, and the wide dynamic range detection of the reading circuit system is ensured.
Drawings
Fig. 1 is a schematic diagram of the architecture of a low-power-consumption wide-range array type photon timing readout circuit according to the present invention;
FIG. 2 is a schematic diagram of an APD and AQC interface circuit according to the present invention;
FIG. 3 is a schematic diagram of an arrayed TDC in accordance with the present invention;
FIG. 4 is a schematic diagram of an auxiliary pixel unit according to the present invention;
FIG. 5 is a block diagram of a quantization mode configuration module according to the present invention;
fig. 6 is a schematic diagram of the working timing sequence of the low-power consumption wide-range array type photon timing reading circuit of the present invention.
Detailed Description
Embodiments of the present invention will be further described with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a structure of a dual-mode switching-based low-power consumption wide-range array type photon timing readout circuit, which includes a two-dimensional pixel area array formed by array pixel units, an auxiliary pixel unit added to the periphery of the area array, a quantization mode configuration module, a timing control module, and an on-chip clock generation circuit. The high-frequency multiphase clock can be transmitted to each array pixel unit through the H-tree type driving network, and the quantization error code of the array pixel TOF caused by clock deviation is reduced.
Specifically, the two-dimensional pixel area array comprises M × N array pixel units, and the structure of each array pixel unit is the same. The array pixel units comprise APD detector input ports, AQC interface circuits, array type TDCs and registers; the APD detector is biased in a Geiger mode in an effective window of a gate control signal EN, and a single photon signal randomly arriving in the window can rapidly trigger APD avalanche and generate a pulse current signal; the AQC interface circuit is used for carrying out I-V conversion on avalanche current generated by the APD, generating a voltage pulse signal STOP capable of representing the moment when photons reach the APD, and controlling an MOS (metal oxide semiconductor) switching tube to pull up the anode potential of the APD by using the immediately generated STOP and related signals thereof so as to reduce the reverse bias voltage of the APD, quench the avalanche current and finish single photon detection of a current frame; the array type TDC is driven by a stable high-frequency counting clock and is used for carrying out periodic counting quantification on TOF of each array pixel, meanwhile, a register in the pixel is used for latching multi-phase clock state data from shared phase equalization to realize the subdivision identification effect on the TOF of each array pixel, and the complete TOF quantified data latched by each array pixel is read out in a serial mode outside an effective window of a gating signal EN;
the specific structure of the APD detector and the AQC interface circuit is shown in fig. 2, and includes a reverse bias diode for simulating APD characteristics, NMOS transistors M1-M6, PMOS transistors M7-M12, and an OR gate OR, where M6 and M12 adopt MOS transistors with standard threshold values, and the rest adopt MOS transistors with high voltage standard threshold values. Total parasitic capacitance C at point IN the figure IN The device is composed of two parts: cs is the junction capacitance of APD, Cc is the sum of the parasitic capacitances from point IN to ground, and includes the capacitance of APD anode to ground and the parasitic capacitance generated by the circuit at point IN (the parasitic capacitances of the gate source and drain of each MOS transistor connected to point IN, etc.). In the figure, M7 is a gate control tube, and the gate end is connected with a gate control signal EN to realize the gate control function. M2 is a reset tube, the grid end is connected with an APD reset signal REC, and the APD detector is reset to Geiger mode. The source and drain of M1 are shorted, and the gate terminal is connected with the inverted signal of REC, so as to suppress the clock feed-through effect. M8 is an active quenching tube, and a grid is connected with the output of an OR gate to accelerate the quenching process of the APD detector. The threshold comparator is realized by M3 and M9, the gate is connected with IN, and the size of the flip threshold depends on the width-length ratio of the two tubes. An inverter is formed by M4 and M10, the gate terminal of the inverter is connected with the output STOPb of the detection comparator, on one hand, the signal is shaped to improve the driving capability of the output, on the other hand, the signal is inverted, and a rising edge signal with the same polarity as the IN point is obtained and is used by a subsequent reading circuit system. The input of the OR gate is connected with the STOPb signal and the REC signal for avoiding the competition phenomenon caused by the simultaneous conduction of the quenching tube and the reset tube. M5, M11, M6 and M12 form a level conversion circuit, and output a STOP pulse signal of a standard voltage for a subsequent reading circuit.
As shown in fig. 3, the above-mentioned array TDC adopts a pseudo three-segment structure, in which the high segment adopts a pseudo two-segment counting TDC composed of an asynchronous binary counter and a synchronous pseudo random counter, and is driven by a stable high-frequency counting clock HCK0 to image each arrayThe pixel TOF carries out period counting quantification, simultaneously latches phase state data of four shared uniform split-phase high-frequency clocks HCK 0-HCK 3 at the rising edge of the STOP signal through a register group in the pixel, and can realize T through data reading and decoding HCK0 Temporal resolution of/8, T HCK0 Counting the clock period of the clock signal HCK0 for high frequencies, a fine quantization of each array pixel TOF is achieved. The high-order output of the 2-bit asynchronous binary counter is used as an input clock for driving the synchronous pseudo-random counter to work, and the counting clock frequency of the synchronous pseudo-random counter is reduced, so that the counting power consumption of the array type TDC in the array pixel is effectively reduced. The asynchronous binary counter and the pseudo-random counter are controlled by a Multiplexer (MUX) to complete the switching of two modes of clock counting and data transmission, and the pseudo-random counter can complete the mode switching only by one MUX, so that the pixel area is effectively saved. The Transmission Gate (TG) is used for cutting off the high-frequency counting clock HCK0 to STOP TDC quantization after the rising edge of the STOP signal arrives, the data temporary storage characteristic of the retention time is established through the low TG, and the error rate of data sampling can be effectively reduced through a composite sampling structure formed by matching with the D trigger.
As shown in fig. 4, the additional auxiliary pixel units on the periphery of the area array share the APD detector and the AQC interface circuit in the multiple adjacent array pixel units, the APD detector is not required to be additionally arranged, a counting TDC structure formed by a binary synchronous addition counter is adopted in the pixel, under the drive of a low-medium frequency clock signal LCK, the counter carries out periodic counting quantization on the TOF of the auxiliary pixel in each frame, a distance TOF estimated value corresponding to the space distance of a detected target is obtained, the distance TOF estimated value is respectively locked in a reading register and a setting register, data stored in the reading register is read out outside an effective window of a current frame gating signal EN for subsequent processing, and data stored in the setting register is sent to a quantization mode configuration module at the falling edge of the current frame gating signal EN. The initial phase error control module IN fig. 4 (a) is configured to adjust the rising edge of the LCK _ IN signal to always lag behind the rising edge of EN, and the maximum value of the LCK signal does not exceed 1 cycle of the LCK signal, so as to ensure that the quantization error caused by initial phase mismatch always makes the quantization value of the final auxiliary pixel TOF larger, and facilitate configuring a proper photon pre-flight time IN the dual-frame multiplexing quantization mode.
The quantization mode configuration module is shown in fig. 5, and the operation principle is as follows:
and sampling a comparison result Compare of the multi-bit binary value comparator through a D trigger at the falling edge of the current frame gating signal EN to obtain the quantization mode switching selection Judge. If the comparison result sampled by the multi-bit binary value comparator is high level 1, the next frame readout circuit will be configured in the single frame quantization mode, the next frame gate signal EN and the multi-phase clock signals HCK 0-HCK 3 will be loaded into the array pixel units at the same time, and the quantization value of the array pixel TOF contains the distance information and the depth information of the measured object at the same time. If the comparison result of the multi-bit binary numerical value comparator is sampled to be low level 0, the next frame reading circuit is configured in a double-frame multiplexing quantization mode, when the rising edge of the RESET signal RESET of the next frame comes, a timing subtraction counter with a set end is preset, and the preset value is the distance TOF estimated value stored in a built-in position register of the auxiliary pixel unit of the current frame. Under the drive of the same middle-low frequency clock signal LCK in the auxiliary pixel unit, a timing subtraction counter carries out timing counting in an effective window of a next frame of gating signal EN, a timing value is set to be slightly smaller than a distance TOF estimated value measured by a current frame (about one reserved maximum measurable depth of field TOF value plus one middle-low frequency LCK period), after the timing counting is finished, a FLAG signal FLAG is changed into high level, meanwhile, a gating clock enabling signal EN _ HCK is set to be high level, multiphase clock signals HCK 0-HCK 3 are gated to the array pixel unit, a quantized value of the next frame of array pixel TOF only contains depth of field information of a measured object, and a complete TOF value which contains the distance information and the depth of field information of the measured object and is generated by one-time detection of the measured object can be formed through comprehensive processing with the distance estimated value measured by the TOF auxiliary pixel. In addition, the high level duration of the EN _ HCK signal is controlled not to exceed the detection range of the array type TDC in the array pixel through a flag signal CUT output by a timing addition counter, and the additional power consumption of the TDC in the array pixel due to redundant counting is avoided.
The time sequence control module divides the data transmission time into a plurality of time periods by adopting an asynchronous binary counter timing control method, a plurality of rows of pixels share one serial output port, low-frequency transmission clocks corresponding to the corresponding rows are gated in different time periods, and the pixel data of the corresponding rows are sequentially read out through the shared serial output port based on a multi-path parallel output mode under the driving of the low-frequency transmission clocks.
The on-chip clock generation circuit adopts a closed-loop high-stability multiphase clock based on PLL or DLL to provide various clock signals of high, medium and low frequencies, wherein the LCK is used for driving the TDC in the auxiliary pixel unit to count, and the high-frequency multiphase clocks HCK 0-HCK 3 provided at the same time have the characteristic of uniform phase splitting and are used for realizing the functions of periodic counting quantization and subdivision resolution of the TDC in the array pixel.
Fig. 6 is a schematic diagram of a working timing sequence of the low-power consumption wide-range array type photon timing readout circuit based on dual-mode switching, which can be specifically divided into the following stages:
1) after a reading circuit system is powered on, firstly resetting an on-chip clock generating circuit and a mode switching signal Judge through a RESET _ HCK signal, then loading a low-frequency reference clock signal, after waiting for about 10 mu s of clock locking delay time, resetting other system modules except the on-chip clock generating circuit and an AQC interface circuit through a global RESET signal RESET, after a falling edge of the RESET signal is delayed for a plurality of times, enabling a rising edge of a gating signal EN to arrive and simultaneously emit laser for detection, after a small fixed delay after the rising edge of the EN signal, enabling the rising edge of the REC signal to arrive and RESET the AQC interface circuit to enable an APD detector to work in a Geiger mode, and when the reading circuit system is completely RESET, a first frame of the reading circuit is configured in a double-frame multiplexing quantization mode.
2) After the rising edge of the first frame gate signal EN comes, the low-low frequency counting clock LCK is gated to enter the auxiliary pixel, a binary synchronous addition counter in the auxiliary pixel carries out addition counting in an effective window of the gate signal EN, at the moment, the FLAG signal is at a low level, and high-frequency multiphase clocks HCK 0-HCK 3 input into the array pixel unit are shielded. When the shared APD detector detects photons reflected by a detected target and then quickly induces avalanche current, the AQC interface circuit performs I-V conversion on the avalanche current and outputs a rising pulse signal STOP representing the arrival of the photons, and latches the count values of a binary synchronous addition counter in the auxiliary pixel, wherein the count values are respectively stored in two groups of registers. The count values stored in one group of registers are sent to a multi-bit binary comparator to be compared with a preset threshold value, so as to obtain a comparison result, the count values stored in the other group of registers are sequentially read out outside an effective window of a first frame EN for subsequent processing, and the read count values are converted into time quantum, namely, the time quantum of the TOF quantized value a1 of the auxiliary pixel in the figure.
3) Sampling a comparison result Compare of a multi-bit binary value comparator at a falling edge of a first frame gate control signal EN to obtain a mode control signal Judge for adjusting a detection mode of a next frame reading circuit, judging that a distance TOF estimated value is larger than a threshold value preset artificially when Judge is 0 and is judged to be long-distance detection, arranging the reading circuit in a double-frame multiplexing quantization mode in a second frame, determining a gate clock enable signal EN _ HCK by a FLAG signal output by a timing subtraction counter at a position end of the second frame, after the timing subtraction is finished, changing the FLAG output to a high level, simultaneously sending high-frequency multi-phase clocks HCK 0-HCK 3 into each array pixel, and outputting a quantization value of the array pixel TOF only containing the depth information of the detected object, namely an array pixel TOF quantization value B1 in the figure outside an effective window of the second frame EN. Therefore, in the dual-frame quantization mode, the complete TOF including the distance information and the depth of field information generated by one-time detection of the detected object is A1+ B1-T remain Wherein A1-T remain I.e. the count time of the down counter, T, is timed for the second frame remain For counting the reserved time, at least one reserved maximum measurable depth of field TOF value should be larger.
4) On the contrary, if the sampling Judge is 1 at the EN falling edge of the current frame, that is, it is determined as short-range detection, the readout circuit will be configured in the single-frame quantization mode in the next frame, and will output the array pixel TOF quantized values (such as C1, C2 of the array pixel TOF quantized values in fig. 6) that simultaneously contain the measured object distance information and the depth-of-field signal outside the effective window of EN.
In conclusion, the low-power-consumption wide-range array type photon timing reading circuit based on dual-mode switching can dynamically adjust the data quantization mode according to the distance of the measured target, so that the detection power consumption is obviously reduced. The detection range of the system can be effectively widened by increasing the counting digit of the TDC in the auxiliary pixel unit, and the constraint between the detection range and the pixel area in a single-frame quantization mode is eliminated. The invention is suitable for array reading circuits with any scale, and the larger the array scale is, the farther the detection distance is, and the higher the detection benefit of low power consumption brought by quantization mode switching is.
While the present invention has been described in detail with reference to the embodiments shown in the drawings, it is to be understood that the present invention is not limited to the embodiments, and various changes and modifications may be made without departing from the spirit and scope of the present invention.
Claims (4)
1. A low-power consumption wide-range array type photon timing reading circuit based on dual-mode switching comprises a two-dimensional area array formed by a plurality of array pixel units, an auxiliary pixel unit additionally arranged on the periphery of the area array, a quantization mode configuration module, a time sequence control module and an on-chip clock generation circuit, and is characterized in that:
the array pixel units comprise APD detector input ports, AQC interface circuits, array type TDC and a register;
the APD detector is used for detecting single photons in an effective window of a gate control signal EN, and the single photon signal which arrives randomly in the window can rapidly trigger APD avalanche in a Geiger mode and generate a pulse current signal;
the AQC interface circuit is used for carrying out I-V conversion on avalanche current generated by the APD, generating a voltage pulse signal STOP capable of representing the moment when photons reach the APD, and controlling an MOS (metal oxide semiconductor) switching tube to pull up the anode potential of the APD by using the immediately generated STOP and related signals thereof so as to reduce the reverse bias voltage of the APD, quench the avalanche current and finish single photon detection of a current frame;
the array TDC adopts a counting TDC structure consisting of an asynchronous binary counter and a synchronous pseudo-random counter, and is used for carrying out periodic counting quantization on each array pixel TOF under the driving of a stable high-frequency counting clock;
the register is used for latching the multi-phase clock state data from the shared phase equalization to realize the subdivision identification effect on TOF of each array pixel, and the complete TOF quantized data latched by each array pixel is read out in a serial mode outside an effective window of a gating signal EN;
the auxiliary pixel units are used for sharing APD detectors and AQC interface circuits in a plurality of array pixel units adjacent to the auxiliary pixel units, no additional APD detector is needed, a counting type TDC structure formed by a binary synchronous addition counter is adopted in the pixels, and the auxiliary pixel TOF is subjected to periodic counting quantization under the drive of a low-frequency clock to obtain an approximate estimated value of a distance TOF corresponding to a measured target space distance;
the quantization mode configuration module is used for adaptively selecting a data quantization mode of a next frame reading circuit according to the size of the quantization value of the current frame auxiliary pixel TOF;
the time sequence control module is used for generating a system time sequence control signal, completing the detection of the TOF quantized value of each pixel and orderly transmitting the TOF quantized value;
and the on-chip clock generating circuit is used for generating clock signals of various frequencies required by the read-out circuit system to normally work.
2. The dual-mode switching-based low-power consumption wide-range array type photon timing readout circuit according to claim 1, wherein the working timing sequence mainly comprises the following steps:
step 1, in a first frame after the system is powered on and reset, array pixels do not work, auxiliary pixels work normally, a reading circuit is arranged in a double-frame multiplexing quantization mode, the first frame is used for roughly searching the current distance of a measured target, and an approximate estimation value of the distance TOF of the measured target is a TOF quantization value latched by the auxiliary pixels in an EN effective window;
step 2, comparing the quantization value of the auxiliary pixel TOF in the current frame with a preset threshold value through a multi-bit binary numerical value comparator, wherein the comparison result of the numerical value comparator is used as a selection signal of the quantization mode of the reading circuit of the next frame;
step 3, if the quantization value of the auxiliary pixel TOF in the current frame is smaller than a preset threshold value, the fact that the distance of the measured object is short is confirmed, the next frame reading circuit is configured in a single frame quantization mode, the multiphase clock signal and the gate control signal EN in the single frame quantization mode are loaded into the array pixels at the same time, and the quantization value of each array pixel TOF of each frame contains the distance information and the depth of field information of the measured object;
step 4, if the quantized value of the auxiliary pixel TOF in the current frame is larger than a preset threshold value, confirming that the distance of the measured object is far, and configuring a next frame reading circuit in a double-frame multiplexing quantization mode, wherein the next frame reading circuit is controlled by a timing counting unit with a position end in the mode, so that a multiphase clock signal delay gating signal EN is loaded into the array pixels after delaying for a period of time, the delay size is determined by the quantized value of the auxiliary pixel TOF in the current frame and the preset maximum measurable depth of field TOF value, the quantized value of each frame of array pixel TOF only contains the depth of field information of the measured object, and the distance information of the measured object is obtained by reading and comprehensively processing the quantized value of the auxiliary pixel TOF in the current frame and the quantized value of the array pixel TOF in the next frame;
step 5, the reading circuit reads the quantized value (A) of each frame of auxiliary pixel TOF and the quantized value (B) of all array pixels TOF by adopting a pipeline form of (A1, 0), (A2, B1) and (A3, B2) outside an effective window of each frame of gate control signal EN, and if the current reading circuit works in a double-frame multiplexing quantization mode, the integrated processing is carried out on the A and the B with the same number in two continuous adjacent frames, so that a complete TOF quantized value containing the distance information and the depth of field information of the measured object generated by one-time detection is obtained; on the contrary, if the reading circuit works in a single-frame quantization mode, only the quantization value B of the array pixel TOF is adopted; the pipeline reading mode ensures that the equivalent frame frequency of the work of the reading circuit is approximately unchanged in the double-frame multiplexing quantization mode.
3. The dual-mode switching-based low-power consumption wide-range array type photon timing readout circuit according to claim 2, wherein in the dual-frame multiplexing quantization mode and the single-frame quantization mode, the array type TDC works for a short time at the same time, and the system detection quantization has low power consumption.
4. The array type photon timing and reading circuit with low power consumption and wide range based on dual-mode switching as claimed in claim 1, wherein the on-chip clock generation circuit selects a closed loop high stable multiphase clock based on PLL or DLL to provide various clock signals of high, medium and low frequencies, wherein the medium and low frequency clock signals are used for driving the TDC counting operation in the auxiliary pixel unit, and the provided high frequency multiphase clock has the characteristic of uniform phase splitting and is used for realizing the functions of cycle counting quantization and subdivision discrimination of the TDC in the array pixel.
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