CN210155522U - Pixel-level high-precision amplitude-time conversion circuit - Google Patents
Pixel-level high-precision amplitude-time conversion circuit Download PDFInfo
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- CN210155522U CN210155522U CN201921250881.7U CN201921250881U CN210155522U CN 210155522 U CN210155522 U CN 210155522U CN 201921250881 U CN201921250881 U CN 201921250881U CN 210155522 U CN210155522 U CN 210155522U
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Abstract
The utility model discloses a high accuracy range time conversion circuit of pixel level. The utility model discloses realize a high accuracy range time conversion circuit of pixel level, read out an amplitude time conversion circuit of circuit inside every pixel promptly, consequently, in a survey, all pixels all can give different echo signal's intensity information. The utility model discloses an amplitude-time conversion circuit receives clock frequency's restriction less, has greatly improved conversion accuracy, and the voltage that represents echo signal intensity directly exports with digital format, need not on-chip ADC and carries out 2 quantizations, has reduced the degree of difficulty of system on chip design.
Description
Technical Field
The utility model relates to a high accuracy range time conversion circuit belongs to circuit technical field.
Background
The laser radar is an active detection technology which can accurately and quickly acquire three-dimensional space information of the ground or the atmosphere, can be used for distance measurement, angle measurement and the like, and is widely applied to the fields of military and civil use. Imaging lidar is classified into various modes of operation, such as scanning imaging with a cell or line detector and non-scanning imaging with an array detector. The scanning imaging action distance of the unit or line array detector can be far, but the imaging speed is limited to a certain extent; the imaging speed of the array detector is very high, the defects of large scanning volume, heavy mass and poor reliability are overcome, the array detector plays a crucial role in the application of space target relative navigation with high requirements on real-time performance and volume, and the array detector is a key point and a hotspot of research in many countries at present.
The APD array has the characteristics of full solid-state structure, high quantum efficiency and the like, and can keep good signal-to-noise ratio under high gain. The laser three-dimensional imaging radar based on the APD array adopts laser to carry out flood irradiation on a target scene, and a three-dimensional image of a target can be obtained by one-time laser pulse. When the bias voltage of the APD is lower than its avalanche voltage, it acts as a linear amplification of incident light electrons, and this operating state is called linear mode. In the linear mode, the higher the reverse voltage, the greater the gain. The linear APD amplifies the input photoelectrons with equal gain to form a continuous current, and obtains a laser continuous echo signal with time information and intensity information.
The linear APD detector of the large area array needs to be matched with a large area array laser radar reading circuit, and the current domestic laser radar reading circuit is mainly a discrete device or a small area array, so that the resolution and the imaging rate are lower. When the APD scale reaches 64 x 64 pixels or even larger, the laser radar reading circuit can only be realized by adopting a single-chip integration method. The large-area array laser radar reading circuit chip is realized based on a standard CMOS process, the size of a control system can be reduced, the weight is reduced, the power consumption is reduced, the anti-interference capability is improved, the reliability is improved, and high-precision time resolution is obtained while the target high-frame frequency is captured.
The current large-area array three-dimensional imaging laser reading circuit is limited by the area of a pixel, and generally has only a timing and ranging function, namely, a high-precision time-digital conversion circuit is integrated in each pixel, so that only the time information of an echo signal can be extracted. For extracting the strength information of the echo signal, the circuit can only adopt one ADC shared by each column or a plurality of columns, the amplitude of the corresponding pixel is selected through the row/column control signal, and the ADC conversion is carried out on the amplitude information of each pixel one by one. This approach severely limits the operating frequency of the readout circuit, which in turn limits the imaging speed of the linear APD detector.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve the technical problem that overcome prior art's defect, provide a high accuracy range time conversion circuit of pixel level, can realize having integrateed a range time conversion circuit in reading out the inside every pixel of circuit, consequently, in a survey, make all pixels all can give the digital intensity information of quantization of high accuracy of different echo signal.
In order to solve the technical problem, the utility model discloses a technical scheme as follows:
a pixel-level high-precision amplitude-time conversion circuit is characterized by comprising a plurality of D triggers, a latch unit, a 2-to-1 multiplexer, a comparator, a gate circuit and a capacitor;
the inverting input end of the comparator is connected with the peak-hold voltage, and the non-inverting input end of the comparator is connected with a detection port for charging and discharging of the capacitor;
the output signals of the first D flip-flop and the comparator generate a Control signal Control through a gate circuit, and the Control signal Control is used for controlling the states of other D flip-flops in an amplitude conversion period or a data reading period;
the N D triggers are sequentially connected to form a trigger group, and the output end of the previous trigger is connected with the input end of the next trigger; during amplitude conversion: the group of flip-flops serves as a counter; during data read-out, the flip-flop group functions as a shift register;
the rest D triggers are connected with the trigger group in sequence and used as a memory for storing the phase state of each clock signal during amplitude conversion; as a shift register during data readout;
the latch unit is used for latching the phase state of the clock signal and storing the latch signal into the rest D triggers;
the Control Start signal Start controls the capacitor to charge or discharge, and the 2-to-1 multiplexer is controlled to select and transmit the corresponding path of data according to the amplitude conversion period or the data reading period according to different generated Control signals Control.
Further, a control Start signal Start is input to the gate of the MOS switch tube, and the MOS switch tube is controlled to control the constant current source I to charge or discharge the capacitor.
Further, when the control Start signal Start controls the gate voltage of the MOS switch tube to be high, the capacitor C discharges;
when the control Start signal Start controls the gate voltage of the MOS switch tube to be low, the capacitor C is charged.
Further, the clock signal comprises a reference clock signal and a plurality of clock signals formed by delaying through a plurality of delay units.
Further, the two paths of data transmitted by the 2-to-1 multiplexer comprise data of a previous image element and output data of a four-input exclusive-nor gate circuit.
Further, the output signal of the comparator is subjected to phase comparison with the output signal of the first D flip-flop after passing through the NOT gate, and then a Control signal Control is generated.
Further, when the Control signal Control =0, the data read-out period is entered;
when the Control signal Control is 1, the amplitude conversion period is entered.
The utility model discloses the beneficial effect who reaches:
the utility model realizes a pixel-level high-precision amplitude-time conversion circuit, namely, an amplitude-time conversion circuit is integrated in each pixel inside the reading circuit, so that all pixels can give out the intensity information of different echo signals; and simultaneously, the utility model discloses an amplitude-time conversion circuit receives clock frequency's restriction less, has greatly improved the conversion precision. The voltage representing the strength of the echo signal is directly output in a digital format, and 2-time quantization of an on-chip ADC is not needed, so that the difficulty of on-chip system design is reduced.
Drawings
Fig. 1 is a high-precision amplitude-time conversion circuit at a pixel level.
Detailed Description
The present invention will be further described with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
As shown in fig. 1, the conversion circuit in this embodiment includes 16D flip-flops 1D to 16D, LATCH units LATCH1 to LATCH4, DELAY units DELAY1 to DELAY3, 1-out-of-2 circuit, a comparator com, a gate circuit, a MOS switch transistor M0, a constant current source I, a capacitor C, and the like.
The external signals of the circuit are a control Start signal Start, a peak hold voltage VR, and a clock signal CLK.
D flip-flops 1D-16D are 16 same falling edge triggered D flip-flops.
D flip-flops 1D-12D form a flip-flop group, the D flip-flops are connected in sequence, the output end of the previous flip-flop is connected with the input end of the next flip-flop, and the clocks of all the flip-flops are clock signals ck 1. During amplitude conversion: the trigger group is used as a counter; during data read-out, the flip-flop group is used as a shift register.
The clock signal of the three D flip-flops 13D-15D is ck 1. During amplitude conversion: the 13D-15D triggers are used as memories; in the data read period, 13D to 15D are used as shift registers.
In other embodiments, the number of D flip-flops may be other numbers, mainly according to the clock period and the signal size.
The D flip-flop 16D generates a Control signal Control through a gate circuit together with a Control Start signal Start and a comparator com. The output signal of the comparator com passes through the NOT gate and then is compared with the output signal phase of the D flip-flop 16D to output a Control signal Control.
When the Control signal Control =1, the circuit is in the amplitude conversion period;
when the Control signal Control changes from 1 to 0, the circuit enters a data read period.
The clock signal CLK can be latched by a LATCH unit LATCH1, and the phase state of the latched clock signal ck1 is stored in the D flip-flop 13D; the clock signal CLK2 is obtained by a delay unit dead 1, and can be latched by a LATCH unit LATCH2, and the latched phase state signal ck2 is stored in the D flip-flop 14D; the clock signal CLK3 is the clock signal CLK2 obtained through a delay unit DELY 2; the clock signal CLK4 is a clock signal CLK3 obtained through a delay unit deal 3, and the clock signal CLK3 and the clock signal CLK4 are latched by a LATCH unit LATCH3 and LATCH4, respectively, and the latched phase state signals are output through an exclusive nor gate and stored in the D flip-flop 15D.
The LATCH unit LATCH is used to LATCH the states of the clock signals CLK, CLK2, CLK3, and CLK 4.
The Control signal Control is 1, the 1-from-2 circuit selects an A end, and the A end is connected with the output of the four-input XNOR gate circuit; the Control signal Control is equal to 0, and the 2-out-of-1 circuit selects the terminal B. The principle of the 2-to-1 circuit, namely the two-way selection circuit, is to transmit data at the A end or transmit data at the B end under the action of a control signal. The data at the B end is the data of the previous pixel, and the data at the A end is the output of a four-input exclusive-nor gate circuit.
The inverting input end of the comparator com is connected with the peak-hold voltage VR, and the non-inverting input end of the comparator com is a detection port VC for charging and discharging the capacitor C by the constant current source I.
The MOS switch tube M0 controls the capacitor C to charge or discharge, and when the control Start signal Start controls the grid voltage of the MOS switch tube M0 to be high, the capacitor C performs a discharging operation; when the control Start signal Start controls the gate voltage of the MOS switch transistor M0 to be low, the capacitor C performs a charging operation.
The working principle is as follows:
the linear APD photosensitive chip converts the received laser narrow pulse echo signal into a current signal, and the current signal is converted into a voltage signal with a certain amplitude through a trans-impedance amplifier, wherein the voltage signal represents the intensity of the laser echo signal; the peak-hold circuit holds the voltage signal as the peak-hold voltage VR. The utility model discloses an amplitude-time conversion circuit carries out digital quantization to peak protection voltage VR, and the convenience is integrated in order to realize the fast transmission with echo signal's time information.
First each D flip-flop clears 0. After the control Start signal Start is changed from high to low, the amplitude-time transition of the present invention is started.
The constant current source I charges the capacitor C, and the voltage of the detection port VC is gradually increased from 0. Meanwhile, the trigger group is used as an integer counter, and the D triggers 13D-15D are used as precise counters until the voltage VC of the detection port is greater than the peak-to-average voltage VR. The Control start signal Control is set to 0 by 1, the circuit of 1 in 2 selects the end B, under the effect of the falling edge of the next clock signal CLK, the peak-to-hold voltage VR representing the echo intensity is read out from the D flip-flops 1D-15D in sequence at the falling edges of 15 clock signals ck1, and therefore the voltage conversion and the data output of the pixels are in seamless connection.
When the voltage VC of the detection port is less than the peak holding voltage VR, the LATCH units LATCH 1-LATCH 4 are not latched; when the voltage VC > the peak hold voltage VR at the detection port, the LATCH units LATCH1 to LATCH4 LATCH the phase states of the clock signals CLK, CLK2, CLK3, and CLK4 at that time, and the states are latched into the D flip-flops 13D to 15D to be stored.
The counting accuracy of the precision counter can be adjusted according to the DELAY unit DELAY. The number of the clock signals and the number of the latch units are cooperatively arranged according to the number of the delay units.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be considered as the protection scope of the present invention.
Claims (7)
1. A pixel-level high-precision amplitude-time conversion circuit is characterized by comprising a plurality of D triggers, a latch unit, a 2-to-1 multiplexer, a comparator, a gate circuit and a capacitor;
the inverting input end of the comparator is connected with the peak-hold voltage, and the non-inverting input end of the comparator is connected with a detection port for charging and discharging of the capacitor;
the output signals of the first D flip-flop and the comparator generate a Control signal Control through a gate circuit, and the Control signal Control is used for controlling the states of other D flip-flops in an amplitude conversion period or a data reading period;
the N D triggers are sequentially connected to form a trigger group, and the output end of the previous trigger is connected with the input end of the next trigger; during amplitude conversion: the group of flip-flops serves as a counter; during data read-out, the flip-flop group functions as a shift register;
the rest D triggers are connected with the trigger group in sequence and used as a memory for storing the phase state of each clock signal during amplitude conversion; as a shift register during data readout;
the latch unit is used for latching the phase state of the clock signal and storing the latch signal into the rest D triggers;
the Control Start signal Start controls the capacitor to charge or discharge, and the 2-to-1 multiplexer is controlled to select and transmit the corresponding path of data according to the amplitude conversion period or the data reading period according to different generated Control signals Control.
2. The pixel-level high-precision amplitude-time conversion circuit according to claim 1, wherein a control Start signal Start is input to a gate of the MOS switch tube, and the MOS switch tube is controlled to control the constant current source I to charge or discharge the capacitor.
3. The pixel-level high-precision amplitude-time conversion circuit according to claim 1, wherein when the control Start signal Start controls the gate voltage of the MOS switch transistor to be high, the capacitor C discharges;
when the control Start signal Start controls the gate voltage of the MOS switch tube to be low, the capacitor C is charged.
4. A pixel-level high-precision amplitude-time conversion circuit according to claim 1, wherein the clock signal comprises a reference clock signal and a plurality of clock signals formed by delaying through a plurality of delay units.
5. A pixel-level high-precision amplitude-time conversion circuit according to claim 1, wherein the two paths of data transmitted by the 2-to-1 multiplexer include data of a previous pixel and output data of a four-input exclusive-nor circuit.
6. A pixel-level high-precision amplitude-time conversion circuit as claimed in claim 1, wherein the output signal of the comparator is inverted with the output signal of the first D flip-flop to generate the Control signal Control.
7. A pixel-level high-precision amplitude-time conversion circuit according to claim 1, wherein when the Control signal Control =0, a data readout period is entered;
when the Control signal Control is 1, the amplitude conversion period is entered.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921250881.7U CN210155522U (en) | 2019-08-05 | 2019-08-05 | Pixel-level high-precision amplitude-time conversion circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921250881.7U CN210155522U (en) | 2019-08-05 | 2019-08-05 | Pixel-level high-precision amplitude-time conversion circuit |
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| CN210155522U true CN210155522U (en) | 2020-03-17 |
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| CN201921250881.7U Withdrawn - After Issue CN210155522U (en) | 2019-08-05 | 2019-08-05 | Pixel-level high-precision amplitude-time conversion circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110347031A (en) * | 2019-08-05 | 2019-10-18 | 中国兵器工业集团第二一四研究所苏州研发中心 | A kind of high-precision amplitude time converting circuit of Pixel-level |
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2019
- 2019-08-05 CN CN201921250881.7U patent/CN210155522U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110347031A (en) * | 2019-08-05 | 2019-10-18 | 中国兵器工业集团第二一四研究所苏州研发中心 | A kind of high-precision amplitude time converting circuit of Pixel-level |
| CN110347031B (en) * | 2019-08-05 | 2024-01-26 | 中国兵器工业集团第二一四研究所苏州研发中心 | Pixel-level high-precision amplitude-time conversion circuit |
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