CN107300705B - Laser radar ranging system and method based on carrier modulation - Google Patents

Laser radar ranging system and method based on carrier modulation Download PDF

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Publication number
CN107300705B
CN107300705B CN201710435593.8A CN201710435593A CN107300705B CN 107300705 B CN107300705 B CN 107300705B CN 201710435593 A CN201710435593 A CN 201710435593A CN 107300705 B CN107300705 B CN 107300705B
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circuit
light source
signal
signals
output
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CN107300705A (en
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雷述宇
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Ningbo Abax Sensing Electronic Technology Co Ltd
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Ningbo Abax Sensing Electronic Technology Co Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S17/00—Systems using the reflection or reradiation of electromagnetic waves other than radio waves, e.g. lidar systems
    • G01S17/02—Systems using the reflection of electromagnetic waves other than radio waves
    • G01S17/06—Systems determining position data of a target
    • G01S17/08—Systems determining position data of a target for measuring distance only
    • G01S17/32—Systems determining position data of a target for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated
    • G01S17/36—Systems determining position data of a target for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated with phase comparison between the received signal and the contemporaneously transmitted signal
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S17/00—Systems using the reflection or reradiation of electromagnetic waves other than radio waves, e.g. lidar systems
    • G01S17/88—Lidar systems specially adapted for specific applications
    • G01S17/93—Lidar systems specially adapted for specific applications for anti-collision purposes
    • G01S17/931—Lidar systems specially adapted for specific applications for anti-collision purposes of land vehicles
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
    • G01S7/483—Details of pulse systems
    • G01S7/486—Receivers
    • G01S7/4861—Circuits for detection, sampling, integration or read-out
    • G01S7/4863—Detector arrays, e.g. charge-transfer gates

Abstract

The invention provides a laser radar ranging system and a ranging method based on carrier modulation, which have high measurement precision and good anti-interference performance and are used for solving the problems of low measurement precision and poor anti-interference performance of the conventional laser radar ranging system. The distance measuring system comprises a control circuit, a light source, a detecting device and an optical system; the control circuit comprises a main processor and a light source driving circuit; the main processor is connected with both the light source driving circuit and the detection device; the main processor is used for outputting a group of pseudo-random code sequences; the light source driving circuit carries out low-frequency carrier modulation on an optical signal emitted by a light source by using a pseudo-random code sequence; the optical system is used for projecting the optical signal emitted by the light source to a target object to be detected, converging the echo signal reflected by the target object to be detected and projecting the converged echo signal to the detection device; the detection device samples, differentially amplifies and A/D converts the received echo signals and outputs digital signals; and the main processor calculates the phase according to the digital signal and acquires the distance information of the target object to be measured.

Description

Laser radar ranging system and method based on carrier modulation
Technical Field
The invention relates to a laser radar ranging system and a laser radar ranging method based on carrier modulation.
Background
With the development of laser technology, embedded technology and integrated optics, laser ranging is developing towards digitization, automation, low cost and miniaturization. The laser ranging radar has the advantages of high precision, small system volume and rapid measurement, and has wide application prospect.
How to obtain accurate target location among the laser radar range finding process, this has very important effect to improving image resolution, especially to the target vehicle of continuous motion, because of there is electromagnetic interference in the vehicle inside, causes the not accurate problem of measurement easily.
In addition, most of the traditional vehicle-mounted laser radar detectors adopt a single-point testing mode, a mechanical scanning device needs to be configured, the scanning speed is slow, and the image space resolution is low. The focal plane array detector is required to be selected for improving the scanning speed, but the most existing chip packaging process of the focal plane array detector is to separate a detector array and a reading circuit array into two layers, the detector array is arranged on the bottom layer of a chip, the upper layer of the detector array is an A/D converter and an amplifying circuit of the reading circuit, a diode firstly penetrates through a circuit layer of the reading circuit on the upper layer of the diode when receiving a light signal, light loss is easily caused by light reflection when the light is projected to the circuit layer, and the light receiving quantity of the diode is reduced.
Disclosure of Invention
Based on the background, the invention provides the laser radar ranging system and the ranging method based on the carrier modulation, which have high measurement precision and good anti-interference performance, in order to solve the problems of low measurement precision and poor anti-interference performance of the conventional laser radar ranging system.
The technical solution adopted by the invention is as follows:
a laser radar ranging system based on carrier modulation comprises a control circuit, a light source, a detection device and an optical system; the control circuit comprises a main processor and a light source driving circuit;
it is characterized in that:
the main processor is connected with both the light source driving circuit and the detection device; the main processor is used for outputting a group of pseudo-random code sequences;
the light source driving circuit carries out low-frequency carrier modulation on an optical signal emitted by a light source by using a pseudo-random code sequence;
the optical system is used for projecting the optical signal emitted by the light source onto a target object to be detected, converging the echo signal reflected by the target object to be detected and projecting the converged echo signal onto the detection device;
the detection device samples, differentially amplifies and A/D converts the received echo signals and outputs digital signals;
and the main processor calculates the phase according to the digital signal and acquires the distance information of the target object to be measured.
Furthermore, the detection device comprises a detector array, a signal acquisition processing unit, a substrate, interconnection metal, a metal wiring layer, a time sequence control circuit and a row selection module for generating row selection signals;
the detector array is composed of a plurality of independent photodiodes which are arranged on the substrate and correspond to different space field angles;
the signal acquisition processing unit comprises a sampling circuit and a processing circuit consisting of a column differential amplifying circuit, an A/D conversion circuit and a data output module; the data output module comprises a column selection module for generating a column selection signal;
the sampling circuits correspond to the photodiodes one by one, and each sampling circuit is connected with the negative end of the corresponding photodiode and integrated into a whole to form a pixel unit; all the pixel units form a pixel unit array;
the pixel unit array and the processing circuit are integrated on the substrate, the pixel unit array is connected with the metal wiring layer through interconnection metal, and the metal wiring layer is connected with the processing circuit through a data column line;
the number of the column differential amplifying circuits is equal to the number of columns of the pixel unit array, and one column differential amplifying circuit corresponds to one column of pixel units; the output ends of all the sampling circuits of each row of pixel units are connected with the input ends of the row differential amplifying circuits corresponding to the row of pixel units; the output ends of all the column differential amplifying circuits are connected with the input end of the A/D conversion circuit;
the output end of the A/D conversion circuit is connected with the input end of the data output module; the A/D conversion circuit is used for converting the voltage difference signals output by the column differential amplification circuit into digital signals; the sequential control circuit is used for controlling the row selection module and the column selection module to work; and the data output module is used for outputting digital signals which are used for calculating the phase and correspond to the photodiodes determined by the row selection module and the column selection module.
Furthermore, the sampling circuit comprises an NMOS tube NM7, switches S1, S2, S3, S4, S5 and S6, and capacitors C1 and C2; the switches S1-S4 are formed by butting an NMOS tube and a PMOS tube, and the switches S5-S6 are formed by PMOS tubes; NMOS transistors of the switches S1 to S4 are respectively marked as NM1, NM2, NM3 and NM4, PMOS transistors of the switches S1 to S4 are respectively marked as PM1, PM2, PM3 and PM4, and PMOS transistors of the switches S5 to S6 are respectively marked as PM5 and PM 6;
the grid of NM7 is connected with clamping voltage Vb, the source of NM7 is connected with the negative terminal of the photodiode, the drain of NM7 is connected with the drains of NM1, NM2 and PM1, PM 2; the sources of NM1 and PM1 are connected with one end of a capacitor C1, and the sources of NM2 and PM2 are connected with one end of a capacitor C2; the other ends of the capacitor C1 and the capacitor C2 are respectively grounded;
the sources of NM1 and PM1 are also connected with the drains of PM5, PM3 and NM3 at the same time; the gates of NM1 and PM1 are respectively connected with control signals Vs1 and Vs 2; the source of the PM5 is connected with a reset power supply Vdd; the gate of the PM5 is connected with a reset voltage Vrst; the sources of the PM3 and the NM3 are connected to serve as one output end Vout1 of the sampling circuit; the gates of the PM3 and NM3 are respectively connected with control signals Vs3 and Vs 4;
the sources of NM2 and PM2 are also connected with the drains of PM6, PM4 and NM4 at the same time; the gates of NM2 and PM2 are respectively connected with control signals Vs2 and Vs 1; the source of the PM6 is connected with a reset power supply Vdd; the gate of the PM6 is connected with a reset voltage Vrst; the sources of the PM4 and the NM4 are connected with each other to serve as the other output end Vout2 of the sampling circuit; the gates of the PM4 and NM4 are respectively connected with control signals Vs3 and Vs 4;
the control signal Vs1 is a modulation signal sent by the pseudo random code sequence code sent by the main processor and sent to the signal acquisition processing unit, and the control signal Vs2 is obtained by inverting the modulation signal;
the output terminals Vout1 and Vout2 are connected to the two input terminals of the column differential amplifier circuit, respectively.
Furthermore, the a/D conversion circuit includes a ramp generating circuit and a plurality of comparators, the number of the comparators is equal to the number of columns of the pixel unit array, and one comparator corresponds to one column of pixel units; the waveform signal output end of the ramp wave generating circuit is connected with one input end of each comparator, voltage signals output by all sampling circuits of each row of pixel units are sent to the other input end of the comparator corresponding to the row of pixel units through the corresponding row differential amplifying circuit, and the output ends of all comparators are connected with the input end of the data output module;
the ramp wave generating circuit comprises a load resistor R, an integrating capacitor C and an operational amplifier; one end of the load resistor R is connected with a voltage Vin1, the other end of the load resistor R is simultaneously connected with the inverting input end of the operational amplifier and one end of the integrating capacitor C, the other end of the integrating capacitor C is connected with the output end Vramp of the operational amplifier, two ends of the integrating capacitor C are also connected with a reset switch RST in parallel, and the homodromous input end of the operational amplifier is connected with a voltage Vin 2; the voltages Vin1 and Vin2 are used for controlling the ramp wave signal generated by the ramp wave generating circuit, wherein the voltages Vin1 and Vin2 are generated by a voltage dividing circuit in the detecting device;
the data output module also comprises an Nbit counter, an output buffer module and a plurality of memories; the input ends of the plurality of memories are respectively connected with the output ends of the plurality of comparators in a one-to-one correspondence manner, the Nbit counter and the column selection module respectively send control signals to the control ends of the plurality of memories, the data output ends of the plurality of memories are all connected with the input end of the output buffer module through a data bus, and the output end of the output buffer module outputs digital signals for calculating the phase.
Further, a microlens array composed of a plurality of fresnel lenses is arranged at the bottom of the substrate; each fresnel lens corresponds to one pixel unit and is used for transmitting the echo signal light and converging the echo signal light onto the photodiode of the corresponding pixel unit.
Further, the modulation frequency of the low frequency carrier is <500 MHz.
Further, the main processor is a DSP digital signal processor, an FPGA programmable gate array, a special ASIC, a GPU or a CPU; the light source is a surface light source, an LED light source or an LD light source.
The invention also provides a method for ranging by using the laser radar ranging system, which comprises the following steps:
1) generating a set of pseudo-random code sequences by a main processor;
2) carrying out low-frequency carrier modulation on an optical signal output by a light source by using a pseudo-random code sequence;
3) projecting the modulated optical signal onto a target object to be measured;
4) each pixel unit of the detection device receives echo signals reflected by a target object to be detected respectively, and sampling, differential amplification and A/D conversion processing are carried out on the echo signals to obtain digital signals;
5) and the main processor calculates the phase according to the digital signal and acquires the distance information of the target object to be detected.
Further, the step 2) is specifically: the pseudo random code sequence output by the main processor is transmitted to the light source driving circuit, and the light source driving circuit modulates through current to ensure that the intensity of the light source is synchronously changed along with the pseudo random code generated by the main processor.
Compared with the prior art, the invention has the following advantages:
1. the invention utilizes the low-frequency pseudo-random code sequence to carry out carrier modulation on the light source signal, thereby improving the measurement precision and the anti-interference capability of the system.
2. The detection device adopted by the invention is an array detector, thereby avoiding the dependence of a distance measurement system on a mechanical scanning device and simultaneously improving the reliability of the system.
3. The invention adopts the detector array to carry out area array detection on the echo signal, the detector array is composed of a plurality of independent photodiodes, each photodiode and a sampling circuit connected with the photodiode form a pixel unit, each pixel unit corresponds to a complete reading circuit, and when the system works, each pixel unit simultaneously carries out data conversion, thereby greatly improving the scanning speed of the ranging system compared with the traditional single-point detection mode.
4. Each photodiode of the detector array corresponds to different space field angles through the lens, and the image space resolution is high.
5. Each photodiode in the detector array is integrated with a sampling circuit, and the circuit simply processes signals in a small-sized chip.
6. The detection device adopts a back-illuminated design, the metal wiring layer is arranged at the bottom layer of the photodiode, the photodiode can be directly contacted with the light-transmitting surface, the light loss of an intermediate link is reduced, and the thickness of a chip is effectively reduced.
7. The bottom of the substrate of the detection device is provided with the micro-lens array, each photodiode corresponds to one micro-lens, echo signal light is more effectively converged on the corresponding photodiode, and redundant light interference among the photodiodes is reduced.
Drawings
FIG. 1 is a schematic diagram of the structure of the distance measuring system of the present invention;
FIG. 2 is a schematic block diagram of the circuit of the signal acquisition processing unit of the present invention;
FIG. 3 is a schematic view of the overall structure of the detecting device of the present invention;
FIG. 4 is a schematic diagram of the structure of the detecting device of the present invention;
FIG. 5 is a side sectional view of a probing apparatus of the present invention;
FIG. 6 is a schematic diagram of the overall structure of the detecting device and its output interface system according to the present invention;
FIG. 7 is a wiring diagram of the pixel output of the detector shown in FIG. 6;
FIG. 8 is an overall schematic block diagram of the detection apparatus of the present invention;
FIG. 9 is a schematic diagram of the ramp generating circuit of FIG. 8;
FIG. 10 is a schematic diagram of the sampling circuit of FIG. 8;
FIG. 11 is a schematic view of a one-dimensional row gating module of the detection apparatus of the present invention;
FIG. 12 is a schematic diagram of a two-dimensional row/column gating module of the detection apparatus of the present invention;
FIG. 13 is a timing diagram of the probing apparatus of the present invention;
FIG. 14 is a logic diagram of an address row enable strobe switch of the detection apparatus of the present invention;
FIG. 15 is a logic diagram of an addressed column enable gating switch of the detection apparatus of the present invention.
Description of reference numerals:
1-a control circuit, 11-a main processor, 12-a light source driving circuit, 13-a peripheral interface circuit, 2-a light source, 3-a detection device, 31-a signal acquisition processing unit, 32-a detector array, 311-a sampling circuit, 312-a processing circuit, 3121-a column differential amplification circuit, 3122-A/D conversion circuit, 3123-a data output module,
301-microlens, 302-substrate, 303-device active region (epi layer), 304-metal wiring layer, 305-interconnect metal, 306-pixel cell array, 3031-photodiode, 307-data column line,
322. 324-N type doped layer, 325-P type doped layer, 326-cathode electrode, 327-anode electrode, 328-SiO2The isolation layer is arranged on the substrate,
4-optical system, 5-target, 6-peripheral, 7-row-gating address line, 8-data bus.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and examples.
Referring to fig. 1-8, the lidar ranging system provided by the present invention mainly includes a control circuit 1, a light source 2 (which may be a surface light source, an LED light source or an LD light source), an optical system 4, and a detection device 3 composed of a detector array 32 and a signal acquisition processing unit 31;
the control circuit 1 mainly comprises a main processor 11, a light source driving circuit 12 and an external interface circuit 13, wherein the output end of the light source driving circuit 12 is connected with the input end of the light source 2, and the I/O port of the main processor 11 is respectively connected with the detection device 3, the light source driving circuit 12 and the external interface circuit 13; the main processor 11 as a core control device of the control circuit can select a DSP digital signal processor or a FPGA programmable gate array or a special ASIC or a GPU or a CPU; the external interface circuit 13 can adopt RS-422, RS-485 or RS-232 interfaces;
the detector array 32 is used for receiving the echo signal returned by the optical system 4, and the detector array 32 is composed of a plurality of independent photodiodes 3031 for collecting echo signal light; the photodiode 3031 is disposed on the substrate 302, and is distributed in the device active region (epitaxial layer) 303 between the substrate 302 and the metal wiring layer 304;
the signal acquisition processing unit 31 is used for receiving and processing the output signals of the detector array 32, and the signal acquisition processing unit 31 is communicated with the main processor 11; the signal acquisition processing unit 31 comprises a sampling circuit 311 and a processing circuit 312 which is composed of a column differential amplifying circuit 3121, an A/D conversion circuit 3122 and a data output module 3123; the sampling circuit 311, the column differential amplifying circuit 3121, the a/D conversion circuit 3122, and the data output module 3123 are connected in sequence; the sampling circuit 311 is configured to complete the collection and charge accumulation of pixel signals, output two voltage signals to the column differential amplification circuit 3121, transmit a difference signal obtained by the column differential amplification circuit 3121 to the a/D conversion circuit 3122, convert an analog signal into a digital signal for calculating a phase through the a/D conversion circuit 3122, and finally transmit the digital signal to the main processor 11 through the data output module 3123;
the negative terminal of each photodiode 3031 in the detector array 32 is connected with a sampling circuit 311 and integrated with the sampling circuit 311 to form a pixel unit; all the pixel units form a pixel unit array 306; the processing circuit 312 serves as a readout circuit for the pixel cell array;
the detection device 3 further comprises a substrate 302 (made of Si), an interconnection metal 305 (the interconnection metal is used as a contact to realize the connection of the device and the Si substrate), a metal wiring layer 304, a timing control circuit and a row selection module for generating a row selection signal; the pixel unit array 306, the processing circuit 312, the timing control circuit and the row selection module are integrated on the substrate 302, the pixel unit array 306 is connected with the metal wiring layer 304 through an interconnection metal 305, and the metal wiring layer 304 is connected with the processing circuit 312 through a data column line 307;
referring to fig. 4, the metal wiring layer 304 is formed by a plurality of metal wiring units, and each column of metal wiring units corresponds to one column of pixel units; each metal wiring unit is composed of multiple metal layers and multiple dielectric layers, each metal layer is provided with a connection point, the multiple dielectric layers are respectively arranged between two adjacent metal layers, and the dielectric layers are made of SiO2An insulating layer of material.
Referring to fig. 4, a microlens array integrated with the substrate 302 is further disposed at the bottom of the substrate 302, the microlens array is composed of a plurality of fresnel lenses, each fresnel lens corresponds to one pixel unit, and is used for transmitting the echo signal light and converging the echo signal light onto the photodiode 3031 of the corresponding pixel unit, so that the photodiode 306 is facilitated to absorb the light signal, and the microlens array effectively improves the surface transmittance of the substrate.
Referring to FIG. 5, a substrate 302 is provided with SiO on top2 An isolation layer 328 of SiO2The isolation layer 328 is provided with a plurality of holes for embedding the cathode electrode 326 and the anode electrode 327, an N-type doped layer 324 with an area larger than the sectional area of the cathode electrode 326 is arranged at the contact surface of the cathode electrode 326 embedded in the substrate 302, and a P-type doped layer 325 with an area larger than the sectional area of the anode electrode 327 is arranged at the contact surface of the anode electrode 327 embedded in the substrate 302. The substrate 302 has an N-doped layer 322 at the bottom and the microlens array is disposed at the bottom of the N-doped layer 322.
Sampling circuit
Referring to fig. 7 and 8, a plurality of sampling circuits 311 are provided, and correspond to the photodiodes 3031 one by one, and a negative terminal of each photodiode 3031 is connected with one sampling circuit 311 and integrated.
Referring to fig. 10, the sampling circuit 311 includes an NMOS transistor NM7, switches S1, S2, S3, S4, S5, S6, and capacitors C1, C2; the switches S1-S4 are formed by butting an NMOS tube and a PMOS tube, and the switches S5-S6 are formed by PMOS tubes; NMOS transistors of the switches S1 to S4 are respectively marked as NM1, NM2, NM3 and NM4, PMOS transistors of the switches S1 to S4 are respectively marked as PM1, PM2, PM3 and PM4, and PMOS transistors of the switches S5 to S6 are respectively marked as PM5 and PM 6;
the source of NM7 is connected with the negative terminal of the photodiode, the drain of NM7 is connected with the drains of NM1 and NM2 and the drains of PM1 and PM2, and the gate of NM7 is connected with the clamping voltage Vb; the sources of NM1 and PM1 are connected with one end of a capacitor C1, and the sources of NM2 and PM2 are connected with one end of a capacitor C2; the other ends of the capacitor C1 and the capacitor C2 are respectively grounded;
the sources of NM1 and PM1 are also connected with the drains of PM5, PM3 and NM3 at the same time; the gates of NM1 and PM1 are respectively connected with control signals Vs1 and Vs 2; the source of the PM5 is connected with a reset power supply Vdd; the gate of the PM5 is connected with a reset voltage Vrst; the sources of the PM3 and the NM3 are connected to serve as one output end Vout1 of the sampling circuit; the gates of the PM3 and NM3 are respectively connected with control signals Vs3 and Vs 4;
the sources of NM2 and PM2 are also connected with the drains of PM6, PM4 and NM4 at the same time; the gates of NM2 and PM2 are respectively connected with control signals Vs2 and Vs 1; the source of the PM6 is connected with a reset power supply Vdd; the gate of the PM6 is connected with a reset voltage Vrst; the sources of the PM4 and the NM4 are connected with each other to serve as the other output end Vout2 of the sampling circuit; the gates of the PM4 and NM4 are respectively connected with control signals Vs3 and Vs 4;
the control signal Vs1 is a modulation signal sent by the pseudo random code sequence code sent by the main processor and sent to the signal acquisition processing unit, and the control signal Vs2 is obtained by inverting the modulation signal;
NM7 is a clamp circuit for preventing the voltage across the photodiode from changing greatly when the voltage on the capacitors C1 and C2 changes;
the output terminals Vout1 and Vout2 are connected to the two input terminals of the column differential amplification circuit 3121, respectively.
The working principle of the sampling circuit shown in fig. 10 is:
the NMOS transistor NM7 connected to the photodiode performs a clamping function, and Vb is a clamping voltage.
Capacitors C1 and C2 are in-pixel integration capacitors, switches S1 and S2 are used for controlling in-pixel integration processes, control signals Vs1 of an NMOS tube NM1 of the switch S1 and a PMOS tube PM2 of the switch S2, control signals Vs2 of a PMOS tube PM1 of the switch S1 and an NMOS tube NM2 of the switch S2 are control signals output by the row selection module, and voltages Vs1 and Vs2 are opposite; vs1 is high Vs2 is low, S1 is closed and S2 is open; vs1 is low Vs2 is high, S1 opens S2 closure.
The switches S3 and S4 are used for controlling the output of the integrated voltage in the pixel, S3 and S4 are respectively formed by butting a pair of PMOS and NMOS transistors, a control signal Vs3 of a PMOS transistor PM4 of the switch S4 and a control signal Vs4 of an NMOS transistor NM3 of the switch S3 are row selection signals output by the row selection module, the Vs3 is set to be high, Vs4 is set to be low, S3 and S4 can be disconnected, the Vs3 is set to be low, Vs4 is set to be high, and S3 and S4 can be closed.
The switches S5 and S6 function to control the reset of the capacitance in the pixel, and the Vrst signal at the control terminal comes from the row selection module, and Vrst is set high to open S5 and S6, and Vrst is set low to close S5 and S6.
The operation of the sampling circuit shown in fig. 10
In fig. 13, the upper diagram represents the signal cycle of a certain row and each frame, the lower diagram represents the specific change situation of a certain row of signals in a frame, different signals control the on and off of different switches, and the following describes the working process of the sampling circuit with reference to fig. 10 and 13 and the working state of the switches:
the method comprises the following steps: the switches S3, S4, S5 and S6 are opened, the switches S1 and S2 are alternately closed according to control signals Vs1 and Vs2, the light source emits modulated light according to the modulation signal, the control signal Vs1 is the same as the modulation signal, the control signal Vs2 is just opposite to the modulation signal, and the charges generated by the echoes are stored in the capacitor C1 and the capacitor C2.
Step two: the switches S1 and S2 are disconnected, the switches S5 and S6 are still in an open state, the switches S3 and S4 are closed through row selection signals, the voltages of the capacitors C1 and C2 are transmitted to the two column lines Vout1 and Vout2 and transmitted to the column differential amplification circuit, the difference of the voltages of the capacitors C1 and C2 is obtained, the voltage difference signal is transmitted to the A/D conversion circuit, the analog signal is converted into a digital signal, and finally the digital signal is transmitted to the outside of the detection device through the data output module.
In this step, the voltage of the capacitor C1 is A1D, [ integral ] m (t) m (t-Td) & dt, the voltage of the capacitor C2 is A1∫[1-m(t)]m (t-Td) dt, processed by a differential amplifier circuit, and output A2∫[2m(t)-1]m(t-Td)·dt＝A3(Tc-Td); wherein A is1、A2And A3All are coefficients and, in the case of approximately constant time, are constant values.
Step three: after the transmission is finished, the switches S5 and S6 are closed, the switches S3 and S4 are opened, the switches S1 and S2 are still in an open state, and the reset of the data column line and the capacitors C1 and C2 is completed.
Step four: the switches S3, S4, S5 and S6 are opened, the switches S1 and S2 are alternately closed according to control signals Vs1 and Vs2, the light source emits modulated light according to the modulation signal, the control signal Vs1 is delayed by one chip length from the modulation signal, the control signal Vs2 is just opposite to the control signal Vs1, and charges generated by the echo signal are stored in the capacitors C1 and C2.
Step five: the switches S1 and S2 are both opened, the switches S5 and S6 are both kept in an opened state, the switches S3 and S4 are closed through row selection signals, the voltages of the capacitors C1 and C2 are transmitted to the two output ends Vout1 and Vout2 and transmitted to the column differential amplification circuit to obtain the difference of the voltages of the capacitors C1 and C2, then the voltage difference signal is transmitted to the A/D conversion circuit, the analog signal is converted into a digital signal and finally transmitted to the outside of the detection device through the data output module, and after the transmission is finished, the switches S5 and S6 are closed to reset the capacitors in the pixel units.
In this step, the voltage of the capacitor C1 is A1Integral [ n (t-Tc) m (t-Td) dt, voltage of capacitor C2 is A1∫[1-m(t-Tc)]m (t-Td) dt, processed by a differential amplifier circuit, and output A2∫[2m(t-Tc)-1]m(t-Td)·dt＝A3·Td。
Step six: the switches S1, S2, S5, and S6 are closed, the switches S3 and S4 are opened, and the photodiode and the capacitors C1 and C2 are reset.
Two data (A) output in step two and step five3(Tc-Td) and A3Td) for feeding into the main processor for calculation to obtain distance information.
The voltage values of C1 and C2 are involved in the second step and the fifth step, wherein m refers to m sequence, Tc refers to the time of a small pulse, namely the time length of a chip; td is the delay time of the return.
Column differential amplifier circuit
Referring to fig. 8, the number of the column differential amplification circuits 3121 is equal to the number of columns of the pixel cell array, and one column differential amplification circuit corresponds to one column of pixel cells; the output ends of all the sampling circuits of each row of pixel units are connected with the input ends of the row differential amplifying circuits corresponding to the row of pixel units; the output terminals of all the column differential amplification circuits are connected to the input terminal of the a/D conversion circuit 3122.
A/D conversion circuit
Referring to fig. 8, the a/D conversion circuit 3122 includes a ramp wave generation circuit and a plurality of comparators, the number of which is equal to the number of columns of the photodiodes 3031, one comparator corresponding to each column of the photodiodes; the waveform signal output end of the ramp generating circuit is connected with one input end of each comparator, the output end of the column differential amplifying circuit 312 corresponding to each column of the photodiode 3031 is connected with the other input end of each comparator, and the output ends of all the comparators are connected with the input end of the data output module.
Referring to fig. 9, the ramp wave generating circuit includes a load resistor R, an integrating capacitor C, and an operational amplifier; one end of the load resistor R is connected with a voltage Vin1, the other end of the load resistor R is simultaneously connected with the inverting input end of the operational amplifier and one end of the integrating capacitor C, the other end of the integrating capacitor C is connected with the output end Vramp of the operational amplifier, two ends of the integrating capacitor C are also connected with a reset switch RST in parallel, and the homodromous input end of the operational amplifier is connected with a voltage Vin 2; the voltages Vin1, Vin2 are used for controlling the ramp signal generated by the ramp generating circuit, wherein the voltages Vin1, Vin2 are generated by the voltage dividing circuit in the detecting device.
Data output module
The data output module 3123 includes Nbit counter, column selection module, output buffer module and multiple memories; the input ends of the memories are connected with the output ends of the comparators in the a/D conversion circuit 3122 in a one-to-one correspondence manner, the Nbit counter and the column selection module respectively send control signals to the control ends of all the memories, the data output ends of all the memories are connected with the input end of the output buffer module through a data bus, and the output buffer module outputs digital signals for calculating phases.
Sequential control circuit
The time sequence control circuit is used for controlling the row selection module in the detection device and the column selection module in the data output module to work, and the time sequence control circuit can adopt the existing modules.
As shown in fig. 14, the row selection module of the detection apparatus may obtain the row selection signal by decoding the output of the row counter, and the enabling time is respectively the same as the period of the row clock signal; where Row _ clk is a Row clock signal, 1 and 2 in fig. 14 respectively represent Row strobe switch control signals, Q <1> to Q < n > respectively represent output data of a 1-bit counter, and NQ <1> to NQ < n > represent output data of an Nbit counter.
As shown in fig. 15, the column selection module of the detection apparatus may obtain the column selection signal by decoding the output of the column counter, and the enabling time is respectively the same as the period of the column clock signal; wherein Col _ clk is a column clock signal, 1 and 2 in fig. 15 respectively represent column gating switch control signals, Q <1> to Q < n > respectively represent output data of a 1-bit counter, and NQ <1> to NQ < n > represent output data of an Nbit counter.
The working principle of the detection device 3 is as follows:
as shown in fig. 7, each pixel cell has a row-gating address line connected to the row-selection module, the row-gating address line being connected to switches S1-S6 for controlling the sampling circuit of each pixel cell and a reset power supply Vdd, respectively, wherein the switches S1 and S2 are signaled by Vs1 and Vs2, the switches S3 and S4 are signaled by Vs3 and Vs4, wherein the switches S5, S6 and the reset power supply Vdd are signaled by Vrst; each row of pixel units shares two data column lines 307, and the output ends of the data column lines 307 are sequentially connected with a row differential amplifying circuit, an A/D conversion circuit and a data output module; as shown in fig. 8, after the integration of the sampling circuit 311 is finished, the ramp generating circuit in the a/D conversion circuit starts to operate, and the data of the sampling circuit in a certain row of pixel units is read out by the selection of the row selection signal provided by the row selection module;
the differential signal output by the column differential amplifying circuit corresponding to each column of pixel units and the output signal of the ramp generating circuit are respectively sent to two input ends of a comparator corresponding to each column of pixel units, and when the output end of the comparator is turned over, the count value of the current Nbit counter is stored in a memory corresponding to the comparator;
after the ramp wave generating circuit is cut off, the data in the memory are controlled to be sequentially read to the data bus through the column selection signals given by the column selection module in the data output module, and then the data are read out of the detection device through the output buffer module in the data output module.
The working principle and the process of the ranging system are as follows:
the main processor 11 outputs two pseudo-random code sequences: one path of the signal is to modulate the light source signal of the light source 2 by a low frequency (modulation frequency <500MHz) carrier through a light source driving circuit 12 to obtain a modulation signal; one path of the signal is sent to the signal acquisition and processing unit 31 to control the on/off of the switch S1 in the sampling circuit 311;
the transmitting end of the light source 2 projects the transmitted light to the target object 5 through the optical system 4, during the transmission process of the atmospheric medium, the echo signals reflected by the target object 5 after the light signals are absorbed and scattered by the atmospheric medium are converged by the optical system 4 and then projected to the detector array 32, and the signal acquisition and processing unit 31 acquires, differentially amplifies and A/D converts the echo signals absorbed by the detector array 32 to obtain digital quantity signals; and the main processor calculates and processes the digital quantity signal to obtain the distance information of the target object to be measured. The specific calculation method for obtaining the distance information comprises the following steps: a is to be3(Tc-Td) and A3Td is ratioed in FPGA to get
Figure BDA0001318546760000141
Td is obtained with known Tc; and due to
Figure BDA0001318546760000142
The distance D can be obtained by taking the distance from the object to be detected to the detector array and the light speed as c.

Claims (9)

1. A laser radar ranging system based on carrier modulation comprises a control circuit, a light source, a detection device and an optical system; the control circuit comprises a main processor and a light source driving circuit;
the method is characterized in that:
the main processor is connected with both the light source driving circuit and the detection device; the main processor is used for outputting a group of pseudo-random code sequences;
the light source driving circuit carries out low-frequency carrier modulation on an optical signal emitted by a light source by using a pseudo-random code sequence;
the optical system is used for projecting the optical signal emitted by the light source onto a target object to be detected, converging the echo signal reflected by the target object to be detected and projecting the converged echo signal onto the detection device;
the detection device samples the received echo signals based on the modulation of the pseudo-random code sequence to generate two groups of voltage signals, wherein each group of voltage signals comprises two voltage sub-signals, and the two groups of voltage signals are subjected to differential amplification and A/D conversion respectively and then output digital signals;
and the main processor calculates the phase according to the digital signal and acquires the distance information of the target object to be measured.
2. The carrier modulation based lidar ranging system of claim 1, wherein: the detection device comprises a detector array, a signal acquisition and processing unit, a substrate, interconnection metal, a metal wiring layer, a time sequence control circuit and a row selection module for generating row selection signals;
the detector array is composed of a plurality of independent photodiodes which are arranged on the substrate and correspond to different space field angles;
the signal acquisition processing unit comprises a sampling circuit and a processing circuit consisting of a column differential amplifying circuit, an A/D conversion circuit and a data output module; the data output module comprises a column selection module for generating a column selection signal;
the sampling circuits correspond to the photodiodes one by one, and each sampling circuit is connected with the negative end of the corresponding photodiode and integrated into a whole to form a pixel unit; all the pixel units form a pixel unit array;
the pixel unit array and the processing circuit are integrated on the substrate, the pixel unit array is connected with the metal wiring layer through interconnection metal, and the metal wiring layer is connected with the processing circuit through a data column line;
the number of the column differential amplifying circuits is equal to the number of columns of the pixel unit array, and one column differential amplifying circuit corresponds to one column of pixel units; the output ends of all the sampling circuits of each row of pixel units are connected with the input ends of the row differential amplifying circuits corresponding to the row of pixel units; the output ends of all the column differential amplifying circuits are connected with the input end of the A/D conversion circuit;
the output end of the A/D conversion circuit is connected with the input end of the data output module; the A/D conversion circuit is used for converting the voltage difference signals output by the column differential amplification circuit into digital signals; the sequential control circuit is used for controlling the row selection module and the column selection module to work; and the data output module is used for outputting digital signals which are used for calculating the phase and correspond to the photodiodes determined by the row selection module and the column selection module.
3. The carrier modulation based lidar ranging system of claim 2, wherein: the sampling circuit comprises an NMOS tube NM7, switches S1, S2, S3, S4, S5 and S6, and capacitors C1 and C2; the switches S1-S4 are formed by butting an NMOS tube and a PMOS tube, and the switches S5-S6 are formed by PMOS tubes; NMOS transistors of the switches S1 to S4 are respectively marked as NM1, NM2, NM3 and NM4, PMOS transistors of the switches S1 to S4 are respectively marked as PM1, PM2, PM3 and PM4, and PMOS transistors of the switches S5 to S6 are respectively marked as PM5 and PM 6;
the grid of NM7 is connected with clamping voltage Vb, the source of NM7 is connected with the negative terminal of the photodiode, the drain of NM7 is connected with the drains of NM1, NM2 and PM1, PM 2; the sources of NM1 and PM1 are connected with one end of a capacitor C1, and the sources of NM2 and PM2 are connected with one end of a capacitor C2; the other ends of the capacitor C1 and the capacitor C2 are respectively grounded;
the sources of NM1 and PM1 are also connected with the drains of PM5, PM3 and NM3 at the same time; the gates of NM1 and PM1 are respectively connected with control signals Vs1 and Vs 2; the source of the PM5 is connected with a reset power supply Vdd; the gate of the PM5 is connected with a reset voltage Vrst; the sources of the PM3 and the NM3 are connected to serve as one output end Vout1 of the sampling circuit; the gates of the PM3 and NM3 are respectively connected with control signals Vs3 and Vs 4;
the sources of NM2 and PM2 are also connected with the drains of PM6, PM4 and NM4 at the same time; the gates of NM2 and PM2 are respectively connected with control signals Vs2 and Vs 1; the source of the PM6 is connected with a reset power supply Vdd; the gate of the PM6 is connected with a reset voltage Vrst; the sources of the PM4 and the NM4 are connected with each other to serve as the other output end Vout2 of the sampling circuit; the gates of the PM4 and NM4 are respectively connected with control signals Vs3 and Vs 4;
the control signal Vs1 is a modulation signal sent by the pseudo random code sequence code sent by the main processor and sent to the signal acquisition processing unit, and the control signal Vs2 is obtained by inverting the modulation signal;
the output terminals Vout1 and Vout2 are connected to the two input terminals of the column differential amplifier circuit, respectively.
4. The carrier modulation based lidar ranging system of claim 3, wherein: the A/D conversion circuit comprises a ramp wave generation circuit and a plurality of comparators, the number of the comparators is equal to the number of columns of the pixel unit array, and one comparator corresponds to one column of pixel units; the waveform signal output end of the ramp wave generating circuit is connected with one input end of each comparator, voltage signals output by all sampling circuits of each row of pixel units are sent to the other input end of the comparator corresponding to the row of pixel units through the corresponding row differential amplifying circuit, and the output ends of all comparators are connected with the input end of the data output module;
the ramp wave generating circuit comprises a load resistor R, an integrating capacitor C and an operational amplifier; one end of the load resistor R is connected with a voltage Vin1, the other end of the load resistor R is simultaneously connected with the inverting input end of the operational amplifier and one end of the integrating capacitor C, the other end of the integrating capacitor C is connected with the output end Vramp of the operational amplifier, two ends of the integrating capacitor C are also connected with a reset switch RST in parallel, and the homodromous input end of the operational amplifier is connected with a voltage Vin 2; the voltages Vin1 and Vin2 are used for controlling the ramp wave signal generated by the ramp wave generating circuit, wherein the voltages Vin1 and Vin2 are generated by a voltage dividing circuit in the detecting device;
the data output module also comprises an Nbit counter, an output buffer module and a plurality of memories; the input ends of the plurality of memories are respectively connected with the output ends of the plurality of comparators in a one-to-one correspondence manner, the Nbit counter and the column selection module respectively send control signals to the control ends of the plurality of memories, the data output ends of the plurality of memories are all connected with the input end of the output buffer module through a data bus, and the output end of the output buffer module outputs digital signals for calculating the phase.
5. The carrier modulation based lidar ranging system of any of claims 2 to 4, wherein: a micro-lens array formed by a plurality of Fresnel lenses is arranged at the bottom of the substrate; each fresnel lens corresponds to one pixel unit and is used for transmitting the echo signal light and converging the echo signal light onto the photodiode of the corresponding pixel unit.
6. The carrier modulation based lidar ranging system of any of claims 1 to 4, wherein: the modulation frequency of the low frequency carrier is <500 MHz.
7. The carrier modulation based lidar ranging system of any of claims 1 to 4, wherein: the main processor is a DSP digital signal processor, an FPGA programmable gate array, a special ASIC, a GPU or a CPU; the light source is a surface light source, an LED light source or an LD light source.
8. A method of ranging using the lidar ranging system of any of claims 1 to 7, comprising the steps of:
1) generating a set of pseudo-random code sequences by a main processor;
2) carrying out low-frequency carrier modulation on an optical signal output by a light source by using a pseudo-random code sequence;
3) projecting the modulated optical signal onto a target object to be measured;
4) each pixel unit of the detection device receives echo signals reflected by a target object to be detected respectively, samples the echo signals based on the modulation of the pseudo-random code sequence, generates two groups of voltage signals, wherein each group of voltage signals comprises two voltage sub-signals, and performs differential amplification and A/D conversion processing on the two groups of voltage signals respectively to obtain digital signals;
5) and the main processor calculates the phase according to the digital signal and acquires the distance information of the target object to be detected.
9. The method according to claim 8, wherein the step 2) is specifically: the pseudo random code sequence output by the main processor is transmitted to the light source driving circuit, and the light source driving circuit modulates through current to ensure that the intensity of the light source is synchronously changed along with the pseudo random code generated by the main processor.
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