CN108848326B - Front-end reading circuit of high dynamic range MCP detector and reading method thereof - Google Patents

Front-end reading circuit of high dynamic range MCP detector and reading method thereof Download PDF

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CN108848326B
CN108848326B CN201810605557.6A CN201810605557A CN108848326B CN 108848326 B CN108848326 B CN 108848326B CN 201810605557 A CN201810605557 A CN 201810605557A CN 108848326 B CN108848326 B CN 108848326B
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module
switch
signal
comparator
dynamic range
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CN108848326A (en
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常玉春
王若溪
李亮
郭玉萍
刘芳圆
李婕菲
慕雨松
殷景志
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Jilin University
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

The invention discloses a front-end reading circuit of a high dynamic range MCP detector and a reading method thereof, belonging to the technical field of semiconductor image sensing and comprising a signal input module, a dynamic range expansion module, a buffer module, a high-speed comparator module, a time-to-digital conversion module and a logic circuit module; the photoelectric current signal from the detector enters a front-end reading circuit through a signal input module, then is subjected to integration and dynamic range expansion processing through a dynamic range expansion module, and the voltage signal after integration is subjected to buffering processing through a buffer module and then is transmitted to a high-speed comparator module which comprises a first comparator and a second comparator. The invention adopts the judgment process of the strength of the input signal to be placed in the pixel for processing, does not need the complex back-end processing process, simplifies the design process of the back-end circuit, and ensures that the whole chip has simple structure, high pixel filling ratio and good chip area utilization ratio.

Description

Front-end reading circuit of high dynamic range MCP detector and reading method thereof
Technical Field
The invention belongs to the technical field of semiconductor image sensing, and particularly designs a front-end reading circuit of a high dynamic range MCP detector and a reading method thereof.
Background
The fast neutron photography technology can obtain detailed internal characteristics of materials by deeply analyzing an object to be detected, thereby realizing the function of nondestructive detection on complex articles and structures, and having wide requirements and applications in a plurality of basic scientific fields such as condensed state physics, material science and engineering, earth science and bioscience and the like.
The single photon detector applied to the fast neutron photography field needs to have single photon sensitivity, also needs to be capable of carrying out high-precision time marking on the photons arriving at each moment, and simultaneously records high-precision space two-dimensional coordinates of the photons, namely, the single photon detector with three-dimensional high space-time resolution is required.
The micro-channel plate (MCP) can work in a pulse counting mode, has response time of dozens of picoseconds and spatial resolution capacity of several micrometers, becomes one of the first planar array photoelectric conversion devices of the single-photon detector, and can be combined with different charge distribution and processing devices to form the three-dimensional imaging detector with single-photon sensitivity. In addition, MCP has the advantages of being capable of working in a strong magnetic field, small in dark noise and the like.
The Dynamic Range (DR) is an important index of a single photon detector, and marks the light intensity range which can be processed by the detector, and the unit of the dynamic range is expressed by decibel (dB). One of the factors limiting the dynamic range is the size of the integrating capacitance (i.e., well capacity) inside the pixel, with larger capacitances leading to higher detectable light intensities.
In the single photon detection process, in order to meet the characteristics of ultra-high brightness and ultra-wide energy spectrum of a photon emission source, a reading circuit must have a very high dynamic range, but if only an integral capacitor is increased, the unit pixel area is increased. Therefore, in the design process of the front-end readout circuit, compromise between performance and area needs to be considered, and the dynamic range needs to be improved while the area is reduced and the power consumption is reduced.
In recent years, research in the field of fast neutron photography has attracted extensive attention in academic circles, and international research results on new materials and high-performance MCP single photon detectors have been proposed, but research on read-out circuits of MCP detectors is less involved, and research on high-performance ASIC chips specially designed for reading out signals of MCP detectors is almost blank. In addition, in the design of a front-end reading circuit of a traditional MCP detector, optimization processing is not performed aiming at a performance parameter of a dynamic range, so that the input signal range of the whole single photon detection system is very small, and the application field is relatively limited.
In order to fully exert the advantage of single photon detection capability of MCP, the MCP is applied to a fast neutron photographic system, the traditional reading circuit structure cannot guarantee that high-precision spatial resolution capability and high-precision time resolution capability can be obtained simultaneously under the condition of high counting rate, and when the number of charges output by the MCP is too large, the traditional circuit structure based on a charge amplifier causes signal saturation, and the number of charges cannot be accurately calculated. At present, the existing read signal processing scheme is not ideal in improving system performance such as dynamic range and resolution, and an ideal scheme capable of improving dynamic range and reducing chip area is not provided in the industry.
Disclosure of Invention
In order to solve the technical problem, the invention provides a front-end reading circuit of an MCP detector with a high dynamic range and a reading method thereof, which adopt a plurality of times of charge transfer logic (similar to an asynchronous logic successive approximation type analog-to-digital converter based on charge redistribution) and can provide an ultra-wide input signal dynamic range.
The invention is realized by the following technical scheme:
a front-end reading circuit of a high dynamic range MCP detector comprises a signal input module, a dynamic range expansion module, a buffer module (AMP), a high-speed Comparator Module (CMP), a time-to-digital conversion module (TDC) and a LOGIC circuit module (LOGIC); the high-speed comparator module comprises a first comparator CMP1 and a second comparator CMP2, the comparison result of the first comparator is converted into a digital signal through a time-to-digital conversion module and then is stored in data, and the comparison result of the second comparator generates a switch control signal of the dynamic range expansion module through a logic circuit module.
Furthermore, the signal input module comprises two input signal electrodes, namely a PAD and a TP, wherein the PAD is an MCP electron cloud charge collecting electrode, the TP is an input signal electrode for testing, and the PAD and the TP are connected to the same output node through a Test switch Test.
Further, the dynamic range extension module comprises a first sampling capacitor C1A second sampling capacitor C2A first switch S1A second switch S2And a third switch S3(ii) a Wherein, the first sampling capacitor C1And a second sampling capacitor C2For storage of electric charge, C1One end is connected with the wire grounding end (GND), and the other end is connected with the S1Connected together, the node is A; c2One end is connected with the ground end of the wire, and the other end is connected with the S2Connected together, node B, S1And S2The other ends are connected to a reference potential VREF，S3Both ends of which are connected to nodes a and B, respectively.
Further, the buffer module is a unity gain amplifier, which adopts a differential input single-ended output amplifier structure, and the inverting input end and the output end of the amplifier structure are connected together, so that the closed loop gain is 1.
Further, the threshold voltages of the first comparator and the second comparator are different; the first comparator is used for judging the arrival time of the input signal; the second comparator is used to determine the saturation state of the front-end sensing circuit.
Further, the time-to-digital conversion module comprises a coarse counting module and a fine counting module, wherein the coarse counting module is used for performing coarse counting on the arrival time, the fine counting module is used for performing detailed counting on the arrival time so as to improve the resolution, and then the counting result is output to a Static Random Access Memory (SRAM) for storage.
Further, the logic module comprises a combined logic part consisting of an AND gate and an OR gate and a two-phase non-overlapping clock generation part, and the first switch S is calculated according to the output signal of the second comparator1A second switch S2And a third switch S3And then returns to the dynamic range expansion module.
The high dynamic range MCP detectorThe front-end readout circuit can be based on S1、S2、S3The logical relation of control signals of the three switches (given by a logic module) is that the charges are respectively arranged at C1、C2And the two integrating capacitors are transferred to obtain higher input signal dynamic range. Specifically, the reading method of the front-end reading circuit of the high dynamic range MCP detector comprises the following specific steps:
first, in initial state, the first switch S1A second switch S2Off, third switch S3Opening the first sampling capacitor C1A second sampling capacitor C2Reset to VREFThe reference voltage VREF3.3V of power supply voltage;
when an electronic cloud signal is emitted, an emitting part of the detection system can generate a starting signal: a START signal, the circuit starting to START when the START signal arrives, a first switch S1A second switch S2Opening;
thirdly, timing is started after the time-to-digital conversion module receives the starting signal, and the whole reading circuit waits for the arrival of the electronic cloud signal; the first sampling capacitor C receives the input charge when the PAD receives the input charge1Starting integration, the integrated voltage being transmitted to the high speed comparator module via the buffer module;
reference voltage V of fourth, first comparator CMP1TH1The power supply voltage is 3.3V, when electric charge is input, the output of the comparator is overturned, the comparison result is used as a STOP signal of the time-to-digital conversion module to STOP timing, and the arrival time measured by the time-to-digital conversion module is converted into a digital signal and stored in an SRAM memory;
fifth, the output signal of the buffer module is also transmitted to the second comparator CMP2, and the reference voltage VTH2Comparing and confirming whether the reading circuit reaches a saturation state; if the voltage of the input node is a negative value, the circuit is in a saturation state, and if the input node enters the saturation state, the second switch S is opened2And closing the third switch S3A first sampling capacitor C1Half of the charge in the second sampling capacitor C is injected into the second sampling capacitor C2Thereby risingHigh first sampling capacitance C1A voltage across; then the second switch S is switched on2On, the third switch S3Disconnecting the first sampling capacitor C1And a second sampling capacitor C2To the second sampling capacitor C2Carrying out reset discharge; judging the first sampling capacitor C again1Size of charge, second switch S is opened again2Closing the third switch S3Performing a first sampling on the capacitor C1A second sampling capacitor C2The transfer of charge between; the process is circulated until the circuit is out of the saturation state, namely the voltage at the input end of the buffer module rises to be more than 0V, and the initial potential of the second comparator CMP2 is recovered;
sixthly, the first switch S is switched on1A second switch S2And a third switch S3Are all disconnected, the buffer module outputs a first sampling capacitor C1The integrated voltage of (2) is recorded as a first sampling capacitance C1Number of discharges N and residual voltage V output therebysTotal amount of charge released by discharge is Q0The output residual charge is Qs＝C1VsTotal input charge amount of Q0+Qs。
Compared with the prior art, the invention has the following advantages:
1. based on the characteristic that MCP has no dark current (not dark counting) and the advantage of a high-dynamic CMOS image sensor circuit framework, the reading circuit provided by the invention adopts multiple charge transfer logic (similar to an asynchronous logic successive approximation type analog-to-digital converter based on charge redistribution), and can provide an ultra-wide input signal dynamic range.
2. The dynamic range expansion module adopted by the invention has a simple structure, can realize a larger dynamic range only by using two capacitors, and reduces the area of the pixel.
3. The invention has high system integration level, puts the judgment process of the input signal strength into the pixel for processing, does not need a complex back-end processing process, simplifies the design process of a back-end circuit, and ensures that the whole chip has simple structure, high pixel filling ratio and good chip area utilization rate.
Drawings
FIG. 1 is a schematic diagram of a front-end readout circuit of a conventional MCP detector;
FIG. 2 is a schematic structural diagram of a front-end readout circuit of the MCP detector of the invention;
FIG. 3 is a timing diagram illustrating the operation of the front-end readout circuit of the MCP detector of the present invention;
FIG. 4 shows transient operating characteristics and simulation results of embodiment 1 of the present invention;
Detailed Description
The reading circuit of the MCP neutron detector is completely compatible with a 0.18 mu m standard CMOS process, and the chip is explained in detail with the aid of the accompanying drawings and the embodiment.
Example 1
As shown in fig. 2, a front-end readout circuit of a high dynamic range MCP detector includes a signal input module, a dynamic range extension module, a buffer module (AMP), a high speed Comparator Module (CMP), a time-to-digital conversion module (TDC), and a LOGIC circuit module (LOGIC); the high-speed comparator module comprises a first comparator CMP1 and a second comparator CMP2, the comparison result of the first comparator is converted into a digital signal through a time-to-digital conversion module and then is stored in data, and the comparison result of the second comparator generates a switch control signal of the dynamic range expansion module through a logic circuit module.
The signal input module comprises two input signal electrodes, namely a PAD and a TP, wherein the PAD is an MCP electron cloud charge collecting electrode, the TP is an input signal electrode for testing, and the PAD and the TP are connected to the same output node through a Test switch Test. The signal input module comprises two electrodes of PAD and TP, which are input parts of the whole front-end readout circuit, and are metal layers which are independently defined in the CMOS process and related to the process.
Said dynamic rangeAn expansion module including a first sampling capacitor C1A second sampling capacitor C2A first switch S1A second switch S2And a third switch S3(ii) a Wherein, the first sampling capacitor C1And a second sampling capacitor C2For storing charges, and the capacitors are equal in size. C1One end is connected with the wire grounding end (GND), and the other end is connected with the S1Connected together, the node is A; c2One end is connected with the ground end of the wire, and the other end is connected with the S2Connected together, node B, S1And S2The other ends are connected to a reference potential VREF，S3Both ends of which are connected to nodes a and B, respectively. First switch S1And a second switch S2All the integrated capacitors are used as reset switches of the integrated capacitors, and the integrated capacitors are designed by adopting a complementary CMOS structure. And to further optimize the efficiency of the charge transfer, the third switch S3A Boostrap switch is adopted. In order to save area and reduce the influence of parasitic on the capacitance value, the first sampling capacitor C1And a second sampling capacitor C2The MOM capacitor structure is adopted.
The buffer module is a unity gain Amplifier (AMP), which adopts a differential input single-ended output amplifier structure, and the inverting input end and the output end of the amplifier structure are connected together, so that the closed-loop gain is 1.
The amplifier adopts a rail-to-rail amplifier structure, and can directly adopt a circuit structure of Willy Sansen in 'essence of analog integrated circuit design'.
The high-speed comparator module compares analog signals to obtain time data and a switching logic relation of a dynamic range expansion module, and comprises a five-stage Cascade amplifier and a cross-coupled comparator, wherein the cross-coupled amplifier can directly adopt a structure of P386 in CMOS analog integrated circuit design (second edition) by Phillip E.Allen. The threshold voltages of the first comparator and the second comparator are different; the first comparator is used for judging the arrival time of the input signal; the second comparator is used to determine the saturation state of the front-end sensing circuit.
The time-to-digital conversion module adopts the working principle of a vernier method and comprises a rough counting module and a fine counting module, wherein the rough counting module obtains a high-order counting result, the fine counting module obtains a low-order counting result, and the high-order counting result and the low-order counting result jointly form a digital signal representing arrival time and then are output to an SRAM for storage.
The logic module comprises a combined logic part and a two-phase non-overlapping clock generation part, wherein the combined logic part is composed of an AND gate and an OR gate, and the AND gate and the OR gate are both composed of standard logic units provided by a CMOS process. Calculating a first switch S according to the output signal of the second comparator1A second switch S2And a third switch S3And then returns to the dynamic range expansion module.
The working sequence of the embodiment is shown in fig. 3, and the working process is as follows:
the system clock used by the present invention is 320 MHz. At initial state, S1、S2Closing, S3Is turned on for two integrating capacitors C1、C2Reset to VREF. In the present invention, the reference voltage VREFWhen the supply voltage is 3.3V. When the START signal START comes, the circuit STARTs to START, the switch S1、S2And (4) opening. And after the TDC module receives the starting signal, timing is started, and the whole reading circuit waits for the arrival of the electronic cloud signal. After PAD receives input charge, C1The capacitance begins to integrate. The integrated voltage is transmitted to the high speed comparator block via the unity gain amplifier AMP. Since the reference voltage VTH1 of the arrival time determination comparator CMP1 is 3.3V, the output of the comparator will be inverted as long as there is a charge input. The comparison result is used as a STOP signal of the TDC module to STOP timing, and the arrival time measured by the TDC module is converted into a digital signal and stored in the SRAM memory.
In addition, the output signal of AMP is also transmitted to the input dynamic range comparator CMP2, and is compared with the reference voltage VTH2And comparing to confirm whether the read circuit reaches a saturation state. When the number of the electron cloud charges received by the PAD is large, the charge capacitor C is charged1Less rapid voltage dropTo a negative value, causing the amplifier AMP output to saturate, the AMP input node voltage is 0V. The reference voltage of CMP2 is set to 0V, and when the circuit reaches saturation, C1The integrated voltage at (f) is negative and the AMP output voltage remains at 0V, at which time CMP2 flips. The comparison result is passed through a LOGIC module to generate S2、S3The control signal of (2). I.e. after entering saturation state, turn on S2Closing S3Mixing C with1Half of the charge in (1) is injected into (C)2Thereby raising C1The voltage of (c). Then the S is added2Conduction, S3Break, open C1And C2Is connected to C2Reset discharge is performed. Judging again C1If the voltage of the input node is still negative, the circuit is still in a saturation state, and S is turned on again2Closing S3To proceed with C1、C2To transfer charge between them. This is repeated until the circuit is out of saturation, the AMP input voltage rises above 0V, and CMP2 returns to the initial potential. Finally, all switches S are connected1、S2、S3All are off, buffer module output C1The voltage is integrated. Recording capacitance C1Number of discharges N and residual voltage V output therebys(further converting to a digital signal), the input charge Q ═ C can be obtained1×(VREF-VS)×2N。
Fig. 4 shows simulation results of the circuit front-end simulation part, and the horizontal axis shows simulation time in ns. In simulation, the input charge amount is set to 1 × 107Integrating capacitor C in electronic pixel circuit1、C2Are all 200 fF. According to Q ═ CV, the charge amount of the conventional circuit reaches 4.125 × 10 at an input capacitance of 200fF6When the circuit is in use, the circuit reaches a saturation state. The clock of the whole system is 320MHz, and the interval between two reset signals is 20 ns. To ensure the utilization of C2To C1During the discharging process, the charge is not lost, S2、S3The control switch signal of (2) needs to be two-phase non-overlapping clocks. Due to C1、C2The capacitors are of the same size, so that the charge transfer amount per time is half of the total input charge,as can be seen from FIG. 4, the input charge is 107The electrons need to be discharged twice, and the input voltage is a positive value. Simulation shows that the input voltage is finally kept at 1.3838V, the residual charging voltage of the capacitor is 2.026V, and the initial charging voltage is 22X 2.013 ═ 8.042V (ideally, 8V).

Claims (7)

1. A front-end reading circuit of a high dynamic range MCP detector is characterized by comprising a signal input module, a dynamic range expansion module, a buffer module, a high-speed comparator module, a time-to-digital conversion module and a logic circuit module; the photoelectric current signal from the detector enters a front-end reading circuit through a signal input module, then is subjected to integration and dynamic range expansion processing through a dynamic range expansion module, a voltage signal after integration is subjected to buffering processing through a buffer module and then is transmitted to a high-speed comparator module, the high-speed comparator module comprises a first comparator CMP1 and a second comparator CMP2, a comparison result of the first comparator is converted into a digital signal through a time-to-digital conversion module and then is stored in data, and a comparison result of the second comparator generates a switching control signal of the dynamic range expansion module through a logic circuit module;
the dynamic range expansion module comprises a first sampling capacitor C1A second sampling capacitor C2A first switch S1A second switch S2And a third switch S3(ii) a Wherein, the first sampling capacitor C1And a second sampling capacitor C2For storage of electric charge, C1One end is connected with the ground end of the wire, and the other end is connected with the S1Connected together, the node is A; c2One end is connected with the ground end of the wire, and the other end is connected with the S2Connected together, node B, S1And S2The other ends are connected to a reference potential VREF，S3Both ends of which are connected to nodes a and B, respectively.
2. The front-end readout circuit of a high dynamic range MCP detector of claim 1, wherein said signal input module comprises two input signal electrodes PAD and TP, wherein PAD is the MCP electron cloud charge collection electrode and TP is the input signal electrode for testing, both of which are connected to the same output node through the Test switch Test.
3. A front-end readout circuit for a high dynamic range MCP detector, as claimed in claim 1, wherein said buffer module is a unity gain amplifier, using a differential input single-ended output amplifier configuration, with inverting inputs connected to the output to provide a closed loop gain of 1.
4. A front-end readout circuit for a high dynamic range MCP detector according to claim 1, wherein said first comparator and said second comparator have different threshold voltages; the first comparator is used for judging the arrival time of the input signal; the second comparator is used to determine the saturation state of the front-end sensing circuit.
5. A high dynamic range MCP detector front-end readout circuit according to claim 1, wherein said time-to-digital conversion module comprises a coarse counting module for coarse counting of arrival times and a fine counting module for fine counting of arrival times for resolution enhancement and outputting the counting result to the sram for storage.
6. The front-end readout circuit of MCP detector as claimed in claim 1, wherein said logic circuit block comprises a combinational logic part consisting of an and gate or an or gate and a two-phase non-overlapping clock generation part, and the first switch S is calculated from the output signal of the second comparator1A second switch S2And a third switch S3And then returns to the dynamic range expansion module.
7. A method for reading out a front-end readout circuit of an MCP detector according to claim 1, characterized by the specific steps of:
first, in initial state, the first switch S1A second switch S2Off, third switch S3Opening the first sampling capacitor C1A second sampling capacitor C2Reset to VREFReference voltage VREF3.3V of power supply voltage;
when an electronic cloud signal is emitted, an emitting part of the detection system can generate a starting signal: a START signal, the circuit starting to START when the START signal arrives, a first switch S1A second switch S2Opening;
thirdly, timing is started after the time-to-digital conversion module receives the starting signal, and the whole reading circuit waits for the arrival of the electronic cloud signal; the first sampling capacitor C receives the input charge when the PAD receives the input charge1Starting integration, and transmitting the integrated voltage to a high-speed comparator module through a buffer module;
reference voltage V of fourth, first comparator CMP1TH1The voltage is 3.3V, when electric charge is input, the output of the comparator is overturned, the comparison result is used as a STOP signal of the time-to-digital conversion module to STOP timing, and the arrival time measured by the time-to-digital conversion module is converted into a digital signal and stored in an SRAM memory;
fifth, the output signal of the buffer module is also transmitted to the second comparator CMP2, and the reference voltage VTH2Comparing and confirming whether the reading circuit reaches a saturation state; if the voltage of the input node is a negative value, the circuit is in a saturation state, and if the input node enters the saturation state, the second switch S is opened2And closing the third switch S3A first sampling capacitor C1Half of the charge in the second sampling capacitor C is injected into the second sampling capacitor C2Thereby raising the first sampling capacitance C1A voltage across; then the second switch S is switched on2On, the third switch S3Disconnecting the first sampling capacitor C1And a second sampling capacitor C2To the second sampling capacitor C2Carrying out reset discharge; judging the first sampling capacitor C again1Magnitude of electric charge, beating againOpen the second switch S2Closing the third switch S3Performing a first sampling on the capacitor C1A second sampling capacitor C2The transfer of charge between; the process is circulated until the circuit is out of the saturation state, namely the voltage at the input end of the buffer module rises to be more than 0V, and the initial potential of the second comparator CMP2 is recovered;
sixthly, the first switch S is switched on1A second switch S2And a third switch S3Are all disconnected, the buffer module outputs a first sampling capacitor C1The integrated voltage of (2) is recorded as a first sampling capacitance C1Number of discharges N and residual voltage V output therebysThe total charge released per discharge is Q0The output residual charge is Qs＝C1VsTotal input charge amount of Q0+Qs。
CN201810605557.6A 2018-06-13 2018-06-13 Front-end reading circuit of high dynamic range MCP detector and reading method thereof Expired - Fee Related CN108848326B (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1568532A (en) * 2001-10-09 2005-01-19 Itt制造企业公司 Intensified hybrid solid-state sensor
CN102307046A (en) * 2011-06-09 2012-01-04 中国科学院西安光学精密机械研究所 Time-resolved photon counting imaging system and method
CN105609511A (en) * 2014-11-21 2016-05-25 中国科学院微电子研究所 Single photon imaging detector and manufacturing method thereof
CN106092339A (en) * 2016-06-01 2016-11-09 南京邮电大学 A kind of simulation counting circuit for single-photon detector
CN107613230A (en) * 2017-08-25 2018-01-19 电子科技大学 High-resolution large dynamic range digital read-out device and its reading method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1703301A1 (en) * 2003-04-10 2006-09-20 Japan Science and Technology Agency Radiation detector

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1568532A (en) * 2001-10-09 2005-01-19 Itt制造企业公司 Intensified hybrid solid-state sensor
CN102307046A (en) * 2011-06-09 2012-01-04 中国科学院西安光学精密机械研究所 Time-resolved photon counting imaging system and method
CN105609511A (en) * 2014-11-21 2016-05-25 中国科学院微电子研究所 Single photon imaging detector and manufacturing method thereof
CN106092339A (en) * 2016-06-01 2016-11-09 南京邮电大学 A kind of simulation counting circuit for single-photon detector
CN107613230A (en) * 2017-08-25 2018-01-19 电子科技大学 High-resolution large dynamic range digital read-out device and its reading method

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