CN111246136B - CMOS Image Sensor Pixel Readout Acceleration Circuit - Google Patents

Abstract

The invention discloses a pixel readout acceleration circuit of a CMOS image sensor, which includes a register DFF1, the CLK end of the register DFF1 is connected to the CLK end of the register DFF2 and is also connected to a comparator A, and the Q end of the register DFF1 is connected to the MOS transistor M1. The gate is connected, the D terminal of the register DFF1 is connected to the emitter of the MOS transistor M1, the collector of the MOS transistor M1 is connected to the collector of the MOS transistor M4, the gate of the MOS transistor M4 is connected to the Q terminal of the register DFF2, and the The D terminal and the emitter of the MOS transistor M1 are both connected to the power supply VCC, and at the same time are internally connected to the CMOS image sensor to be accelerated. The present invention solves the problem that the CMOS image sensor in the prior art cannot achieve fast settling time in the face of large parasitic capacitance.

Description

CMOS Image Sensor Pixel Readout Acceleration Circuit

technical field

The invention belongs to the technical field of readout circuits, and in particular relates to a pixel readout acceleration circuit of a CMOS image sensor.

Background technique

With the development of CMOS technology, a series of advantages such as low cost, high integration, process compatibility, low power consumption, high speed, random reading of image information, and small size of CMOS image sensors have gradually emerged, making them suitable for use in security monitoring, Digital cameras, scanners, mobile phones, computer cameras, automobiles, medical images, aerospace and other fields have a wide range of applications, with a very large consumer group, and the market prospect is bright.

However, in some cases with extremely high resolution requirements, increasing the number of pixel units will increase the area of the entire chip, thereby increasing the parasitic capacitance of the output node of a single pixel unit. This is particularly unfavorable for signal readout, and one of the main reasons is that when the parasitic capacitance value of the output node of the pixel unit is large, it will significantly affect the establishment process of the output signal. The following will focus on analyzing the influence of parasitic capacitance on the settling process of the output signal.

At present, mainstream CMOS image sensors all use source followers as buffers. Figure 1 shows a schematic diagram of the sensor structure considering parasitic capacitance and parasitic resistance. The basic principle is that when the reset signal RESET is high, each The output voltage VIN of the photodiode (PD) in the pixel unit is reset to a high level. When the reset signal RESET is a low level, the circuit in the pixel unit enters the integration stage. The specific process is based on the photodiode irradiated. The size of the light intensity on the PD, the corresponding photocurrent will be formed in the photodiode PD, and the charge on the parasitic capacitance at the output end of the photodiode PD will be continuously extracted, and the voltage VPD at the output end of the photodiode PD will gradually decrease. When the integration phase is completed, the photoelectric The photocurrent is no longer generated in the diode PD, the output voltage V _IN of the photodiode PD remains unchanged, and then the row selection signal SEL in each pixel unit is turned on in turn, and the size of V _IN in each pixel unit can be read through V _OUT . However, due to the parasitic capacitance at the output node, V _OUT does not rapidly rise to the output of the source follower, but there is a charging process for the parasitic capacitance, and the charging current in this process is only the source follower drain The difference between the current I1 and the tail current bias I2, so the parasitic capacitance can significantly reduce the settling time of _VOUT . Figure 2 presents a schematic diagram of this phenomenon.

Therefore, how to compress the settling time of the output signal of the pixel unit has become an unavoidable problem in CMOS image sensor technology. High frame rates will never be achieved. CMOS image sensors will inevitably have a certain degree of compromise between the array scale and high frame rate, and the application of CMOS image sensors is also greatly limited.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a pixel readout acceleration circuit of a CMOS image sensor, which solves the problem that a fast settling time cannot be achieved in a CMOS image sensor in the prior art when faced with a large parasitic capacitance.

The technical scheme adopted in the present invention is that the pixel readout acceleration circuit of the CMOS image sensor includes a register DFF1, the CLK end of the register DFF1 is connected to the CLK end of the register DFF2 and is also connected to the comparator A, and the Q end of the register DFF1 is connected to the MOS The gate of the tube M1 is connected, the D terminal of the register DFF1 is connected to the emitter of the MOS tube M1, the collector of the MOS tube M1 is connected to the collector of the MOS tube M4, and the gate of the MOS tube M4 is connected to the Q terminal of the register DFF2 connected, the emitter of the MOS tube M4 is grounded, the D terminal of the register DFF2 is grounded, the MOS tube M1 is a P-type MOS tube, and the MOS tube M4 is an N-type MOS tube;

The D terminal of the register DFF1 and the emitter of the MOS transistor M1 are both connected to the power supply VCC, and at the same time are internally connected to the CMOS image sensor to be accelerated. The comparator A is connected between the power supply VCC of the CMOS image sensor or the ground and the output node, The function of fast setting of the parasitic capacitance of the output node is realized, and the setting value of the capacitance is determined by the preset voltage value of the comparator.

The present invention is also characterized in that,

Register DFF1 is a rising edge trigger, and register DFF2 is a falling edge trigger.

A MOS tube M2 and a MOS tube M3 are also set between the register DFF1 and the register DFF2, wherein the MOS tube M2 is a P-type MOS tube, and the MOS tube M3 is an N-type MOS tube. The specific connection form is: the emitter of the MOS tube M2 and the The collector of the MOS transistor M1 is connected, the gate of the MOS transistor M2 is connected to the control signal SampleR_EN, the collector of the MOS transistor M2 is connected to the collector of the MOS transistor M3, and the emitter of the MOS transistor M3 is connected to the MOS transistor M4. The collector is connected, the gate of the MOS transistor M3 is connected to the control signal SampleS_EN, and the collector of the MOS transistor M2 and the collector of the MOS transistor M3 are also connected to the output signal V _OUT at the same time.

Comparator A is a comparator with a three-state gate structure. The clock signal of the register is output through the comparator. The negative end of the comparator A is connected to the reference signal VC, and the positive end of the comparator A is connected to the input signal VIN. The Q output terminal is simultaneously connected to the CLK terminal of the register DFF1 and the CLK terminal of the register DFF2.

The internal structure of the CMOS image sensor to be accelerated is: including an N-type MOS transistor M5 and an N-type MOS transistor M6 connected between the power supply VCC and the parasitic resistance R in turn, the collector of the N-type MOS transistor M5 is connected to the power supply VCC, and the N-type MOS transistor M5 is connected to the power supply VCC. The gate of the MOS transistor M5 is connected to the emitter of the N-type MOS transistor M7, the N-type MOS transistor M7 is used as a reset signal, the collector of the N-type MOS transistor M7 is connected to the power supply VCC at the same time, and the emitter of the N-type MOS transistor M7 is connected to a diode. After grounding, the emitter of the N-type MOS transistor M5 is connected to the collector of the N-type MOS transistor M6, the emitter of the N-type MOS transistor M6 is connected to one end of the parasitic resistance R, and the other end of the parasitic resistance R is connected to the ground and the output Between nodes, parasitic capacitance C is located between the output node and ground.

The beneficial effect of the invention is that the pixel readout acceleration circuit of the CMOS image sensor can charge and discharge the parasitic capacitance of the output node by using the power supply or the ground. When the reset signal is read, the acceleration mechanism is to charge the parasitic capacitance; When integrating the signal, the acceleration mechanism is to discharge the parasitic capacitance; by introducing a comparator-controlled switch structure between the power supply or the ground and the output node, the function of quickly setting the parasitic capacitance of the output node is realized, and the capacitance setting value is compared by It is determined by the preset voltage value of the comparator; the switch structure controlled by the comparator is realized by the register and the tri-state gate structure. The clock signal of the register is output by the comparator, and the edge-triggered characteristic of the register is used to cooperate with the control signal of the tri-state gate to realize The control of the acceleration mechanism is embodied in the control of the end of the acceleration process.

Description of drawings

Figure 1 is a schematic diagram of the sensor structure considering parasitic capacitance and parasitic resistance;

FIG. 2 is a schematic diagram of the influence of parasitic capacitance on the output signal;

3 is a schematic diagram of a circuit for accelerating the readout speed of a sensor pixel unit;

4 is a circuit specific structure for accelerating the readout speed of the sensor pixel unit;

Fig. 5 is the instantiation application of the present invention;

FIG. 6 is a schematic diagram of a control signal.

Detailed ways

The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

A CMOS image sensor pixel readout acceleration circuit of the present invention, the structure is shown in Figures 4 and 5, including a register DFF1, the CLK end of the register DFF1 is connected to the CLK end of the register DFF2, and is also connected to the comparator A. The register DFF1 The Q terminal is connected to the gate of the MOS tube M1, the D terminal of the register DFF1 is connected to the emitter of the MOS tube M1, the collector of the MOS tube M1 is connected to the collector of the MOS tube M4, and the gate of the MOS tube M4 is connected to the The Q terminal of the register DFF2 is connected, the emitter of the MOS tube M4 is grounded, and the D terminal of the register DFF2 is grounded, the MOS tube M1 is a P-type MOS tube, and the MOS tube M4 is an N-type MOS tube;

The D terminal of the register DFF1 and the emitter of the MOS transistor M1 are both connected to the power supply VCC, and at the same time are internally connected to the CMOS image sensor to be accelerated. The comparator A is connected between the power supply VCC of the CMOS image sensor or the ground and the output node, The function of fast setting of the parasitic capacitance of the output node is realized, and the setting value of the capacitance is determined by the preset voltage value of the comparator.

Register DFF1 is a rising edge trigger, and register DFF2 is a falling edge trigger.

A MOS tube M2 and a MOS tube M3 are also set between the register DFF1 and the register DFF2, wherein the MOS tube M2 is a P-type MOS tube, and the MOS tube M3 is an N-type MOS tube. The specific connection form is: the emitter of the MOS tube M2 and the The collector of the MOS transistor M1 is connected, the gate of the MOS transistor M2 is connected to the control signal SampleR_EN, the collector of the MOS transistor M2 is connected to the collector of the MOS transistor M3, and the emitter of the MOS transistor M3 is connected to the MOS transistor M4. The collector is connected, the gate of the MOS transistor M3 is connected to the control signal SampleS_EN, and the collector of the MOS transistor M2 and the collector of the MOS transistor M3 are also connected to the output signal V _OUT at the same time.

Comparator A is a comparator with a three-state gate structure. The clock signal of the register is output through the comparator. The negative end of the comparator A is connected to the reference signal VC, and the positive end of the comparator A is connected to the input signal VIN. The Q output terminal is simultaneously connected to the CLK terminal of the register DFF1 and the CLK terminal of the register DFF2.

As shown in FIG. 3 , the internal structure of the CMOS image sensor to be accelerated is: including an N-type MOS transistor M5 and an N-type MOS transistor M6 connected between the power supply VCC and the parasitic resistance R in sequence, and the collector of the N-type MOS transistor M5 is connected to the N-type MOS transistor M5. The power supply VCC is connected, the gate of the N-type MOS transistor M5 is connected to the emitter of the N-type MOS transistor M7, the N-type MOS transistor M7 is used as a reset signal, the collector of the N-type MOS transistor M7 is connected to the power supply VCC at the same time, and the N-type MOS transistor M7 is connected to the power supply VCC at the same time. The emitter of M7 is connected to the diode and then grounded, the emitter of the N-type MOS transistor M5 is connected to the collector of the N-type MOS transistor M6, the emitter of the N-type MOS transistor M6 is connected to one end of the parasitic resistance R, and the other end of the parasitic resistance R is connected. One end is connected between the ground and the output node, and the parasitic capacitance C is located between the output node and the ground.

Figure 3 shows a CMOS image sensor suitable for a pixel readout acceleration circuit of a CMOS image sensor. There are parasitic resistance R and parasitic capacitance C at the output node. According to the idea proposed by the present invention, there is a control circuit between the two points A and B, which is controlled by the gating signal to charge or discharge the parasitic capacitance of the output node with the power supply or the ground. When performing correlated double sampling, when reading the reset signal, use the power supply to charge the parasitic capacitance of the output node; when reading the integral signal, in order to avoid overcharging the parasitic capacitance, the actual signal is covered, and then the parasitic capacitance of the output node is overwritten. Discharge is performed to ensure the accuracy of signal acquisition. Since the present invention does not make any changes to the structure of the pixel unit itself, but uses a new technology on the readout circuit outside the pixel unit to speed up the signal establishment time, parameters such as the fill factor and photoelectric characteristics of the pixel are not affected.

The pixel readout acceleration circuit of the CMOS image sensor proposed by the present invention includes a voltage comparator for detecting the established state of the column line, a D register DFF1 triggered by a rising edge, a D register DFF2 triggered by a falling edge, and a tri-state gate structure. The structure is shown in Fig. 4 shown.

FIG. 5 is a combination diagram of the structure proposed by the present invention applied to a CMOS image sensor. In this circuit structure, the initial state of the comparator is a low level. DFF1 is a rising edge trigger, and DFF2 is a falling edge trigger. SampleR_EN and SampleS_EN are two control signals. SampleR_EN is gated when the reset signal is read, and SampleS_EN is gated when the integral signal is read. The schematic diagram of its logic control is given in FIG. 6 . The comparator input terminals are respectively connected to the output signal V _OUT and the reference signal VC. In the initial state, the value of V _OUT is low due to the influence of the parasitic capacitance C. Do the first signal acquisition, when the reset signal is read, M3 and M4 are turned off, the register DFF1 is reset, and the M1 tube is turned on. SampleR_EN turns on the M2 tube following the strobe signal SEL. A path is established between the power supply and the parasitic capacitance C, and the parasitic capacitance C is charged. When V _OUT is higher than VC1, the comparator is turned over, the output of register DFF1 is turned over, and the M1 tube is turned off. The acceleration process ends, and the parasitic capacitance C is charged by the source follower's own current in the subsequent process. When the second signal acquisition is performed and the integrated signal is read, the potential of V _OUT is relatively high in the initial state due to the aforementioned operations, so the parasitic capacitance C is discharged in this process. At this time, M1 and M2 are turned off, the register DFF2 is set, and the M4 tube is turned on. SampleS_EN turns on the M3 tube following the strobe signal SEL, establishes a path between the ground and the parasitic capacitance C, and discharges the parasitic capacitance C. When V _OUT is lower than V _C2 , the comparator flips, turning off M4. The acceleration process ends, and the parasitic capacitance C is charged again by the source follower's own current in the subsequent process. Due to the above operations, when the source follower itself charges the parasitic capacitance, the required charging voltage is small, so the process takes a short time.

Regarding the selection of the voltage value V _C , in order to improve the establishment speed of the output signal as much as possible, the value should be as close to the output value as possible. But considering that the value of V _C is larger, it will cover the actual collected signal. The given method of _VC in the present invention is to use the signal strengths received by adjacent pixel units to be similar, and the selection of _VC can be obtained by dividing the output of adjacent pixel units. In the present invention, on the premise of not increasing the area of the pixel unit, the readout circuit can speed up the establishment process of the output signal of the pixel unit, thereby increasing the frame rate of the sensor.

Claims (2)

1. The CMOS image sensor pixel reading acceleration circuit is characterized by comprising a register DFF1, wherein the CLK end of a register DFF1 is connected with the CLK end of a register DFF2 and then connected with a comparator A, the Q end of the register DFF1 is connected with the grid of a MOS tube M1, the D end of a register DFF1 is connected with the emitter of a MOS tube M1, the collector of the MOS tube M1 is connected with the collector of the MOS tube M4, the grid of the MOS tube M4 is connected with the Q end of the register DFF2, the emitter of the MOS tube M4 is grounded, the D end of the register DFF2 is grounded, the MOS tube M1 is a P-type MOS tube, and the MOS tube M4 is an N-type MOS tube;

   the D end of the register DFF1 and an emitter of the MOS tube M1 are both connected with a power supply VCC and are simultaneously connected with the interior of a CMOS image sensor to be accelerated, a collector of the N-type MOS tube M5 is connected with the power supply VCC, a collector of the N-type MOS tube M7 is simultaneously connected with the power supply VCC, the comparator A is connected between the power supply VCC or ground of the CMOS image sensor and an output node to realize the effect of quickly setting the parasitic capacitance of the output node, and the capacitance setting value is determined by the preset voltage value of the comparator;

   the register DFF1 is triggered by a rising edge, and the register DFF2 is triggered by a falling edge;

   still be provided with MOS pipe M2 and MOS pipe M3 between register DFF1 and the register DFF2, wherein, MOS pipe M2 is P type MOS pipe, and MOS pipe M3 is N type MOS pipe, and concrete connection form is: the emitter of MOS transistor M2 is connected with the collector of MOS transistor M1, the gate of MOS transistor M2 is connected with control signal SampleR _ EN, the collector of MOS transistor M2 is connected with the collector of MOS transistor M3, the emitter of MOS transistor M3 is connected with the collector of MOS transistor M4, the gate of MOS transistor M3 is connected with control signal SampleS _ EN, the collector of MOS transistor M2 and the collector of MOS transistor M3 are simultaneously connected with output signal V_OUT；

   The comparator A is a comparator with a tri-state gate structure, a clock signal serving as a register is output through the comparator, and the negative end of the comparator A and a reference signal V_CConnected, the positive terminal of the comparator A and the input signal V_INAnd the Q output end of the comparator A is simultaneously connected with the CLK end of the register DFF1 and the CLK end of the register DFF 2.
2. 2. The CMOS image sensor pixel readout acceleration circuit of claim 1, wherein the CMOS image sensor internal structure to be accelerated is: the N-type MOS tube-N-type power supply circuit comprises an N-type MOS tube M5 and an N-type MOS tube M6 which are sequentially connected between a power supply VCC and a parasitic resistor R, wherein a collector of the N-type MOS tube M5 is connected with the power supply VCC, a grid of the N-type MOS tube M5 is connected with an emitter of the N-type MOS tube M7, the N-type MOS tube M7 is used as a reset signal, a collector of the N-type MOS tube M7 is simultaneously connected with the power supply VCC, an emitter of the N-type MOS tube M7 is connected with a diode and then grounded, an emitter of the N-type MOS tube M5 is connected with a collector of the N-type MOS tube M6, an emitter of the N-type MOS tube M6 is connected with one end of the parasitic resistor R, the other end of the parasitic resistor R is connected to an output node, and Vb and a parasitic capacitor C are connected between the output node and the ground in parallel.

Images