CN206294149U - A kind of simulation counting circuit of the count range high for being applied to SPAD detectors - Google Patents
A kind of simulation counting circuit of the count range high for being applied to SPAD detectors Download PDFInfo
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- CN206294149U CN206294149U CN201621354347.7U CN201621354347U CN206294149U CN 206294149 U CN206294149 U CN 206294149U CN 201621354347 U CN201621354347 U CN 201621354347U CN 206294149 U CN206294149 U CN 206294149U
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Abstract
The utility model discloses a kind of simulation counting circuit of the count range high for being applied to SPAD detectors.The circuit counts electric capacity C, 1 resistance R and 15 metal-oxide-semiconductors and constitutes by one, wherein NMOS tube MN3 and MN4, PMOS MP6, MP7, MP8 and MP9 and resistance R constitutes a Cascode biasing circuit, for counting circuit provides biasing, the biasing circuit is also for the output follower of counting circuit provides a current source load simultaneously, ensure that the linear convergent rate of counter, the biasing circuit also provides a bias voltage for higher level for current limliting PMOS MP2, and an excessive effect of limitation conducting electric current is served on the branch road that electric capacity charges is counted.The utility model also proposes a kind of method that simulation counting circuit using the above-mentioned count range high for being applied to SPAD detectors is counted, and it includes reseting stage, counting stage and reading stage three and stage.The utility model can reduce capacity area, and count range is big, and the utility model also has the advantages that the fill factor of pixel cell is high.
Description
Technical field
The utility model proposes a kind of linear analogue counting circuit based on snowslide rising edge of a pulse flip-flop number and side
Method, belongs to single photon detection technical field.
Background technology
SPAD (Single Photon Avalanche Diode) is single-photon avalanche photodiode.In photodetection
In field, traditional photomultiplier (PMT) can not be satisfied with the detection under high speed low light condition, tradition imaging
Technology receives certain limitation in terms of image taking speed and pixel sensitivity, then starts solid state photomultiplier pipe occur, i.e.,
Single photon avalanche diode detector.In recent years, high density, high integration are produced using modern standard CMOS process
SPAD detector arrays turn into the development trend of this single photon avalanche diode detector.
Traditional counting circuit takes the mode of digital counting, and directly the snowslide pulse that SPAD is produced is processed, and supplies
Subsequent conditioning circuit carries out Digital Signal Processing.Although digital counting circuit has more preferable noise suppressed, detectivity and low
The characteristics such as noise, but its shortcoming is complex structure, it is necessary to up to a hundred transistors, and area occupied is big, has had a strong impact on pixel
The fill factor of unit.In order to effectively reduce the area of reading circuit, fill factor is improved, it is necessary to which research is counted using simulation
Several methods is counted to snowslide pulse.
Most areas of pixel cell domain but the counting electric capacity in simulative counter generally accounts for.Count range
Influenceed larger by capacity area, count range is directly proportional to the size of capacitance, i.e., be directly proportional to the area of electric capacity.Want into
The area that one step reduces counting circuit counts the area of electric capacity domain it is necessary to reduce, but can so cause the reduction of count range.
Therefore, in the SPAD detector applications counted using simulation, it is necessary to solve to count electric capacity and chip area and count range it
Between contradictory problems.
Utility model content
For traditional analog counting circuit count range by the problem for counting electric capacity and the pulsewidth restriction of input avalanche signal, this
Utility model proposes a kind of simulation counting circuit of the count range high for being applied to SPAD detectors.
Specific technical scheme is a kind of simulation counting circuit of the count range high for being applied to SPAD detectors, the circuit
Electric capacity C, 1 resistance R and 15 metal-oxide-semiconductors are counted by one to constitute, wherein NMOS tube MN3 and MN4, PMOS MP6, MP7, MP8
A Cascode biasing circuit is constituted with MP9 and resistance R, for counting circuit provides biasing, while the biasing circuit is also meter
The output follower of number circuit provides a current source load, it is ensured that the linear convergent rate of counter, and the biasing circuit is also
Current limliting PMOS MP2 provides a bias voltage for higher level, and a limit is served on the branch road that electric capacity charges is counted
The excessive effect of conducting electric current processed, PMOS MP0 is electric charge ascending pipe, is signal input switch, and its grid connects a pulse letter
Number in, source electrode meets supply voltage VDD, and its drain electrode is connected with the source electrode of PMOS MP1 pipes；MP1 is isolated tube, and its grid connects power supply
Voltage VDD, its drain electrode is connected together with the source electrode of current limliting PMOS MP2；MP2 is current limiting tube, the voltage bias that its grid connects by
Cascode biasing circuits are provided, and its effect is the size that the moment charged in electric capacity limits charging current, PMOS MP2's
Drain electrode connects the top crown of electric capacity C；NMOS tube MN0 is a reset switch, and the grid of MN0 meets a reset signal Clear, is drained
The positive plate for counting electric capacity C is connect, source electrode connects the bottom crown for counting electric capacity, i.e. GND；NMOS tube MN1, MN2, MN3 and MN4 are constituted
NMOS tube current mirror；PMOS MP4 and MP5 constitute pmos current mirror, and the effect of the two current mirrors is to bias Cascode
The bias current of circuit be delivered to output end out where branch road, final PMOS MP4 is equivalent to follower PMOS MP3's
Current source load；PMOS MP3 is voltage follower, is responsible for the last voltage signal by counting electric capacity and is delivered to output end
Out, as the output result for counting.
Above-mentioned counting circuit is made up of PMOS MP0, MP1, MP2 and electric capacity C.
The utility model has the advantage that：
1. the utility model can reduce capacity area, and count range is big：Use the counting electric capacity of 250pF can be with
The counting of 1600 times is realized, because the utility model is using the method for rising edge flip-flop number, in rising edge of a pulse each time, meter
Number electric capacity increases the electric charge of denier.Therefore can be while counting capacity area be reduced, count range does not have significantly drop
It is low.
2. circuit of the present utility model can realize rail-to-rail level count range：By simple biasing circuit by electricity
Stream source as output follower load, output resistance is equivalent to infinity, therefore output level will not be subject to output loading
Influence.
3. the fill factor of pixel cell of the present utility model is high：The utility model replaces tradition using simulation counting circuit
Digital counting circuit, due to simulation counting circuit area it is small, be conducive to improve SPAD detector arrays fill factor.
Brief description of the drawings
Fig. 1 is the linear analogue counting circuitry of rising edge flip-flop number.
Fig. 2 is the working timing figure of the linear analogue counting circuit of rising edge flip-flop number.
Fig. 3 is the simulation result figure of the linear analogue counting circuit of rising edge flip-flop number.
Fig. 4 is the domain of the linear analogue counting circuit of rising edge flip-flop number.
Specific embodiment
The utility model patent is described in further detail below in conjunction with Figure of description.
The scheme that the circuit is charged using electric capacity, real-time monitoring is carried out to the electric charge on electric capacity, can finally by calculating
The quantity of the photon to be detected.In order to realize linear analogue counting circuit in larger dynamic range to counting electric capacity
Charging, after the rising edge of the method that the utility model takes rising edge of a pulse flip-flop number, i.e. each avalanche signal arrives, will
Increase the unit charge of denier on electric capacity is counted.Using the method for this rising edge flip-flop number so that electric capacity is only in arteries and veins
The extremely short moment inside counting rushed after rising edge arrives, so that the unit quantity of electricity very little that electric capacity charges each time, so that
Realize the counting in large dynamic range.
Based on the principle that electric capacity both end voltage can not be mutated, the utility model devises a kind of based on the linear of electric capacity charging
Simulation counting circuit, its physical circuit is as shown in Figure 1.The circuit has used one to count electric capacity C, 1 resistance R and 15 MOS
Pipe.Wherein NMOS tube MN3 and MN4, PMOS MP6, MP7, MP8 and MP9 and resistance R constitute a simple Cascode (common source
Common grid) biasing circuit, for counting circuit provides biasing.This biasing circuit provides an electricity for the output follower of counting circuit
The load of stream source (is provided) by MP4, it is ensured that the linear convergent rate of counter.In addition.Biasing circuit is also for current limliting PMOS MP2 is provided
One bias voltage of higher level, serves an excessive work of limitation conducting electric current on the branch road that electric capacity charges is counted
With.PMOS MP0 is electric charge ascending pipe, is signal input switch, and its grid meets a pulse signal in, and source electrode connects supply voltage
VDD, its drain electrode is connected with the source electrode of PMOS MP1 pipes；MP1 is isolated tube, and its grid meets supply voltage VDD, and it drains and limit
The source electrode of stream PMOS MP2 is connected together；MP2 is current limiting tube, and the voltage bias that its grid connects are carried by Cascode biasing circuits
For its effect is the size that the moment charged in electric capacity limits charging current, and the drain electrode of PMOS MP2 connects the upper pole of electric capacity C
Plate；NMOS tube MN0 is a reset switch, and the grid of MN0 meets a reset signal Clear, and drain electrode connects the positive pole for counting electric capacity C
Plate, source electrode connects the bottom crown for counting electric capacity, i.e. GND；NMOS tube MN1, MN2, MN3 and MN4 constitute NMOS tube current mirror；PMOS
MP4 and MP5 constitutes pmos current mirror.The effect of the two current mirrors is to transmit the bias current of Cascode biasing circuits
Branch road to where output end out, final PMOS MP4 takes electric current equivalent to the current source load of follower PMOS MP3
Load is made in source can improve the linearity of count results, realize rail-to-rail level count range；PMOS MP3 is voltage follow
Device, is responsible for the last voltage signal by counting electric capacity and is delivered to output end out, as the output result for counting.
The operation principle of counting circuit of the present utility model can be divided into 3 stages with process, as shown in Fig. 2 being respectively
Reseting stage, counting stage and reading stage.Reseting stage is the preparatory stage of photon detection, before snowslide pulse arrival,
Reset signal Clear is high level, and signal input switch MP0 is off, using reset switch Clear by the original of electric capacity
Some charge discharges to GND, to wait the arrival of counting stage.For counting stage, single-photon avalanche diode photodetection
Device starts to detect optical signal, produce snowslide pulse input signal, snowslide pulse signal in when low level, MP0
It is conducting, and its channel resistance is very small.Therefore the drain electrode of MP0, with source potential close to identical, is supply voltage.Work as snowslide
When one rising edge of pulse signal arrives, due to the principle that the both end voltage of electric capacity can not be mutated, the voltage at MP0 two ends can not
Mutation, therefore during the grid voltage rising of MP0, its drain voltage is also increased, and is returned to again by an of short duration moment
Normal condition.Due to there was only transient switching, and current limiting metal-oxide-semiconductor MP2 limits the size of conducting electric current, counts what electric capacity was obtained
The quantity of electric charge is considerably less, counts electric capacity and is just completed in a flash at this and charges and count.In the stage of reading, SPAD is completed to monochromatic light
The detection of subsignal, signal input switch MP0 disconnects, and voltage follower MP3 starts the voltage on the top crown to counting electric capacity C
Read, the number of photons that SPAD is detected during detecting is can obtain by calculating.The utility model proposes it is this
Simulation reading method count range is big, and circuit structure is simple, the fill factor of pixel cell will not be reduced, while will not also improve
The cost of circuit manufacture.Based on the principle that electric capacity both end voltage can not be mutated, the utility model proposes this based on snowslide arteries and veins
The linear analogue counting circuit and method of rising edge flip-flop number are rushed, the method has count range higher, count electric capacity and account for
With area it is small the advantages of.
As shown in figure 1, being the linear analogue counting circuitry of the utility model rising edge flip-flop number.The circuit is by 1
Electric capacity C, 1 resistance R and 15 metal-oxide-semiconductors are constituted, and are specifically included：PMOS MP0, MP1, MP2, MP3, MP4, MP5, MP6, MP7,
MP8, MP9, NMOS tube MN0, MN1, MN2, MN3, MN4.Wherein PMOS MP0 is electric charge ascending pipe, snowslide pulse input signal
It is input into from the grid of MP0, its source electrode meets VDD, the source electrode that drain electrode meets PMOS MP1 is connected together；MP1 is isolated tube, its grid
Supply voltage VDD is met, before the rising edge of snowslide pulse signal arrives, the voltage difference of its grid and source electrode remains 0V,
State in cut-off so that the counting branch road where PMOS MP0 and MP1 does not have electric current to flow through；PMOS MP2 is current limliting
Metal-oxide-semiconductor, its source electrode connects the drain electrode of PMOS MP1, and its drain electrode connects the top crown of electric capacity C, and its grid connects a biased electrical higher
Pressure (grid with PMOS MP8 connects together), for counting the moment that electric capacity is counted, limits transient switching electric current, so that
Counts can be increased；NMOS tube MN0 is electric capacity reset switch, and its grid meets reset signal Clear, and source electrode and drain electrode are distinguished
The top crown and bottom crown for counting electric capacity are connect, it is sufficiently large that its breadth length ratio is designed, it is ensured that electric capacity can be in the shorter time
It is interior to complete the operation that resets；PMOS MP3 is voltage follower, and grid connects electric capacity top crown, and source electrode is output end out, and it is responsible for
By the last count results output counted on electric capacity；PMOS MP4 is the current source load of follower, its grid and PMOS
The grid of MP5 connects together, and it constitutes a PMOS current mirror with MP5；NMOS tube MN1, MN2, MN3, MN4 constitute one
NMOS tube current mirror；The effect of the two current mirrors is will to bias the electric current for producing to be delivered to output branch road, constitutes output voltage
The current source load of follower.Biasing circuit is mainly by PMOS MP6, MP7, MP8, MP9, NMOS tube MN3, MN4 and electricity
Resistance R is constituted.
Fig. 2 gives two counting cycles of simulative counter, and the cycle of counting each time of the counting circuit is all divided into 3
In the stage, be respectively reseting stage, counting stage and reading stage.
(1) reseting stage：Before avalanche signal arrival, pulse signal input switch MP0 disconnects, using reset signal
Clear controls the startup of reseting procedure and interrupts.In reseting stage, reset signal Clear is high level, reset switch MN0
Closure, electric capacity C is discharged by MN0, and electric capacity C is discharged to GND, waits the arrival of counting stage.
(2) counting stage：Reset signal Clear in counting stage from high level saltus step be low level, reset switch
MN0 disconnects.In counting stage, SPAD can produce snowslide pulse signal after detecting photon, when pulse signal input switch MP0's
When grid input signal in is in low level, the drain electrode of MP0 is approximately the same with source voltage, is supply voltage.When in signals
When rising edge arrives, the grid current potential of MP0 is raised, because electric capacity both end voltage can not be mutated, in the presence of parasitic capacitance Cgd
The drain voltage of MP0 moment is raised to more than supply voltage, and the source electrode of transistor MP0 now becomes drain electrode, and its drain electrode becomes
It is source electrode.MP0 grid voltages and drain voltage are all VDD, and source voltage of the source voltage higher than supply voltage, i.e. MP1 is carried
Height, so that the source voltage of MP1 is higher than grid and source voltage, MP0 and MP1 is turned on, and the loop of electric discharge has two：One be by
To corona discharge, another is discharged to the drain electrode of MP1 to the source electrode of MP1 to the source electrode of MP1.Then the source voltage of MP1 is rapid
Reduce, but electric capacity C0 is charged enough.When the rising edge of each pulse signal arrives, counting electric capacity C can obtain
Measure atomic weak electric charge.The electric charge on electric capacity C is counted as the number of pulse signal is linearly increasing.
(3) stage is read：SPAD completes the detection to single photon signal, and signal input switch MP0 disconnects, on electric capacity
Electric charge is not further added by, and keeps constant.Voltage follower circuit starts to be read to counting the magnitude of voltage on electric capacity C top crowns.
Because each snowslide pulse count signal electric capacity C enhanced charge amount is equal, electric capacity C two ends are counted within a certain period of time
Voltage change is directly proportional to the number of photons detected in this period.It is that can obtain SPAD during detecting by simple computation
The number of photons for being detected.
Specific embodiment：The utility model be based on 0.18 μm of SMIC CMOS technology to it is above-mentioned based on electric capacity charge
Linear analogue counting circuit is emulated, and simulation parameter is specific as follows：Count electric capacity C and take 250fF, snowslide pulse signal in arteries and veins
Width takes 10ns, and the cycle takes 100ns；Based on above simulation parameter, the utility model has carried out the emulation of duration 120us, and obtains
Simulation result figure as shown in Figure 3.Abscissa is simulation time in figure, and ordinate is the magnitude of voltage of output end.Starting stage, electricity
Hold the C signals that are reset and discharge into 0V；Subsequent circuit often detects a snowslide pulse signal, and the magnitude of voltage on counting electric capacity C is just
Can reduce a bit, voltage waveform is presented stepped being incremented by.Under the pattern waveform of output end voltage with simulation time also be in compared with
Good linear change.By calculating, the electric capacity of 250fF can be counted about 1600 times, can realize the meter considerably beyond 10bit
Number.The corresponding magnitude of voltage of output end is 3.2V after counting 1600 times, close to supply voltage value (3.3V), is realized almost
Rail-to-rail count range.
According to simulation result above, it will be seen that counting mode of the present utility model has the good linearity, and
Maximum linear count range is larger, it is possible to achieve 1600 counting.And capacitance only needs to 250fF, counting is substantially reduced
The chip area of circuit.
Fig. 4 is the layout design of the linear analogue counting circuit based on rising edge flip-flop number, and electricity is counted including 1
Hold C and 15 metal-oxide-semiconductor.The size of metal-oxide-semiconductor MP0, MP1, MP2 all takes the minimum dimension of PMOS, and (length and width is all
300nm).The length and width of reset transistor MN0 is 1.6 μm and 350nm.For count electric capacity C, choose MIM capacitor, its width and
Length takes 10 μm and 26 μm respectively, and corresponding capacitance is 250fF.The width and length of follower MP3 be respectively 12 μm and
300nm.The width and length of current mirror MP4 and MP5 are respectively 12 μm and 1 μm.The width and length of MP6 and MP8 are respectively 8 μm
And 300nm.The width and length of MP7 and MP9 are respectively 12 μm and 1 μm.The width and length of MN2 and MN4 be respectively 12 μm and
350nm.The width and length of MN1 and MN3 are respectively 12 μm and 600nm.Resistance for producing biasing uses polysilicon resistance,
Width and length are respectively 1 μm and 10 μm, and segments is 9, and all-in resistance is 29.6k Ω.Final design out based on pulse
The linear analogue counting circuit domain of rising edge flip-flop number is as shown in Figure 4.
The utility model proposes this simulation reading method count range it is big, circuit structure is simple, will not reduce pixel
The fill factor of unit, while will not also improve the cost of circuit manufacture.Based on the principle that electric capacity both end voltage can not be mutated, this
Utility model proposes this linear analogue counting circuit based on snowslide rising edge of a pulse flip-flop number and method, the method tool
Have a count range higher, count electric capacity area occupied it is small the advantages of.
Claims (2)
1. a kind of simulation counting circuit of the count range high for being applied to SPAD detectors, it is characterised in that circuit is by a counting
Electric capacity C, 1 resistance R and 15 metal-oxide-semiconductor compositions, wherein NMOS tube MN3 and MN4, PMOS MP6, MP7, MP8 and MP9 and electricity
Resistance R constitutes a Cascode biasing circuit, for counting circuit provides biasing, while the biasing circuit is also the defeated of counting circuit
Go out follower there is provided a current source load, it is ensured that the linear convergent rate of counter, the biasing circuit is also current limliting PMOS
MP2 provides a bias voltage for higher level, and a limitation conducting electric current is served on the branch road that electric capacity charges is counted
Excessive effect, PMOS MP0 is electric charge ascending pipe, is signal input switch, and its grid meets a pulse signal in, and source electrode connects
Supply voltage VDD, its drain electrode is connected with the source electrode of PMOS MP1 pipes；MP1 is isolated tube, and its grid meets supply voltage VDD, its
Drain electrode is connected together with the source electrode of current limliting PMOS MP2；MP2 is current limiting tube, and the voltage bias that its grid connects are biased by Cascode
Circuit is provided, and its effect is the size that the moment charged in electric capacity limits charging current, and the drain electrode of PMOS MP2 meets electric capacity C
Top crown；NMOS tube MN0 is a reset switch, and the grid of MN0 meets a reset signal Clear, and drain electrode meets counting electric capacity C
Positive plate, source electrode connect count electric capacity bottom crown, i.e. GND；NMOS tube MN1, MN2, MN3 and MN4 constitute NMOS tube current mirror；
PMOS MP4 and MP5 constitute pmos current mirror, and the effect of the two current mirrors is by the biased electrical of Cascode biasing circuits
Stream be delivered to output end out where branch road, current source loads of the final PMOS MP4 equivalent to follower PMOS MP3；
PMOS MP3 is voltage follower, is responsible for the last voltage signal by counting electric capacity and is delivered to output end out, as counting
Output result.
2. the simulation counting circuit of the count range high for being applied to SPAD detectors according to claim 1, its feature exists
It is made up of PMOS MP0, MP1, MP2 and electric capacity C in the counting circuit.
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| CN201621354347.7U CN206294149U (en) | 2016-12-09 | 2016-12-09 | A kind of simulation counting circuit of the count range high for being applied to SPAD detectors |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106656166A (en) * | 2016-12-09 | 2017-05-10 | 南京邮电大学 | Analog counting circuit with high counting range applied to single photon avalanche diode (SPAD) detector |
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- 2016-12-09 CN CN201621354347.7U patent/CN206294149U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106656166A (en) * | 2016-12-09 | 2017-05-10 | 南京邮电大学 | Analog counting circuit with high counting range applied to single photon avalanche diode (SPAD) detector |
| CN106656166B (en) * | 2016-12-09 | 2023-09-26 | 南京邮电大学 | High-count-range analog counting circuit applied to SPAD detector |
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