CN111048540B - Gate-controlled pixel unit and 3D image sensor - Google Patents
Gate-controlled pixel unit and 3D image sensor Download PDFInfo
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Abstract
The invention relates to a gate-controlled pixel unit and a 3D image sensor, wherein the gate-controlled pixel unit comprises: the photoelectric conversion and control module is used for converting the received optical signals into voltage signals and obtaining control signals and light intensity information according to the voltage signals; the time-voltage conversion module is used for measuring the time interval information according to the control signal to obtain distance information; the selection output module selects and outputs distance information or light intensity information according to the received selection signal. The gate-controlled pixel unit can be switched between the SPAD working mode and the APD working mode at will by adjusting the bias voltage of the photoelectric conversion and control module so as to realize the measurement of the distance of a target object and the measurement of the illumination intensity reflected by the target object, thereby obtaining the distance information and the light intensity information of the target object.
Description
Technical Field
The invention belongs to the technical field of image sensors, and particularly relates to a gate-controlled pixel unit and a 3D image sensor.
Background
An image sensor is a semiconductor device that converts an optical signal input from the outside into an electrical signal (i.e., performs photoelectric conversion) to provide image information corresponding to the optical signal. Recently, 3D (Three dimensional, three-dimensional) image sensors that provide distance information as well as image information based on optical signals have been proposed, and 3D image sensors have important applications in the fields of laser radar, medical research, artificial intelligence, etc., which are the hot spot direction of current research.
In general, a conventional 3D image sensor generally implements three-dimensional imaging by a Time of Flight (TOF) method, and the testing principle is as shown in fig. 1, in which a start signal triggers a laser pulse signal emitter to synchronously emit laser pulses, and the laser pulses reach the surface of a target object after a period of Time, are reflected back, and are received by a sensor chip after a period of Time and generate an end signal. The time interval that this process takes can be defined by the sensor coreThe slice is quantized, i.e. the time interval t between the start signal and the end signal in fig. 1, so that the distance information s between the sensor and the target object can be obtained,wherein c represents the speed of light.
The conventional pixel unit of the 3D image sensor mainly comprises a photoelectric conversion device, a time-digital conversion circuit (Time to Digital Converter, abbreviated as TDC), a background light suppression circuit and the like, the measurement accuracy of the pixel unit is mainly determined by the conversion performance of the photoelectric conversion device and the resolution of the TDC, and meanwhile, the background light suppression circuit is required to extract an effective photon signal from a noise light signal because the pixel unit is easy to be influenced by noise such as ambient light and hot carriers. It can be seen that the conventional 3D image sensor has a complex internal circuit structure of the pixel unit, low effective filling rate of the pixel, and large pixel area, and is not suitable for designing and producing a large-scale pixel array.
Therefore, the design of the pixel unit of the 3D image sensor, which has high filling rate, small area, easy large-scale integration and environment light inhibition function, has great significance and application prospect.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a gate-controlled pixel unit and a 3D image sensor. The technical problems to be solved by the invention are realized by the following technical scheme:
the invention provides a gate-controlled pixel unit, which comprises: the photoelectric conversion and control module, the time-voltage conversion module and the selective output module, wherein,
the photoelectric conversion and control module is used for converting the received optical signal into a voltage signal and obtaining a control signal and light intensity information according to the voltage signal;
the time-voltage conversion module measures time interval information according to the control signal to obtain distance information;
the selection output module selectively outputs the distance information or the light intensity information according to the received selection signal.
In one embodiment of the present invention, the photoelectric conversion and control module includes: an AND gate, a NAND gate, a first NMOS tube, a first PMOS tube, a first inverter and an avalanche photodiode, wherein,
the input end of the AND gate receives a first reset signal and a gate control signal, and the output end of the AND gate is connected with the first input end of the NAND gate;
the second input end of the NAND gate is respectively connected with the drain electrode of the first NMOS tube and the input end of the first inverter, and the output end of the NAND gate is connected with the time-voltage conversion module;
the grid electrode of the first NMOS tube receives the gating signal, the source electrode of the first NMOS tube is connected with the cathode of the avalanche photodiode, and the drain electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube;
the grid electrode of the first PMOS tube receives the first reset signal, the source electrode is connected with a reset voltage end, and the drain electrode is respectively connected with the input end of the first inverter and the selection output module;
the output end of the first inverter is connected with the time-voltage conversion module;
the anode of the avalanche photodiode is connected with a negative voltage end.
In one embodiment of the present invention, the time-voltage conversion module includes a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a second inverter, a first capacitor, and a second capacitor, wherein,
the source electrode of the second PMOS tube is connected with the voltage end, the grid electrode of the second PMOS tube is connected with the first bias voltage end, and the drain electrode of the second PMOS tube is connected with the source electrode of the third PMOS tube;
the grid electrode of the third PMOS tube is connected with a second bias voltage end, and the drain electrode of the third PMOS tube is respectively connected with the source electrode of the fourth PMOS tube and the source electrode of the fifth PMOS tube;
the grid electrode of the fourth PMOS tube is connected with the output end of the NAND gate;
the input end of the second inverter is connected with the output end of the NAND gate, and the output end of the second inverter is connected with the grid electrode of the fifth PMOS tube;
the drain electrode of the fifth PMOS tube is connected with the grounding end;
the grid electrode of the second NMOS tube receives a first capacitance reset signal, the drain electrode of the second NMOS tube is connected with the drain electrode of the third NMOS tube, and the source electrode of the second NMOS tube is connected with the grounding end;
the grid electrode of the third NMOS tube is connected with the output end of the first inverter, and the source electrode of the third NMOS tube is respectively connected with the drain electrode of the fourth NMOS tube and the selection output module;
the grid electrode of the fourth NMOS tube receives a second capacitance reset signal, and the source electrode of the fourth NMOS tube is connected with the grounding end;
the first capacitor is connected in series between the drain electrode of the fourth PMOS tube and the grounding end;
the second capacitor is connected in series between the source electrode of the third NMOS tube and the grounding end.
In one embodiment of the present invention, the selection output module includes a fifth NMOS transistor, a sixth NMOS transistor, and a source follower, wherein,
the grid electrode of the fifth NMOS tube receives a first selection signal, the source electrode of the fifth NMOS tube is connected with the drain electrode of the first PMOS tube, and the drain electrode of the fifth NMOS tube is connected with the input end of the source electrode follower;
the grid electrode of the sixth NMOS tube receives a second selection signal, the drain electrode of the sixth NMOS tube is connected with the source electrode of the third NMOS tube, and the source electrode of the sixth NMOS tube is connected with the input end of the source electrode follower;
the source follower is used for outputting the received pixel information.
In one embodiment of the present invention, the source follower includes a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor, wherein,
the grid electrode of the sixth PMOS tube is connected with a third bias voltage end, the source electrode of the sixth PMOS tube is connected with the voltage end, and the drain electrode of the sixth PMOS tube is connected with the source electrode of the seventh PMOS tube;
the grid electrode of the seventh PMOS tube receives the column selection signal, and the drain electrode of the seventh PMOS tube is connected with the source electrode of the eighth PMOS tube;
and the grid electrode of the eighth PMOS tube is respectively connected with the drain electrode of the fifth NMOS tube and the source electrode of the sixth NMOS tube, and the drain electrode is connected with the grounding end.
In one embodiment of the present invention, the display device further includes a column amplifier, and the column amplifier is connected to the output end of the source follower, and is used for amplifying and outputting the pixel information.
The invention provides a 3D image sensor, which comprises a pixel array, a reading output circuit module and a quantization circuit module, wherein,
the pixel array is used for acquiring pixel information of a target object, and comprises a plurality of gate-controlled pixel units according to any one of the embodiments;
the reading output circuit module is used for reading and outputting the pixel information one by one in sequence;
the quantization circuit module is used for converting the output pixel information into digital information and outputting the digital information.
Compared with the prior art, the invention has the beneficial effects that:
1. the gate-controlled pixel unit can be switched between the SPAD working mode and the APD working mode at will by adjusting the bias voltage of the photoelectric conversion and control module, so that the measurement of the distance of a target object and the measurement of the illumination intensity reflected by the target object are realized, and the distance information and the light intensity information of the target object are obtained.
2. The gate-controlled pixel unit has no time-to-digital converter circuit, and can greatly reduce the area of the pixel unit, so that the power consumption of the pixel unit is also greatly reduced, and the gate-controlled pixel unit is beneficial to the integrated design of a large-scale pixel array.
3. According to the 3D image sensor, the gate-controlled pixel units are used for measuring the distance of a target object through a gate-controlled distance measuring method, and the 3D image sensor is only controlled to be in an on state within a certain short time interval in one measuring period, so that the 3D image sensor is in an off state within other time, and the interference of dark counting on a measuring result is greatly reduced.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention, as well as the preferred embodiments thereof, together with the following detailed description of the invention, given by way of illustration only, together with the accompanying drawings.
Drawings
FIG. 1 is a schematic diagram of a time-of-flight ranging method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a door control ranging method according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a gate-controlled pixel unit according to an embodiment of the present invention;
FIG. 4 is a graph of voltage versus current characteristics of an avalanche photodiode provided in an embodiment of the present invention;
fig. 5 is a circuit diagram of a gate-controlled pixel unit according to an embodiment of the present invention;
FIG. 6 is a timing diagram of a mode switch of a gate-controlled pixel unit according to an embodiment of the present invention;
fig. 7 is a working timing diagram of a gated pixel unit in a SPAD working mode according to an embodiment of the present invention.
Detailed Description
In order to further illustrate the technical means and effects of the present invention for achieving the predetermined purposes, a gated pixel unit and a 3D image sensor according to the present invention are described in detail below with reference to the accompanying drawings and detailed description.
The foregoing and other features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments when taken in conjunction with the accompanying drawings. The technical means and effects adopted by the present invention to achieve the intended purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only, and are not intended to limit the technical scheme of the present invention.
Example 1
Referring to fig. 2, fig. 2 is a schematic diagram of a door control ranging method according to an embodiment of the invention, such asAs shown in the figure, the time information and the distance obtained in the TOF ranging method are in one-to-one correspondence, the time interval can be equally divided into N parts, namely T in the figure, assuming that the total distance to be measured is S and the corresponding total time interval to be measured is T 1 、T 2 ，……，T N-1 、T N The corresponding distance of each time interval is S 1 、S 2 ，……，S N-1 、S N . It is assumed that in a certain measurement period, T needs to be measured i If the 3D image sensor receives the laser pulse signal in the time interval (1 is less than or equal to i is less than or equal to N), only the 3D image sensor needs to be controlled after starting signal transmissionTo->The time is in an on state, the laser pulse signal is responded, the 3D image sensor is in an off state in the rest of the measurement period, and the laser pulse signal is not responded. Then, if at T i When the 3D image sensor receives photons within the time interval, the 3D image sensor generates an end signal, namely the distance between the target object and the 3D image sensor is considered to be +.>If at T i No photon is received by the 3D image sensor during the time interval, no end signal is generated and the 3D image sensor is controlled to be only at T during the next measurement period i+1 And opening in the time interval, and repeating the steps until the distance between the target object and the 3D image sensor is measured when other times are in the closed state.
The embodiment proposes a gate-controlled pixel unit applied to a 3D image sensor based on a gate-controlled ranging method, please refer to fig. 3, fig. 3 is a schematic structural diagram of the gate-controlled pixel unit provided in the embodiment of the present invention, and as shown in the figure, the gate-controlled pixel unit of the embodiment includes: the device comprises a photoelectric conversion and control module 1, a time-voltage conversion module 2 and a selection output module 3, wherein the photoelectric conversion and control module 1 is used for converting a received optical signal into a voltage signal and obtaining a control signal and light intensity information according to the voltage signal; the time-voltage conversion module 2 measures time interval information according to the control signal to obtain distance information; the selection output module 3 selects and outputs the distance information or the light intensity information according to the received selection signal.
In this embodiment, the optical signal includes a laser echo signal and an ambient optical signal, the photoelectric conversion and control module 1 completes the conversion from the optical signal to the voltage signal through the avalanche photodiode, and meanwhile, the bias voltage of the anode of the avalanche photodiode can be adjusted to enable the avalanche photodiode to work in an APD (photodiode) mode so as to obtain the light intensity information of the target object, and also the bias voltage of the anode of the avalanche photodiode can be adjusted to enable the avalanche photodiode to work in a geiger mode, the time interval information is coarsely measured by using a gate scanning method, then the fine measurement of the time interval information is realized through the time-voltage conversion module 2, so as to obtain the distance information of the target object, and the selection output module 3 realizes the selection function and controls the output to switch between the distance information and the light intensity information.
In this embodiment, the avalanche photodiode is disposed as a photoelectric converter in the photoelectric conversion and control module 1, please refer to fig. 4, fig. 4 is a voltage-current characteristic diagram of the avalanche photodiode according to an embodiment of the present invention, and it can be seen from the figure that the avalanche photodiode operates in different modes due to different applied reverse bias voltages. When the reverse bias voltage is smaller, the device works in an APD mode, and the generated reverse current is in direct proportion to the illumination intensity; when the reverse bias voltage is near the avalanche breakdown voltage but smaller than the breakdown voltage, the device absorbs one photon to excite a limited number of electron hole pairs, and the device works in a linear mode, has the function of linear amplification on a photon-generated carrier and has a limited gain; when the reverse bias voltage is greater than the avalanche breakdown voltage, the device operates in a Geiger mode (Geiger mode) in which a single photon can trigger an APD to generate an avalanche current, and theoretically the avalanche gain is infinite, so that the avalanche photodiode in the Geiger mode is referred to as a Single Photon Avalanche Diode (SPAD), and the Geiger mode is also referred to as a SPAD mode.
Specifically, a specific circuit diagram of a gate-controlled pixel unit in this embodiment is shown in fig. 5, and fig. 5 is a circuit diagram of a gate-controlled pixel unit according to an embodiment of the present invention, where it can be seen that, in the figure, a photoelectric conversion and control module 1 includes: AND gate U 1 NAND gate U 2 A first NMOS tube NM1, a first PMOS tube PM1, a first inverter I 1 And an avalanche photodiode Diode, wherein the and gate U 1 The input end of the (a) receives a first reset signal RST and a gate control signal TRN, and the output end is connected with the NAND gate U 2 Is connected to the first input terminal of the first circuit; NAND gate U 2 The second input end of the first NMOS transistor NM1 is respectively connected with the drain electrode of the first NMOS transistor NM1 and the first inverter I 1 The input end of the power supply is connected with the time-voltage conversion module 2; the grid electrode of the first NMOS tube NM1 receives a gate control signal TRN, the source electrode of the first NMOS tube NM1 is connected with the cathode of the avalanche photodiode Diode, and the drain electrode of the first NMOS tube NM1 is connected with the drain electrode of the first PMOS tube PM 1; the grid electrode of the first PMOS tube PM1 receives a first reset signal RST, the source electrode is connected with a reset voltage end Vex, and the drain electrodes are respectively connected with a first inverter I 1 An input terminal of (a) and a selection output module 3; first inverter I 1 The output end of the (2) is connected with the time-voltage conversion module; the anode of the avalanche photodiode Diode is connected to the negative voltage terminal Vsub.
In this embodiment, the avalanche photodiode Diode is used as a photoelectric converter to convert a received optical signal into a voltage signal, the negative voltage end Vsub provides a bias voltage for the anode of the avalanche photodiode Diode, the reset voltage end Vex provides a bias voltage for the cathode of the avalanche photodiode Diode, the avalanche photodiode Diode can be operated in an APD mode or a SPAD mode by adjusting the voltage of the negative voltage end Vsub, and the first reset signal RST is used for resetting the avalanche photodiode Diode to the SPAD mode. The gate control signal TRN is used for controlling the opening position of the gate control window, and determining the time interval measured in the gate control ranging method, so that the first NMOS transistor NM1 is turned on in the measured time interval.
Further, the time-voltage conversion module 2 includes a second PMOS tube PM2, a third PMOS tube PM3, a fourth PMOS tube PM4, a fifth PMOS tube PM5, and a second PMOS tube PM3NMOS tube NM2, third NMOS tube NM3, fourth NMOS tube NM4, second inverter I 2 The first capacitor C1 and the second capacitor C2, wherein the source electrode of the second PMOS tube PM2 is connected with the voltage end VDD, the grid electrode is connected with the first bias voltage end Vb1, and the drain electrode is connected with the source electrode of the third PMOS tube PM 3; the grid electrode of the third PMOS tube PM3 is connected with a second bias voltage end Vb2, and the drain electrode of the third PMOS tube PM4 is respectively connected with the source electrode of the fifth PMOS tube PM 5; grid electrode of fourth PMOS tube PM4 is connected with NAND gate U 2 An output terminal of (a); second inverter I 2 Is connected with the NAND gate U 2 The output end of the second PMOS tube PM5 is connected with the grid electrode of the second PMOS tube PM 5; the drain electrode of the fifth PMOS tube PM5 is connected with the ground end GND; the grid electrode of the second NMOS tube NM2 receives a first capacitance reset signal RST_1, the drain electrode of the second NMOS tube NM3 is connected with the drain electrode, and the source electrode of the second NMOS tube NM2 is connected with the ground end GND; the grid electrode of the third NMOS tube NM3 is connected with the first inverter I 1 The source electrode of the second NMOS transistor NM4 is respectively connected with the drain electrode of the second NMOS transistor NM4 and the selective output module 3; the grid electrode of the fourth NMOS tube NM4 receives a second capacitance reset signal RST_2, and the source electrode is connected with the ground end GND; the first capacitor C1 is connected in series between the drain electrode of the fourth PMOS tube PM4 and the ground end GND; the second capacitor C2 is connected in series between the source of the third NMOS transistor NM3 and the ground GND.
In this embodiment, the second PMOS tube PM2, the third PMOS tube PM3, the fourth PMOS tube PM4 and the fifth PMOS tube PM5 form a pair of current sources with a cascode structure for charging the first capacitor C1 according to the nand gate U 2 The output control signal controls the charging time of the first capacitor C1 so as to realize fine time quantization, and the second capacitor C2 performs charge sharing with the first capacitor C1 in each measuring period and is used for sharing and averaging the voltage information on the first capacitor C1 for multiple times, so that more accurate time resolution is obtained, and further accurate distance information of a target object is obtained. The first bias voltage terminal Vb1 and the second bias voltage terminal Vb2 provide gate bias voltages for the second PMOS transistor PM2 and the third PMOS transistor PM3, respectively. The first capacitor reset signal rst_1 is used for controlling the reset of the first capacitor C1, and the second capacitor reset signal rst_2 is used for controlling the reset of the first capacitor C2.
Further, the selection output module 3 includes a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, and a source follower 301, where a gate of the fifth NMOS transistor NM5 receives the first selection signal SEL1, a source is connected to a drain of the first PMOS transistor PM1, and a drain is connected to an input end of the source follower 301; the gate of the sixth NMOS transistor NM6 receives the second selection signal SEL2, the drain is connected to the source of the third NMOS transistor NM3, and the source is connected to the input of the source follower 301; the source follower 301 is used to output the received pixel information. Specifically, the source follower 301 includes a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, and an eighth PMOS transistor PM8, where a gate of the sixth PMOS transistor PM6 is connected to the third bias voltage terminal Vb3, a source is connected to the voltage terminal VDD, and a drain is connected to a source of the seventh PMOS transistor PM 7; the grid electrode of the seventh PMOS tube PM7 receives a column selection signal COL, and the drain electrode of the seventh PMOS tube PM8 is connected with the source electrode of the eighth PMOS tube PM 8; the gate of the eighth PMOS PM8 is connected to the drain of the fifth NMOS NM5 and the source of the sixth NMOS NM6, respectively, and the drain is connected to the ground GND.
In this embodiment, the first selection signal SEL1 controls the conduction of the fifth NMOS transistor NM5, outputs the light intensity information, and the second selection signal SEL2 controls the conduction of the sixth NMOS transistor NM6, and outputs the distance information. The light intensity information and the distance information are output as pixel information to a subsequent circuit through the source follower 301. In the operation process of the 3D image sensor, pixel information of each pixel unit in the pixel array is selected and output according to the column selection signal COL. In other embodiments of the present invention, the gated pixel unit further includes a column amplifier 4, where the column amplifier 4 is connected to the output end of the source follower 301, and is used for amplifying and outputting the pixel information.
The gate-controlled pixel unit based on the gate-controlled distance measurement method in this embodiment can be switched between the SPAD working mode and the APD working mode at will by adjusting the bias voltage of the avalanche photodiode Diode in the photoelectric conversion and control module 1, so as to measure the distance of the target object and the intensity of illumination reflected by the target object, thereby obtaining the distance information and the light intensity information of the target object. Meanwhile, a time-to-digital converter circuit does not need to exist in the gate-control pixel unit, so that the area of the pixel unit can be greatly reduced, the power consumption of the gate-control pixel unit is also greatly reduced, and the gate-control pixel unit is beneficial to the integrated design of a large-scale pixel array.
Referring to fig. 6, fig. 6 is a mode switching timing diagram of a gate-controlled pixel unit according to an embodiment of the present invention, and as shown in the drawing, switching between a SPAD operation mode and an APD operation mode is achieved by adjusting a negative voltage terminal Vsub of an avalanche photodiode, and meanwhile, the output path needs to be switched by controlling signals of a first selection signal SEL1 and a second selection signal SEL 2. When the pixel unit is in the SPAD working mode, the first selection signal SEL1 is at a low level, the fifth NMOS transistor NM5 is not conducting, the second selection signal SEL2 is at a high level, and the sixth NMOS transistor NM6 is conducting, then the measurement information in the SPAD working mode, that is, the measurement information of the distance to the target object is output. When the pixel unit is in the APD working mode, the second selection signal SEL2 is at a low level, the sixth NMOS transistor NM6 is not turned on, the first selection signal SEL1 is at a high level, and the fifth NMOS transistor NM5 is turned on, so that measurement information in the APD working mode, that is, measurement information of the light intensity of the target object is output. Referring to fig. 7, fig. 7 is a working timing chart of a gated pixel unit in a SPAD working mode according to an embodiment of the present invention, as shown in the drawing, before the gated pixel unit works, first, the first capacitor C1 and the second capacitor C2 are reset by a first capacitor reset signal rst_1 and a second capacitor reset signal rst_2, so that charges stored in the first capacitor C1 and the second capacitor C2 become zero, and after the resetting is completed, voltages on the first capacitor C1 and the second capacitor C2 are both zero. When the distance information of the target object needs to be measured, the avalanche photodiode Diode is enabled to work in the geiger mode by adjusting the voltage of the negative voltage end Vsub, then the measurement is started, the LASER signal is a LASER pulse signal emitted by the LASER pulse signal emitter, representing the beginning of a measurement period, the gate signal TRN becomes effective after delaying for a period of time after the LASER signal is emitted, and is used for controlling the opening position of the gate window, namely, the time interval measured in the gate distance measuring method is determined by the delayed time, when the gate signal TRN is placed at a high level, the first NMOS tube NM1 is conducted, when the gate signal TRN becomes effectiveWhen the effective high level is reached, the first reset signal RST becomes low level, so that the first PMOS tube PM1 is turned on, and at this time, the total voltage drop across the positive and negative electrodes of the avalanche photodiode is vex+vsub, so that the avalanche photodiode operates in geiger mode, that is, SPAD mode. Then the first reset signal RST is quickly restored to the high level, so that the first PMOS tube PM1 is turned off, and the gate signal TRN remains at the high level, so that the first NMOS tube NM1 remains at the on state, and the first reset signal RST and the gate signal TRN pass through the and gate U 1 The output START signal is high, the node FD (cathode of avalanche photodiode) keeps the reset high level Vex, and the START signal passes through the NAND gate U 2 The output is low, i.e. the node Φ is low, and the current source with the cascode structure charges the first capacitor C1. If the avalanche photodiode Diode receives photons during the period when the gate signal TRN is at a high level (i.e., during the measurement period), a large avalanche current is generated on the avalanche photodiode Diode due to the avalanche multiplication effect, so that the node FD discharges to a low level, and the avalanche photodiode Diode also automatically exits the geiger mode due to the voltage drop across the avalanche photodiode Diode to Vsub. Because the node FD becomes a low level signal, the signal of the node Φ becomes a high level signal, the current source with the cascode structure stops charging the first capacitor C1, and meanwhile, the low level signal of the node FD becomes a high level signal through the first inverter, the third NMOS transistor NM3 is controlled to be turned on, so that when a photon is detected, the second capacitor C2 shares the charge on the first capacitor C1, and stores effective information on the second capacitor C2, and finally, at the end of the measurement period, the first capacitor reset signal RST1 generates a high level signal, so that the charge on the first capacitor C1 is released to zero, and reset is completed.
When the light intensity information of a target object is required to be measured, the avalanche photodiode Diode works in an APD mode by adjusting the voltage of the negative voltage end Vsub to generate limited photoelectric conversion gain, at this time, the illumination intensity and the photocurrent are in a linear relation, namely if the light intensity reflected by the object is larger, the photocurrent is larger, the parasitic capacitance of the node FD integrates the photocurrent in a measuring period, the parasitic capacitance is converted into voltage, and the voltage value of the node FD is quantized to obtain the light intensity information reflected by the object.
In the above-described measurement period, if the first selection signal SEL1 received by the selection output module 3 is valid, the fifth NMOS transistor NM5 is turned on, and the voltage of the negative voltage terminal Vsub is adjusted to make the avalanche photodiode operate in APD mode, so as to output the measured light intensity information; if the second selection signal SEL2 received by the selection output module 3 is valid, the sixth NMOS transistor NM6 is turned on, and the voltage of the negative voltage terminal Vsub is adjusted to make the avalanche photodiode Diode operate in the SPAD mode, so as to output the measured distance information.
It should be noted that, each time interval in the door control ranging method needs to be measured multiple times, so as to further suppress the influence of the ambient light signal, so that the measurement result is more accurate. By measuring multiple times at the same time interval, the voltage stored on the second capacitor C2 of the capacitor can be made to be approximately the average of the voltages on the first capacitor C1 in the multiple measurements. Finally, after each time interval measurement is finished, the second selection SEL2 signal is set to be at a high level, so that the sixth NMOS transistor NM6 is turned on, the voltage on the second capacitor C2 is output through the source follower 301 consisting of the sixth PMOS transistor PM6, the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8, and finer time division can be obtained by quantizing the voltage on the second capacitor C2 through a subsequent quantization circuit, so as to obtain higher time resolution.
Example two
The embodiment provides a 3D image sensor, which comprises a pixel array, a reading output circuit module and a quantization circuit module, wherein the pixel array is used for acquiring pixel information of a target object, and comprises a plurality of gate-controlled pixel units in the first embodiment, and the gate-controlled pixel units form a two-dimensional array of n; the reading output circuit module is used for reading and outputting the pixel information one by one in sequence; the quantization circuit module is used for converting the output pixel information into digital information and outputting the digital information. The circuits of the reading output circuit module and the quantization circuit module are similar to those of the conventional image sensor, and are not described herein again.
The 3D image sensor in this embodiment measures the target object based on the door control ranging method, and in one measurement period, the 3D image sensor is only controlled to be in an on state in a certain short time interval and to be in an off state in other time periods, so that interference of an ambient light signal on the 3D image sensor when receiving an effective laser echo signal can be effectively reduced.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (6)
1. A gate-controlled pixel cell, comprising: a photoelectric conversion and control module (1), a time-voltage conversion module (2) and a selection output module (3), wherein,
the photoelectric conversion and control module (1) is used for converting a received optical signal into a voltage signal and obtaining a control signal and light intensity information according to the voltage signal;
the time-voltage conversion module (2) measures time interval information according to the control signal to obtain distance information;
the selection output module (3) selects and outputs the distance information or the light intensity information according to the received selection signal;
wherein the photoelectric conversion and control module (1) comprises: AND gate (U) 1 ) NAND gate (U) 2 ) A first NMOS tube (NM 1), a first PMOS tube (PM 1), a first inverter (I) 1 ) And avalanche photodiodes (Diode), wherein,
said AND gate (U) 1 ) The input end of the (C) is used for receiving a first Reset Signal (RST) and a gate control signal (TRN), and the output end is connected with the NAND gate (U) 2 ) Is connected to the first input terminal of the first circuit;
the NAND gate (U) 2 ) Is connected to the drain of the first NMOS tube (NM 1) and the first inverter (I) 1 ) The output end of the power supply is connected with the time-voltage conversion module (2);
the grid electrode of the first NMOS tube (NM 1) receives the gate control signal (TRN), the source electrode is connected with the cathode of the avalanche photodiode (Diode), and the drain electrode is connected with the drain electrode of the first PMOS tube (PM 1);
the grid electrode of the first PMOS tube (PM 1) receives the first Reset Signal (RST), the source electrode is connected with a reset voltage end (Vex), and the drain electrodes are respectively connected with the first inverter (I) 1 ) And said selection output module (3);
the first inverter (I 1 ) The output end of the (C) is connected with the time-voltage conversion module (2);
an anode of the avalanche photodiode (Diode) is connected to a negative voltage terminal (Vsub).
2. The gate-controlled pixel unit according to claim 1, wherein the time-voltage conversion module (2) comprises a second PMOS transistor (PM 2), a third PMOS transistor (PM 3), a fourth PMOS transistor (PM 4), a fifth PMOS transistor (PM 5), a second NMOS transistor (NM 2), a third NMOS transistor (NM 3), a fourth NMOS transistor (NM 4), a second inverter (I) 2 ) A first capacitance (C1) and a second capacitance (C2), wherein,
the source electrode of the second PMOS tube (PM 2) is connected with a voltage end (VDD), the grid electrode of the second PMOS tube is connected with a first bias voltage end (Vb 1), and the drain electrode of the second PMOS tube is connected with the source electrode of the third PMOS tube (PM 3);
the grid electrode of the third PMOS tube (PM 3) is connected with a second bias voltage end (Vb 2), and the drain electrode of the third PMOS tube (PM 4) is respectively connected with the source electrode of the fifth PMOS tube (PM 5);
the grid electrode of the fourth PMOS tube (PM 4) is connected with the NAND gate (U) 2 ) An output terminal of (a);
the second inverter (I 2 ) Is connected to the input of the NAND gate (U) 2 ) The output end of the fifth PMOS tube (PM 5) is connected with the grid electrode of the fifth PMOS tube;
the drain electrode of the fifth PMOS tube (PM 5) is connected with a ground end (GND);
the grid electrode of the second NMOS tube (NM 2) receives a first capacitance reset signal (RST_1), the drain electrode of the second NMOS tube (NM 3) is connected with the drain electrode, and the source electrode of the second NMOS tube is connected with the ground end (GND);
the grid electrode of the third NMOS tube (NM 3) is connected with the first phase inverter (I) 1 ) The source electrode of the second NMOS tube (NM 4) is respectively connected with the drain electrode of the second NMOS tube (NM 4) and the selection output module (3);
the grid electrode of the fourth NMOS tube (NM 4) receives a second capacitance reset signal (RST_2), and the source electrode is connected with the ground end (GND);
the first capacitor (C1) is connected in series between the drain electrode of the fourth PMOS tube (PM 4) and the grounding end (GND);
the second capacitor (C2) is connected in series between the source of the third NMOS tube (NM 3) and the ground terminal (GND).
3. Gating pixel cell according to claim 2, wherein the selection output module (3) comprises a fifth NMOS transistor (NM 5), a sixth NMOS transistor (NM 6) and a source follower (301), wherein,
the grid electrode of the fifth NMOS tube (NM 5) receives a first selection signal (SEL 1), the source electrode of the fifth NMOS tube (NM 5) is connected with the drain electrode of the first PMOS tube (PM 1), and the drain electrode of the fifth NMOS tube is connected with the input end of the source follower (301);
the grid electrode of the sixth NMOS tube (NM 6) receives a second selection signal (SEL 2), the drain electrode of the sixth NMOS tube (NM 3) is connected with the source electrode of the third NMOS tube, and the source electrode of the sixth NMOS tube is connected with the input end of the source follower (301);
the source follower (301) is configured to output the received pixel information.
4. A gate-controlled pixel cell according to claim 3, wherein the source follower (301) comprises a sixth PMOS transistor (PM 6), a seventh PMOS transistor (PM 7) and an eighth PMOS transistor (PM 8), wherein,
the grid electrode of the sixth PMOS tube (PM 6) is connected with a third bias voltage end (Vb 3), the source electrode of the sixth PMOS tube is connected with the voltage end (VDD), and the drain electrode of the sixth PMOS tube is connected with the source electrode of the seventh PMOS tube (PM 7);
the grid electrode of the seventh PMOS tube (PM 7) receives a column selection signal (COL), and the drain electrode of the seventh PMOS tube (PM 8) is connected with the source electrode of the eighth PMOS tube;
the grid electrode of the eighth PMOS tube (PM 8) is respectively connected with the drain electrode of the fifth NMOS tube (NM 5) and the source electrode of the sixth NMOS tube (NM 6), and the drain electrode is connected with the grounding end (GND).
5. A gate-controlled pixel cell according to claim 3, further comprising a column amplifier (4), the column amplifier (4) being connected to the output of the source follower (301) for amplifying and outputting the pixel information.
6. A3D image sensor is characterized by comprising a pixel array, a reading output circuit module and a quantization circuit module, wherein,
the pixel array is used for acquiring pixel information of a target object, and comprises a plurality of gate-controlled pixel units according to any one of claims 1-5;
the reading output circuit module is used for reading and outputting the pixel information one by one in sequence;
the quantization circuit module is used for converting the output pixel information into digital information and outputting the digital information.
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