CN111060198B - Gating sampling front-end circuit compatible with laser radar linear/Geiger mode - Google Patents
Gating sampling front-end circuit compatible with laser radar linear/Geiger mode Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J1/00—Photometry, e.g. photographic exposure meter
- G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
- G01J1/44—Electric circuits
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- G—PHYSICS
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- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J1/00—Photometry, e.g. photographic exposure meter
- G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
- G01J1/44—Electric circuits
- G01J2001/4446—Type of detector
- G01J2001/446—Photodiode
- G01J2001/4466—Avalanche
Abstract
The invention belongs to the technical field of photoelectric detection, and particularly relates to a laser radar-oriented linear/Geiger-mode compatible gated sampling front-end circuit, which comprises N × N pixel units and N external processing circuits, wherein each line of N pixel units in the N × N pixel units is correspondingly connected with one external processing circuit, each pixel unit comprises a bias voltage and an avalanche photodiode, and the bias voltage is connected with the anode of the avalanche photodiode; the bias voltage comprises a linear bias voltage and a Geiger-mode bias voltage; the pixel unit further includes: a linear/geiger mode selection circuit connected to the cathode of the avalanche photodiode; the transimpedance amplifier circuit is connected with the linear/Geiger mode selection circuit; the gate control sampling circuit is connected with the transimpedance amplifier circuit; the external processing circuit includes: the Shift Register (SR) is connected with the gate control sampling circuit; and the ADC circuit is connected with the gate control sampling circuit. The invention has the advantages of strong expandability, strong expandability and high measurement precision.
Description
Technical Field
The invention belongs to the technical field of photoelectric detection, and particularly relates to a linear/cover grid mode compatible gated sampling front-end circuit for a laser radar.
Background
The photoelectric detection field is mainly applied to unmanned vehicles, and gray information is necessary to be measured when traffic lights and pedestrian zebra crossings are identified. The gray scale information is beneficial to the unmanned automobile to carry out 3D modeling and object recognition on the periphery of the unmanned automobile.
The traditional Single Photon Avalanche photodiode (SPAD) distance measuring technology based on TDC (Time-to-Digital Converter) circuit counting distance measurement has the advantages of high distance measuring precision, extremely high gain of the SPAD device and the like, but because the Single pixel circuit comprises a large number of circuits such as TDC (Time-to-Digital Converter) circuit, counting circuit and the like in the circuit design, the Single pixel circuit is extremely complex, the power consumption of the circuit is extremely high, and the design scheme is difficult to obtain the gray scale information of the measured object.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a laser radar-oriented linear/geiger mode compatible gated sampling front-end circuit. The technical problem to be solved by the invention is realized by the following technical scheme:
a compatible gated sampling front-end circuit facing a laser radar linear/Geiger mode comprises N x N pixel units and N external processing circuits, wherein each line of N pixel units in the N x N pixel units is correspondingly connected with one external processing circuit, each pixel unit comprises a bias voltage and an avalanche photodiode, and the bias voltage is connected with the anode of the avalanche photodiode and is used for generating avalanche current pulses;
the bias voltage comprises a linear bias voltage Vsub1And a Geiger-mode bias voltage Vsub2；
The pixel unit further includes: the linear/Geiger mode selection circuit is connected with the cathode of the avalanche photodiode and is used for selecting the working mode of the avalanche photodiode;
the trans-impedance amplifier circuit is connected with the linear/Geiger mode selection circuit and is used for generating a pulse voltage signal according to the avalanche current pulse;
the gate-controlled sampling circuit is connected with the transimpedance amplifier circuit and is used for receiving the pulse voltage signal from the transimpedance amplifier circuit;
the external processing circuit includes:
the shift register SR is connected with the gate control sampling circuit;
and the ADC circuit is connected with the gated sampling circuit and serves as a first output end OUT1 of the front-end circuit.
In one embodiment of the present invention, the linear/geiger mode selection circuit includes an NMOS transistor M1, an NMOS transistor M2, a PMOS transistor M7, a quenching capacitor C2, a voltage source VDD, an external clock control signal input SEL0, an external clock control signal input SEL1, and an external clock control signal input SEL 3;
the gate of the NMOS transistor M1 is connected to the external clock control signal input terminal SEL0, the drain of the NMOS transistor M1 is connected to the voltage source VDD, and the source of the NMOS transistor M1 is connected to the drain of the PMOS transistor M7, the transimpedance amplifier circuit, the cathode of the avalanche photodiode, and the drain of the NMOS transistor M2, respectively; the drain of the NMOS transistor M2 is further connected to the cathode of the avalanche photodiode and the transimpedance amplifier circuit, respectively, the gate of the NMOS transistor M2 is connected to the external clock control signal input terminal SEL1, the source of the NMOS transistor M2 is connected to the upper plate of the quenching capacitor C2, and the lower plate of the quenching capacitor C2 is grounded; the source electrode of the PMOS tube M7 is connected with the transimpedance amplifier circuit, and the gate electrode of the PMOS tube M7 is connected with the external clock control signal input end SEL 3.
In one embodiment of the invention, the transimpedance amplifier circuit comprises a feedback resistor R1, a feedback capacitor C1 and an amplifier I1；
The feedback resistor R1 and the feedback capacitor C1 are connected in parallel, the grid electrode of the PMOS tube M7 in the linear/Geiger mode selection circuit is connected with the external clock control signal input end SEL1, the source electrode of the PMOS tube M7 is connected with one end of the feedback resistor R1, and the other end of the feedback resistor R1 is connected with the gated sampling circuit and the amplifier I11The upper electrode plate of the feedback capacitor C1 is connected with the source electrode of the PMOS tube M7, and the lower electrode plate of the feedback capacitor C1 is connected with the amplifier I1And the gated sampling circuit, the amplifier I1The input end of the NMOS transistor M1 and the source end of the NMOS transistor M2 in the linear/Geiger mode selection circuit are connected with the drain electrode of the PMOS transistor M7.
In one embodiment of the invention, the amplifier I1A three-stage inverter is used.
In one embodiment of the present invention, the gated sampling circuit includes a clock signal input terminal CT, a source follower, an NMOS transistor M3, an NMOS transistor M6;
the source electrode of the NMOS tube M3 is connected with the transimpedance amplifier circuit, the gate electrode of the NMOS tube M3 is connected with the clock signal input end CT, and the drain electrode of the NMOS tube M3 is connected with the input end of the source electrode follower; the output end of the source follower is connected with the source electrode of the NMOS tube M6; the grid electrode of the NMOS tube M6 is connected with the output end of the shift register SR, and the drain electrode of the NMOS tube M6 is connected with the input end of the ADC circuit.
In one embodiment of the invention, the source follower comprises an NMOS transistor M4, an NMOS transistor M5, a voltage source VDD, and a current source bias voltage input VT;
the source follower is connected with the transimpedance amplifier circuit through the gate of the NMOS transistor M4, the source of the NMOS transistor M4 is connected with the voltage source, the drain of the NMOS transistor M4 is connected with the drain of the NMOS transistor M5, and the drain of the NMOS transistor M4 is also connected with the source of the NMOS transistor M6; the grid electrode of the NMOS tube M5 is connected with the current source bias voltage input end VT, the source electrode of the NMOS tube M5 is grounded, the drain electrode of the NMOS tube M5 is connected with the drain electrode of the NMOS tube M4, and the drain electrode of the NMOS tube M5 is connected with the source electrode of the NMOS tube M6.
The invention has the beneficial effects that:
the invention does not need complex time-to-digital conversion circuit and technical circuit by adopting the design of the gate-controlled sampling single-pixel circuit, when the avalanche photodiode works in a linear mode, the gate-controlled sampling circuit and the ADC circuit can simultaneously acquire the distance information and the gray information of the measured object, so that the single-pixel circuit is greatly simplified, the expansibility is strong, the power consumption is greatly reduced, the problem of the dark memory number of the APD mode is effectively solved, and the invention can also realize the measurement of time interval high precision and illumination intensity. When the avalanche photodiode works in the Geiger mode, the gated sampling front-end circuit can acquire the distance information of the object to be measured.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic diagram of an overall structure of a macro-pixel of a laser radar-oriented linear/geiger-mode compatible gated sampling front-end circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of another macro-pixel overall structure of a lidar linear/geiger-mode-compatible gated sampling front-end circuit according to an embodiment of the present invention;
fig. 3 is a schematic view of a volt-ampere characteristic curve of a linear/geiger-mode compatible gated sampling front-end circuit for a laser radar according to an embodiment of the present invention;
fig. 4 is a schematic circuit diagram of a lidar linear/geiger mode-compatible gated sampling front-end circuit pixel unit according to an embodiment of the present invention;
fig. 5 is a timing diagram of a pixel unit operation in a linear mode of a laser radar-oriented linear/geiger-mode compatible gated sampling front-end circuit according to an embodiment of the present invention;
fig. 6 is a timing diagram of operations of a pixel unit in a laser radar-oriented linear/geiger mode compatible gated sampling front-end circuit geiger mode according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Referring to fig. 1 and fig. 2, fig. 1 is a schematic diagram of an overall structure of a macro-pixel of a lidar linear/geiger-mode-compatible gated sampling front-end circuit according to an embodiment of the present invention, and fig. 2 is a schematic diagram of another macro-pixel of the lidar linear/geiger-mode-compatible gated sampling front-end circuit according to an embodiment of the present invention, where the macro-pixel includes N × N pixel units and N external processing circuits, where each N row of the N × N pixel units is correspondingly connected to one external processing circuit, the pixel units include a bias voltage and avalanche photodiodes, and the bias voltage is connected to anodes of the avalanche photodiodes for generating avalanche current pulses;
the bias voltage comprises a linear bias voltage Vsub1And a Geiger-mode bias voltage Vsub2；
The pixel unit further includes: the linear/Geiger mode selection circuit is connected with the cathode of the avalanche photodiode and is used for selecting the working mode of the avalanche photodiode;
the trans-impedance amplifier circuit is connected with the linear/Geiger mode selection circuit and is used for generating a pulse voltage signal according to the avalanche current pulse;
the gate-controlled sampling circuit is connected with the transimpedance amplifier circuit and is used for receiving the pulse voltage signal from the transimpedance amplifier circuit;
the external processing circuit includes:
the shift register SR is connected with the gate control sampling circuit;
and the ADC circuit is connected with the gated sampling circuit and serves as a first output end OUT1 of the front-end circuit.
Specifically, each pixel unit is composed of an Avalanche Photo Diode (APD), a transimpedance amplifier circuit, a linear/cover grid mode conversion switch circuit and a gate control sampling circuit, wherein N pixels are in a row, a row of pixels includes a shift register and an ADC (Analog-to-Digital Converter) circuit, and the shift register SR makes the ADC circuit sample each pixel unit in a row in turn and converts the obtained Analog level signal. When the pixel unit is in the cover grid mode, the shift register SR enables the output signals of N units in a row to be output in turn.
The gate-controlled sampling type avalanche photodiode distance measuring method does not need a complex TDC circuit and a counting circuit, when the avalanche photodiode is in a linear mode, the gate-controlled sampling circuit and an ADC (analog-to-digital converter) circuit can be used for simultaneously obtaining distance information and gray information of a measured object, when the avalanche photodiode is in a cover lattice mode, the distance information of the measured object is directly obtained, however, because the cover lattice mode is adopted, voltage does not undergo ADC conversion, the speed is higher than that of the linear mode, the design scheme enables a single-pixel circuit in a laser radar distance measuring chip to be greatly simplified, and power consumption is also greatly reduced; when the avalanche photodiode is in linear mode, the output is an analog signal, so there is no concern about the dark count problem of geiger mode. The invention can also realize the measurement of time interval with high precision and illumination intensity.
In one embodiment of the present invention, the linear/geiger mode selection circuit includes an NMOS transistor M1, an NMOS transistor M2, a PMOS transistor M7, a quenching capacitor C2, a voltage source VDD, an external clock control signal input SEL0, an external clock control signal input SEL1, and an external clock control signal input SEL 3;
the gate of the NMOS transistor M1 is connected to the external clock control signal input terminal SEL0, the drain of the NMOS transistor M1 is connected to the voltage source VDD, and the source of the NMOS transistor M1 is connected to the drain of the PMOS transistor M7, the transimpedance amplifier circuit, the cathode of the avalanche photodiode, and the drain of the NMOS transistor M2, respectively; the drain of the NMOS transistor M2 is further connected to the cathode of the avalanche photodiode and the transimpedance amplifier circuit, respectively, the gate of the NMOS transistor M2 is connected to the external clock control signal input terminal SEL1, the source of the NMOS transistor M2 is connected to the upper plate of the quenching capacitor C2, and the lower plate of the quenching capacitor C2 is grounded; the source electrode of the PMOS tube M7 is connected with the transimpedance amplifier circuit, and the gate electrode of the PMOS tube M7 is connected with the external clock control signal input end SEL 3.
In an embodiment of the present invention, referring to fig. 4, fig. 4 is a schematic circuit diagram of a pixel unit of a lidar linear/geiger-mode compatible gated sampling front-end circuit according to an embodiment of the present invention, where the transimpedance amplifier circuit includes a feedback resistor R1, a feedback capacitor C1, and an amplifier I1；
The feedback resistor R1 and the feedback capacitor C1 are connected in parallel, the grid electrode of the PMOS tube M7 in the linear/Geiger mode selection circuit is connected with the external clock control signal input end SEL1, the source electrode of the PMOS tube M7 is connected with one end of the feedback resistor R1, and the other end of the feedback resistor R1 is connected with the gated sampling circuit and the amplifier I11The upper electrode plate of the feedback capacitor C1 is connected with the source electrode of the PMOS tube M7, and the lower electrode plate of the feedback capacitor C1 is connected with the amplifier I1And the gated sampling circuit, the amplifier I1The input end of the NMOS transistor M1 and the source end of the NMOS transistor M2 in the linear/Geiger mode selection circuit are connected with the drain electrode of the PMOS transistor M7.
It should be noted that, referring to fig. 3, fig. 3 is a schematic view of a volt-ampere characteristic curve of a linear/Geiger-mode compatible gated sampling front-end circuit for a laser radar, according to an embodiment of the present invention, an avalanche photodiode operates in different modes due to different reverse bias voltages, and when the reverse bias voltage is greater than an avalanche breakdown voltage, the device operates in a Geiger mode (Geiger mode), in which a single photon can burst the avalanche photodiode to generate an avalanche current pulse, and in this mode, the avalanche photodiode needs to be quenched after generating the avalanche current pulse, and the single photon can generate the avalanche current pulse, and illumination intensity information is not easy to obtain; when the reverse bias voltage is small, the device works in a photodiode mode, and the generated reverse current is in direct proportion to the illumination intensity; when the reverse bias voltage is near the avalanche breakdown voltage but less than the breakdown voltage, the device absorbs a photon to excite a limited number of electron-hole pairs, and the device works in a linear mode, has a linear amplification effect on photon-generated carriers and has limited gain. Therefore, in the linear mode, a Trans-impedance Amplifier (TIA) is arranged on the circuit, and the time information and the illumination intensity information of the reflected light can be acquired by converting the current signal into a voltage signal.
It should be further noted that, in this embodiment, the circuit structure of the transimpedance Amplifier circuit is a C-TIA (Capacitive transimpedance Amplifier) circuit, and this TIA topology structure has the beneficial effects of low noise, high gain, and high speed.
Specifically, the transimpedance amplifier circuit charges a feedback capacitor C1 having noise characteristics lower than that of the resistor R1, and converts an input current into an output voltage, so that the sensitivity of the laser radar receiver can be greatly improved.
In one embodiment of the present invention, the amplifier I1 employs a three-stage inverter.
Specifically, in this embodiment, the three-stage inverter operates in an amplification mode, and the leakage current of the operating three-stage inverter is less than 0.1%, so that unnecessary current loss is reduced, the rise time of the output voltage of the three-stage inverter is sufficiently short, and the current conversion efficiency is improved.
Further, when the device is operating in the Geiger mode, snow is presentAvalanche photodiode anode connected Geiger mode bias voltage Vsub2Geiger mode bias voltage Vsub2About 12V, the control signals of the NMOS tube M1, the NMOS tube M2 and the PMOS tube M7 input clock control signals through an external clock control signal input end SEL0, an external clock control signal input end SEL1 and an external clock control signal input end SEL3, the clock control signal input by the whole Geiger mode external clock control signal input end SEL3 is in high level, and the feedback resistor R1, the feedback capacitor C1 and the discharger I are enabled to be in high level1Disconnecting; the clock control signals input by the external clock control signal input end SEL0 and the external clock control signal input end SEL1 jump to high level before the window period, the voltage source VDD charges the quenching capacitor C2, after the window period, the clock control signal input by the external clock control signal input end SEL0 is low level, and the NMOS tube M1 is disconnected; when the SPAD generates a pulse current, the voltage of the anode of the avalanche photodiode is rapidly reduced due to the large gain of the SPAD, and a high level is generated at FD1, and the signal passes through the source follower to wait for the shift register SR to turn on the transmission control signal SEL 2.
When the linear mode is selected by the switch, the anode of the avalanche photodiode is connected with a linear bias voltage Vsub1And the cathode is disconnected from the voltage source VDD and quenching capacitor C2 and connected to the transimpedance amplifier. When the Geiger mode is selected by the switch, the anode of the avalanche photodiode is connected to Vsub2The cathode is conducted with a voltage source VDD and the quenching capacitor, and the PMOS tube M7 enables the avalanche photodiode to be in the SPAD mode.
In one embodiment of the present invention, the gated sampling circuit includes a clock signal input terminal CT, a source follower, an NMOS transistor M3, an NMOS transistor M6;
the source electrode of the NMOS tube M3 is connected with the transimpedance amplifier circuit, the gate electrode of the NMOS tube M3 is connected with the clock signal input end CT, and the drain electrode of the NMOS tube M3 is connected with the input end of the source electrode follower; the output end of the source follower is connected with the source electrode of the NMOS tube M6; the grid electrode of the NMOS tube M6 is connected with the output end of the shift register SR, and the drain electrode of the NMOS tube M6 is connected with the input end of the ADC circuit.
Specifically, the clock signal controls the NMOS transistor M3 and the source follower to sample the transimpedance amplifier circuit, and the gate of the NMOS transistor M6 is connected to the shift register SR and receives the gate signal SEL2 from the shift register SR.
In one embodiment of the invention, the source follower comprises an NMOS transistor M4, an NMOS transistor M5, a voltage source VDD, and a current source bias voltage input VT;
the source follower is connected with the transimpedance amplifier circuit through the gate of the NMOS transistor M4, the source of the NMOS transistor M4 is connected with the voltage source, the drain of the NMOS transistor M4 is connected with the drain of the NMOS transistor M5, and the drain of the NMOS transistor M4 is also connected with the source of the NMOS transistor M6; the grid electrode of the NMOS tube M5 is connected with the current source bias voltage input end VT, the source electrode of the NMOS tube M5 is grounded, the drain electrode of the NMOS tube M5 is connected with the drain electrode of the NMOS tube M4, and the drain electrode of the NMOS tube M5 is connected with the source electrode of the NMOS tube M6.
Further, referring to fig. 5, fig. 5 is a timing diagram of a pixel unit operation in a linear mode of a laser radar-oriented linear/geiger-mode compatible gated sampling front-end circuit according to an embodiment of the present invention, where when a laser emission source emits a laser pulse, a clock signal gates a gated sampling circuit in a window period, and as the window period moves, the entire ranging range is measured; when the avalanche photodiode receives photons, avalanche current pulses are generated, and the FD node generates voltage signals as shown in the figure 5 through the trans-impedance amplifier circuit; the magnitude of j in the figure, i.e. the amount of time the avalanche photodiode generates current, is determined by the width of the gate window time t with the light pulse. Since the voltage starts to rise in the nth window, the distance L of the object to be measured is 1/2 × cnt, c is the speed of light, the gray information of the object to be measured is measured by the light intensity, and the highest value of the measured voltage in the nth window and the (n + j) th window is the light intensity information. Since the ADC circuit is shared by a row of pixel units, the gate of the NMOS transistor M6 is used to select the pixel unit to be connected to the ADC circuit, and the output end of the ADC is the output end OUT1 of the front-end circuit.
Further, referring to fig. 6, fig. 6 is a view of a lidar linear/cover according to an embodiment of the present inventionIn the Geiger mode, the clock control signal input from the external clock control signal input SEL3 is at high level, so that the feedback resistor R1, the feedback capacitor C1 and the inverter I1Disconnecting; clock control signals input by an external clock control signal input end SEL0 and an external clock control signal input end SEL1 are pulse control signals, clock control signals input by an external clock control signal input end SEL0 and an external clock control signal input end SEL1 in front of a gating window are high level, and a voltage source VDD charges a quenching capacitor C2; in the gating window, an external clock control signal input end SEL0 is disconnected, the cathode of the avalanche photodiode is at a high level, the avalanche photodiode is in an SPAD mode and can detect photons, when the photons are detected, the cathode of the avalanche photodiode is pulled to a low level, and an inverter I1The output terminal of the NMOS transistor M6 is at a high level, and the signal passes through the source follower, and can be directly output from the drain of the NMOS transistor M6 without further processing by the ADC, where the drain of the NMOS transistor M6 is the output port OUT2 of the front-end circuit.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (6)
1. A lidar linear/Geiger-mode-compatible gated sampling front-end circuit comprising N x N pixel cells, N external processing circuits, one external processing circuit connected to each of N rows of the N x N pixel cells, the pixel cells comprising a bias voltage and avalanche photodiodes, the bias voltage being connected to anodes of the avalanche photodiodes for generating avalanche current pulses, wherein the bias voltage comprises a linear bias voltage (V;) andsub1) And a Geiger mode bias voltage (V)sub2)；
The pixel unit further includes: the linear/Geiger mode selection circuit is connected with the cathode of the avalanche photodiode and is used for selecting the working mode of the avalanche photodiode;
the trans-impedance amplifier circuit is connected with the linear/Geiger mode selection circuit and is used for generating a pulse voltage signal according to the avalanche current pulse;
the gate-controlled sampling circuit is connected with the transimpedance amplifier circuit and is used for receiving the pulse voltage signal from the transimpedance amplifier circuit;
the external processing circuit includes:
a Shift Register (SR) connected to the gated sampling circuit;
and the ADC circuit is connected with the gated sampling circuit and serves as a first output end OUT1 of the front-end circuit.
2. The lidar-oriented linear/Geiger-mode-compatible gated sampling front-end circuit of claim 1 wherein the linear/Geiger-mode selection circuit comprises NMOS transistor M1, NMOS transistor M2, PMOS transistor M7, quenching capacitor C2, voltage source (VDD), external clock control signal input SEL0, external clock control signal input SEL1, and external clock control signal input SEL 3;
the gate of the NMOS transistor M1 is connected to the external clock control signal input terminal SEL0, the drain of the NMOS transistor M1 is connected to a voltage source (VDD), and the source of the NMOS transistor M1 is connected to the drain of the PMOS transistor M7, the transimpedance amplifier circuit, the cathode of the avalanche photodiode, and the drain of the NMOS transistor M2, respectively; the drain of the NMOS transistor M2 is further connected to the cathode of the avalanche photodiode and the transimpedance amplifier circuit, respectively, the gate of the NMOS transistor M2 is connected to the external clock control signal input terminal SEL1, the source of the NMOS transistor M2 is connected to the upper plate of the quenching capacitor C2, and the lower plate of the quenching capacitor C2 is grounded; the source electrode of the PMOS tube M7 is connected with the transimpedance amplifier circuit, and the gate electrode of the PMOS tube M7 is connected with the external clock control signal input end SEL 3.
3. The lidar-oriented linear/Geiger-mode-compatible gated sampling front-end circuit of claim 2, wherein the transimpedance amplifier circuit comprises a feedback resistor R1, a feedback capacitor C1, and an amplifier I1；
The feedback resistor R1 and the feedback capacitor C1 are connected in parallel, the grid electrode of the PMOS tube M7 in the linear/Geiger mode selection circuit is connected with the external clock control signal input end SEL1, the source electrode of the PMOS tube M7 is connected with one end of the feedback resistor R1, and the other end of the feedback resistor R1 is connected with the gated sampling circuit and the amplifier I11The upper electrode plate of the feedback capacitor C1 is connected with the source electrode of the PMOS tube M7, and the lower electrode plate of the feedback capacitor C1 is connected with the amplifier I1And the gated sampling circuit, the amplifier I1The input end of the NMOS transistor M1 and the source end of the NMOS transistor M2 in the linear/Geiger mode selection circuit are connected with the drain electrode of the PMOS transistor M7.
4. The lidar-oriented linear/Geiger-mode-compatible gated sampling front-end circuit of claim 3, wherein the amplifier I is1A three-stage inverter is used.
5. The lidar-oriented linear/geiger-mode-compatible gated sampling front-end circuit of claim 1, wherein the gated sampling circuit comprises a clock signal input (CT), a source follower, an NMOS transistor M3, an NMOS transistor M6;
the source electrode of the NMOS tube M3 is connected with the transimpedance amplifier circuit, the gate electrode of the NMOS tube M3 is connected with the clock signal input end (CT), and the drain electrode of the NMOS tube M3 is connected with the input end of the source follower; the output end of the source follower is connected with the source electrode of the NMOS tube M6; the grid electrode of the NMOS tube M6 is connected with the output end of the Shift Register (SR), and the drain electrode of the NMOS tube M6 is connected with the input end of the ADC circuit.
6. The lidar linear/geiger-mode-compatible gated sampling front-end circuit of claim 5 wherein the source follower comprises NMOS transistor M4, NMOS transistor M5, a voltage source (VDD) and a current source bias voltage input (VT);
the source follower is connected with the transimpedance amplifier circuit through the gate of the NMOS transistor M4, the source of the NMOS transistor M4 is connected with the voltage source, the drain of the NMOS transistor M4 is connected with the drain of the NMOS transistor M5, and the drain of the NMOS transistor M4 is also connected with the source of the NMOS transistor M6; the grid electrode of the NMOS tube M5 is connected with the current source bias voltage input end (VT), the source electrode of the NMOS tube M5 is grounded, the drain electrode of the NMOS tube M5 is connected with the drain electrode of the NMOS tube M4, and the drain electrode of the NMOS tube M5 is connected with the source electrode of the NMOS tube M6.
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