JP5644294B2 - Photodetector - Google Patents

Description

  The present invention relates to a photodetector, and more particularly to a photodetector using an avalanche effect.

  An avalanche photodiode (APD) is used as a light receiving element for detecting a weak optical signal in optical communication or optical radar. When photons are incident on the APD, electron-hole pairs are generated, and the electrons and holes are accelerated by high electrolysis, and subsequently generate impact ionization like avalanches to generate new electron-hole pairs.

  The APD use mode includes a linear mode in which the reverse bias voltage is operated below a breakdown voltage (breakdown voltage) and a Geiger mode in which the reverse bias voltage is operated at a breakdown voltage or higher. In the linear mode, the proportion of electron / hole pairs that disappear (from a high electric field) is larger than the proportion of electron / hole pairs that are generated, and the avalanche stops naturally. Since the output current is substantially proportional to the amount of incident light, it can be used to measure the amount of incident light. In the Geiger mode, an avalanche phenomenon can occur even when a single photon is incident. Such a photodiode is referred to as a single photon photodiode (SPAD). In SPAD, the avalanche can be stopped by lowering the applied voltage to the breakdown voltage. Lowering the applied voltage to stop the avalanche phenomenon is called quenching. The simplest quenching circuit is realized by connecting a quenching resistor in series with the APD. When an avalanche current is generated, the APD bias voltage drops due to a rise in the voltage between the quenching resistance terminals, and when it becomes less than the breakdown voltage, the avalanche current stops. Since a high electric field can be applied to APD, it can respond to weak light at high speed, and is widely used in the fields of optical distance measuring devices and optical communication.

  An optical distance measuring device that performs time-of-flight (TOF) using APD measures the distance to obstacles and people on the road from its nanosecond measurement accuracy and low power consumption. Applicable to collision avoidance safety devices. Such an optical distance measuring device needs to satisfy the requirements of reaction speed, noise resistance, sensitivity, power saving, size, and cost.

  Complementary metal-oxide-semiconductor (CMOS) technology is known as a technique that satisfies some of these requirements. A silicon photomultiplier (SiPM) in which this CMOS technology is applied to an APD is known (Non-patent Document 1). The SiPM forms a large photodetector as a whole by arranging a plurality of APDs in an array.

  However, the current pulse output from each photodiode of SPAD is not exactly proportional to the number of photons to be detected, and the number of photons detected by one SPAD cannot be known. Therefore, continuous light detection is detected as a spatially averaged current value using SiPM having a large number of SPADs.

  For example, as shown in FIG. 17, elements in which quenching resistors 42 are connected in series to four SPADs 40 are connected in parallel, and the sum of current pulses output from the four SPADs 40 is detected in the current flowing through the connection point. To do. In SiPM, the current pulse shows an exponential decrease, and the sum thereof has a waveform as shown in the example of FIG.

JP 2006-179828 A US Patent Publication No. 2009/0121306

"Silicon photomultiplier and its possible application", Nuclear Inst. & Methods in Physics Research, 2003, 504 (1-3), pp. 48-52.

  As shown in FIG. 18, when a photon is detected by a plurality of SPADs, a signal on which a current pulse that decreases exponentially is superimposed is obtained. At this time, the peak value of the signal is not the sum of the peaks of the current pulses output from the SPAD that has detected the photons, and does not correspond to the number of photons detected by the SiPM.

  In a distance measuring device using TOF, it is important to accurately detect the laser beam reflected by the object to be measured and generate a trigger signal. The total number of photons detected almost simultaneously by a plurality of SPADs is calculated. There is a demand for a technology that can be accurately known.

  Patent Document 2 discloses a technique for increasing the light receiving sensitivity of SiPM and reducing crosstalk between elements by increasing the ratio of the area of the light receiving region to the element area of SiPM. However, even this technique does not solve the problem caused by the exponential output pulse decrease.

  Further, in general, the optical distance measuring device needs to satisfy the requirements from the reaction speed, noise resistance, sensitivity, power saving, size and cost.

  The present invention is generated by an array of a plurality of avalanche photodiodes used in a Geiger mode, a plurality of discriminating circuits each converting an output signal from each of the avalanche photodiodes into a rectangular pulse, and the plurality of discriminating circuits. And a summing circuit for summing and outputting the rectangular pulses.

  Here, it is preferable that the pulse width of the rectangular pulse is determined in relation to photoelectric conversion in the avalanche photodiode.

  Preferably, the discrimination circuit controls a current source to generate a current rectangular pulse as the rectangular pulse, and the adding circuit is a common output contact that synthesizes the current rectangular pulse in an analog manner.

  The adder circuit is a binary adder circuit that digitally adds the rectangular pulses in the active state, compares the output of the adder circuit with a reference value, and generates a trigger signal according to the comparison result. It is preferable to provide a comparator circuit for outputting.

  A holding circuit for holding the output value of the adder circuit in synchronization with the trigger signal; and a correction circuit for correcting a timing error of the trigger signal according to the value held in the holding circuit. Is preferred.

  A second discriminating circuit for generating a second rectangular pulse having a pulse width longer than the rectangular pulse in synchronization with the rectangular pulse; and a second adding circuit for digitally adding the second rectangular pulse to a binary value; And a holding circuit for holding the output value of the second adder circuit in synchronization with the trigger signal.

  The second discriminating circuit is preferably a quenching or recharging circuit that generates the second rectangular pulse having a pulse width substantially equal to a dead time of the avalanche photodiode.

  Further, it is preferable that the second discriminating circuit deactivates the second rectangular pulse until the output of the adder circuit becomes equal to or higher than the reference value in the comparison circuit.

  Further, it is preferable that the array of avalanche photodiodes, the discrimination circuit, and the addition circuit are monolithically mounted using complementary metal oxide semiconductor technology.

  Further, any one of the above-described photodetectors may be provided, and an optical distance measuring device that performs distance measurement by detecting time of flight of irradiation light may be used.

  The present invention includes an avalanche photodiode that operates in a Geiger mode with high response speed, high sensitivity, and good noise resistance, capable of generating a detection trigger signal with high accuracy in a distance measuring device using TOF. A photodetector can be provided.

It is a figure which shows the structure of the photodetector in 1st Embodiment. It is a figure which shows the structure of the discrimination circuit in embodiment of this invention. It is a timing chart which shows operation | movement of the photodetector in 1st Embodiment. It is a figure which shows the structure of the photodetector in 2nd Embodiment. It is a timing chart which shows operation | movement of the photodetector in 2nd Embodiment. It is a figure which shows the structure of the photodetector in 3rd Embodiment. It is a timing chart which shows operation | movement of the photodetector in 3rd Embodiment. It is a figure which shows the structure of the photodetector in 4th Embodiment. It is a figure which shows the structure of the photodetector in 5th Embodiment. It is a figure which shows the structure of the photodetector in 6th Embodiment. It is a timing chart which shows operation | movement of the photodetector in 6th Embodiment. It is a figure which shows the structure of the discrimination circuit in embodiment of this invention. It is a figure which shows the structure of another example of the photodetector in 6th Embodiment. It is a figure which shows the structure of the photodetector in 7th Embodiment. It is a timing chart which shows operation | movement of the photodetector in 7th Embodiment. It is a figure which shows the structure of the discrimination circuit in embodiment of this invention. It is a figure which shows the structure of the conventional photodetector. It is a figure which shows the example of the signal detected by the conventional photodetector.

<First Embodiment>
As shown in FIG. 1, the photodetector 100 in the first embodiment includes a silicon photomultiplier (SiPM) 10, a quenching element 12 (12a to 12d), a discrimination circuit 14 (14a to 14d), a current source. 16 (16a to 16d). The photodetector 100 has a basic configuration of other embodiments described below. In the following description, when each signal is at a high level, it will be described as an active state, and when it is at a low level, it will be described as an inactive state. The same operation and effect can be obtained with the configuration.

  The photodetector 100 shows an example configured to include a SiPM 10 including four single photon avalanche photodiodes (SPAD) 10a to 10d. Of course, the scope of application of the present invention is not limited to the SiPM 10 including four SPADs 10a to 10d. For example, the SiPM 10 includes SPADs other than four, such as a configuration in which SPADs are arranged in a 10 × 10 matrix. Can be applied similarly.

  The SiPM 10 includes SPADs 10a to 10d. Each SPAD 10a-10d operates in Geiger mode. That is, each of the SPADs 10a to 10d is operated with the reverse bias voltage equal to or higher than the breakdown voltage, and causes an avalanche phenomenon even when a single photon is incident. Therefore, the SiPM 10 has high sensitivity to incident light such as laser light.

  Here, each of the SPADs 10a to 10d preferably has a guard ring and a metal wiring area as small as possible, and increases a fill factor (aperture ratio) that is a ratio of a light receiving area to an element area. In particular, the fill factor can be increased by not forming quenching elements and recharge elements inside the SPAD arranged in a matrix.

  The quenching element 12 (12a to 12d) can be composed of a transistor or a resistor. The quenching element 12 (12a to 12d) is preferably connected to the SPADs 10a to 10d by metal wiring outside the SPADs 10a to 10d.

  When an avalanche current is generated in the SPADs 10a to 10d, the bias voltage with respect to the SPADs 10a to 10d is decreased due to a voltage increase between the terminals of the quenching element 12, and when the voltage is lower than the breakdown voltage, the avalanche current is stopped. The quenching element 12 (12a to 12d) is connected in series to each of the SPADs 10a to 10d, and is also used to generate an output voltage for each of the discrimination circuits 14 (14a to 14d).

  The discrimination circuit 14 (14a to 14d) is provided for each pair of the SPADs 10a to 10d and the quenching elements 12a to 12d. Hereinafter, the discrimination circuit 14a will be described as an example, but the same applies to the discrimination circuits 14b, 14c, and 14d.

  The discrimination circuit 14a compares the terminal voltage of the quenching element 12a with a predetermined reference value, and generates a rectangular pulse according to the comparison result. As shown in FIG. 2, the discrimination circuit 14a can include a comparator 14e, a delay element 14f, and an AND element 14g. FIG. 3 shows a timing chart for explaining the operation of the discrimination circuits 14a to 14d.

The comparator 14e receives the terminal voltage Va of the quenching device 12a, comparing the terminal voltage Va and the reference voltage _{V REF,} is at a high level as long as the terminal voltage Va is the reference voltage _{V REF} or more, the terminal voltage Va If it is less than the reference voltage V _REF , an output pulse A1 having a low level is output. The delay element 14f receives the output pulse of the comparator 14e, delays the change of the output pulse by the delay time W, and outputs it as the output pulse B1. The delay time W is preferably shorter than the dead time of the SPAD 10a, that is, the time from the rise to the disappearance of the terminal voltage Va, which is the output of the SPAD 10a. Specifically, the delay time W is more preferably set to 1 nsec or more and 20 nsec or less. The AND element 14g receives the output pulse A1 from the comparator 14e and the inverted signal of the output pulse B1 from the delay element 14f, and calculates and outputs a logical product of them. Thus, discrimination circuit 14a generates a rectangular pulse C1 outputs having a pulse width from the time the terminal voltage Va is output from SPAD10a becomes equal to or higher than the reference voltage V _REF by a predetermined delay time W.

  Note that the terminal voltage Va, which is the output of the SPAD 10a, shows a steep rise according to the photon reception time of the photon, so that the rectangular pulse C1 becomes a signal that rises almost simultaneously with the time when the SPAD 10a receives the photon. Further, as shown in FIG. 3, the discrimination circuits 14b, 14c and 14d function in the same manner as the discrimination circuit 14a.

  The current source 16 (16a to 16d) receives the rectangular pulses C1 to C4 output from the discrimination circuit 14 (14a to 14d), and each of the currents has a predetermined value during a period in which the rectangular pulses C1 to C4 are at a high level. Shed. The current source 16 (16a to 16d) is connected to one output terminal T1, and, as shown in FIG. 1, an addition current Isum obtained by adding the currents output from the current source 16 (16a to 16d) to the output terminal T1. Flows.

  As shown in FIG. 3, the addition current Isum takes a value corresponding to the total number of photons detected almost simultaneously by the SPADs 10 a to 10 d included in the SiPM 10. Therefore, by using the addition current Isum as a trigger signal, it is possible to increase the detection accuracy of the laser light reflected by the measurement object. For example, in this embodiment, if the addition current Isum is equal to or greater than 3 units (a state where photons are incident on three of the SPADs 10a to 10d) or more, light detection is highly accurate if the trigger signal is output. Can be done.

<Second Embodiment>
As shown in FIG. 4, the photodetector 200 in the second embodiment includes a silicon photomultiplier (SiPM) 10, a quenching element 12 (12a to 12d), a discrimination circuit 14 (14a to 14d), a digital addition. And a digital comparator 20.

  Hereinafter, the function of the photodetector 200 according to the present embodiment will be described with reference to the timing chart of FIG. In the present embodiment, the functions of the SiPM 10, the quenching element 12, and the discrimination circuit 14 are the same as those in the first embodiment, and a description thereof will be omitted.

  The digital adder 18 digitally adds the output pulses C1 to C4 generated by the discrimination circuit 14 and outputs the value as an output value Dsum. That is, the digital adder 18 calculates and outputs the total number of high-level signals among the output pulses C1 to C4.

The digital comparator 20 compares the output value Dsum of the digital adder 18 with a predetermined reference value D _REF , and if the output value Dsum of the digital adder is greater than or equal to the reference value D _REF, sets the trigger signal TRG to high level, Otherwise, the level is low. For example, if the reference value D _{REF is set} to 3, the trigger signal TRG is set to a high level during a period when the output value Dsum of the digital adder is 3 or more.

  Also in the photodetector 200 of the present embodiment, it is possible to improve the detection accuracy of the laser beam reflected by the measurement object. In this embodiment, the high level is the active state of each signal, but the low level may be the active state of each signal.

<Third Embodiment>
As shown in FIG. 6, the photodetector 300 according to the third embodiment is configured by adding a resistance element R and a constant fraction discriminator (CFD) 22 to the configuration of the first embodiment.

  Hereinafter, the function of the photodetector 300 in the present embodiment will be described with reference to the timing chart of FIG. In the present embodiment, the functions of the SiPM 10, the quenching element 12, the discriminating circuit 14, and the current source 16 are the same as those in the first embodiment, and a description thereof will be omitted.

  The resistance element R is connected to the terminal T1, converts the addition current Isum into a terminal voltage Vin, and outputs it. As illustrated in FIG. 7, the terminal voltage Vin is a value obtained by subtracting a potential difference R × Isum that is a voltage drop due to the resistance element R from the power supply voltage V.

The CFD 22 is a circuit used to accurately detect the rising time of an input pulse without depending on the magnitude of the pulse. As shown in FIG. 6, the CFD 22 can include a comparator 22a, an amplifier 22b, a delay element 22c, a comparator 22d, and an AND element 22e. The comparator 22a compares the input voltage Vin with the reference voltage _VTHR . If the input voltage Vin is equal to or lower than the reference voltage _VTHR , the comparator 22a sets the output signal D to a high level. If the input voltage Vin is greater than the reference voltage _VTHR , the output signal D D is set to low level.

It is preferable that the reference voltage V _THR is changed dynamically according to the magnitude of these noises by monitoring optical noise and other noises included in the input signal Vin. For example, it is preferable to reduce the reference voltage V _THR as the noise increases.

  On the other hand, the input signal Vin is amplified at a predetermined amplification factor A by the amplifier 22b, delayed by a predetermined delay time in the delay element 22c, and output as a signal E. The amplification factor A is preferably 3 to 6 dB, for example. The delay time of the delay element 22c is preferably made smaller than the pulse width of the input signal Vin. The comparator 22d compares the signal E with the input signal Vin. When the input signal Vin is equal to or higher than the signal E, the comparator 22d sets the output signal F to the high level. When the input signal Vin is less than the signal E, the comparator 22d sets the output signal F to the low level. To do. The AND element 22e receives the output signal D from the comparator 22a and the output signal F from the comparator 22d, calculates the logical product of both signals, and outputs it as an output signal G.

  Generally, the rising speed of the input signal Vin (added current Isum) (the rising slope of the signal) varies depending on the difference in the maximum amplitude of the input signal Vin (maximum amplitude of the added current Isum). In the process of detecting the time point when the input signal Vin (addition current Isum) is equal to or higher than a predetermined reference value using a normal comparator as the rising point of the input signal Vin, the maximum amplitude of the input signal Vin (the maximum amplitude of the addition current Isum) ) Causes an error at the detection time. On the other hand, in the optical distance measuring device, an error of 1 ns affects a distance error of about 15 cm. The CFD 22 is a circuit for eliminating such a distance detection error depending on the rising speed of the signal, and reduces the influence of the amplitude of the input signal Vin in the detection of the rising time of the input signal Vin. According to the photodetector 300 of the present embodiment, it is possible to further improve the detection accuracy of the laser light reflected by the measurement object.

<Fourth embodiment>
As shown in FIG. 8, the photodetector 400 in the fourth embodiment includes a transfer impedance amplifier (TIA) 24 instead of the resistance element R in the configuration of the third embodiment.

  The TIA 24 generates and outputs an output signal Vin corresponding to the addition current Isum. At this time, the TIA 24 reduces the influence of the parasitic capacitance C on the wiring shown in FIG. 8 and makes the rise of the output signal Vin steep.

  Thereby, the delay or dullness of the rising of the input signal Vin corresponding to the input of photons to the SiPM 10 can be reduced, and the detection accuracy of the laser light reflected by the measurement object can be further increased.

<Fifth embodiment>
As shown in FIG. 9, the photodetector 500 in the fifth embodiment has a configuration in which the memory element 26 is added to the configuration in the second embodiment.

  The memory element 26 holds and outputs the output value Dsum of the digital adder 18 in synchronization with the change of the trigger signal TRG from the digital comparator 20. The memory element 26 can be composed of one or a plurality of flip-flop elements and latch elements.

  The output value Dsum held in the memory element 26 can be used to correct a temporal error included in the trigger signal TRG according to the output value Dsum. For example, as the output value Dsum increases, the trigger signal TRG tends to become high level earlier. Therefore, a correction circuit (not shown) for performing processing to compensate for such tendency is provided and output from the memory element 26. Processing for correcting the rising timing of the trigger signal TRG can be performed according to the output value Dsum.

<Sixth Embodiment>
As shown in FIG. 10, a photodetector 600 according to the sixth embodiment further includes a discrimination circuit 28 (28a to 28d), a digital adder 30, and a delay element 32 in addition to the configuration according to the fifth embodiment. It has a configuration. FIG. 11 is a timing chart for explaining the operation of the photodetector 600.

  The discrimination circuit 28 (28a to 28d) receives the output signals C1 to C4 from the discrimination circuit 14 (14a to 14d), respectively, and generates rectangular pulses H1 to H4 having a pulse width T longer than the delay time W. Output. Specifically, the discrimination circuit 28 (28a to 28d) can be configured to include a flip-flop element 28e and a delay element 28f, respectively, as shown in FIG. Hereinafter, the discrimination circuit 28a will be described as an example.

  The flip-flop element 28e receives the rectangular pulse C1 as a clock signal, changes the output Q from the low level to the high level in synchronization with the timing when the rectangular pulse C1 changes from the low level to the high level, and outputs the inverted output Q bar. Is changed from high level to low level. The delay element 28f delays the inverted signal of the inverted output Q bar by a delay time T and outputs the delayed signal. The output of the delay element 28f is input to the reset terminal of the flip-flop element 28e. Accordingly, the flip-flop element 28e is reset after the delay time T has elapsed since the output Q changes from the low level to the high level, and changes the output Q from the high level to the low level. In this way, the discrimination circuit 28a has a function of changing the rectangular pulse C1 having the pulse width W to the rectangular pulse H1 having the pulse width T.

  The delay time T of the delay element 28f is preferably substantially equal to the dead time of the SPAD 10a, that is, the time from the rise of the terminal voltage Va that is the output of the SPAD 10a to the disappearance. Specifically, the delay time T is preferably 5 to 100 nsec.

  The digital adder 30 digitally adds the output pulses H1 to H4 from the discrimination circuit 28 (28a to 28d), and outputs the value as an output value Dsum2. That is, the digital adder 30 calculates and outputs the total number of high level signals among the output pulses H1 to H4.

  On the other hand, the delay element 32 delays the trigger signal TRG output from the digital comparator 20 by a predetermined delay time τ and outputs it as a clock signal TRGτ of the memory element 26.

  The memory element 26 holds the output value Dsum2 of the digital adder 30 and outputs it as the output value Dout in synchronization with the change of the clock signal TRGτ from the delay element 32. The memory element 26 can be composed of one or a plurality of flip-flop elements and latch elements.

  Thus, the rectangular pulses H1 to H4 having the pulse width T longer than the delay time W are generated using the discrimination circuit 28 (28a to 28d), and the rectangular pulses H1 to H4 are added using the digital adder 30. Then, the output value Dsum2 is calculated, and the trigger signal TRG is delayed to hold the output value Dsum2 in the memory element 26. Thus, the maximum value of the photons detected almost simultaneously in the photodetector 600 is accurately determined as the output value Dout. Can be obtained as

  The output value Dout output from the memory element 26 can be used for correction of a temporal error included in the trigger signal TRG, as in the fifth embodiment.

  As shown in FIG. 13, the output voltages Va to Vd from the silicon photomultiplier (SiPM) 10 are directly input to the discrimination circuit 28 (28a to 28d) without going through the discrimination circuit 14 (14a to 14d). It is good also as the photodetector 602 which has these.

<Seventh embodiment>
As shown in FIG. 14, the photodetector 700 in the seventh embodiment has a configuration in which a discrimination circuit 34 is further added to the configuration in the sixth embodiment. FIG. 15 is a timing chart for explaining the operation of the photodetector 700.

  As shown in FIG. 16, the discrimination circuit 28 (28a to 28d) included in the photodetector 700 includes a buffer element 28g having a gate function in the discrimination circuit 28 (28a to 28d) in the sixth embodiment. It becomes the composition which added. That is, the discrimination circuit 28 (28a to 28d) outputs only during a period in which the enable signal EN input to the buffer element 28g is at a high level.

  The discrimination circuit 34 receives the trigger signal TRG from the digital comparator 20, and generates and outputs a rectangular pulse with a pulse width T from the time when the trigger signal TRG rises. This rectangular pulse becomes the enable signal EN. The enable signal EN is input to each buffer element 28g and delay element 32 of the discrimination circuit 28 (28a to 28d).

  The discrimination circuit 28 (28a to 28d) outputs the output pulses H1 to H4 only when the enable signal EN becomes high level. Therefore, it is not necessary for the digital adder 30 to substantially perform addition processing until the enable signal EN becomes a high level, and in this embodiment, power consumption in the digital adder 30 can be suppressed.

  The delay element 32 delays the enable signal EN by the delay time τ and outputs it as the clock signal TRGτ of the memory element 26. The memory element 26 holds the output value Dsum2 of the digital adder 30 and outputs it as the output value Dout in synchronization with the change of the clock signal TRGτ from the delay element 32.

  As described above, in the photodetector 700 according to the present embodiment, the power consumption of the entire circuit can be reduced by substantially not performing the addition processing in the digital adder 30 until the trigger signal TRG rises. .

  In addition, it is more preferable that each component in all the above embodiments is formed monolithically on the same semiconductor substrate as the SiPM 10.

  DESCRIPTION OF SYMBOLS 10 Silicon photomultiplier, 10a-10d Single photon avalanche photodiode, 12 (12a-12d) Quenching element, 14 (14a-14d Discrimination circuit, 14e Comparator, 14f Delay element, 14g AND element, 16 (16a-16d) Current source, 18 digital adder, 20 digital comparator, 22 constant fraction discriminator (CFD), 22a comparator, 22b amplifier, 22c delay element, 22d comparator, 22e AND element, 24 transfer impedance amplifier (TIA), 26 memory element 28 (28a to 28d) Discriminating circuit, 28e Flip-flop element, 28f Delay element, 28g Buffer element, 30 Digital adder, 32 Delay element, 34 Valve Circuit, 40 single photon avalanche photodiode, 42 quenching resistor, 100,200,300,400,500,600,602,700 photodetector.

Claims (10)

An array of multiple avalanche photodiodes used in Geiger mode;
A plurality of discriminating circuits each for converting an output signal from each of the avalanche photodiodes into a rectangular pulse;
An addition circuit for adding and outputting the rectangular pulses generated by the plurality of discrimination circuits;
A photodetector comprising: The photodetector of claim 1, comprising:
The pulse width of the rectangular pulse is determined in association with photoelectric conversion in the avalanche photodiode. The photodetector according to claim 1 or 2,
The discrimination circuit controls a current source to generate a current rectangular pulse as the rectangular pulse,
The photodetector is a common output contact that synthesizes the current rectangular pulse in an analog manner. The photodetector according to claim 1 or 2,
The addition circuit is a binary addition circuit that digitally adds the rectangular pulses in an active state,
A photodetector comprising: a comparison circuit that compares an output of the adder circuit with a reference value and outputs a trigger signal in accordance with the comparison result. The photodetector according to claim 4, comprising:
A holding circuit that holds and outputs the output value of the adder circuit in synchronization with the trigger signal;
An optical detector comprising: a correction circuit that corrects a timing error of the trigger signal in accordance with a value held in the holding circuit. The photodetector according to claim 4, comprising:
A second discriminating circuit for generating a second rectangular pulse having a pulse width longer than the rectangular pulse in synchronization with the rectangular pulse;
A second addition circuit that digitally adds the second rectangular pulse to a binary value;
A holding circuit that holds and outputs the output value of the second adder circuit in synchronization with the trigger signal;
A photodetector comprising: The photodetector according to claim 6, comprising:
The photodetector according to claim 1, wherein the second discrimination circuit is a quenching or recharging circuit that generates the second rectangular pulse having a pulse width substantially equal to a dead time of the avalanche photodiode. The photodetector according to claim 6, comprising:
The photodetector according to claim 2, wherein the second discriminating circuit deactivates the second rectangular pulse until the output of the adder circuit becomes equal to or higher than the reference value in the comparison circuit. It is a photodetector as described in any one of Claims 1-8, Comprising:
A photodetector in which the array of avalanche photodiodes, the discrimination circuit, and the addition circuit are monolithically mounted using complementary metal oxide semiconductor technology. Comprising the photodetector according to any one of claims 1 to 9,
An optical distance measuring device that measures distance by detecting the time of flight of irradiated light.

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