CN103873791B - Pixel unit read-out circuit and method, and pixel array read-out circuit and method - Google Patents
Pixel unit read-out circuit and method, and pixel array read-out circuit and method Download PDFInfo
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- CN103873791B CN103873791B CN201410095468.3A CN201410095468A CN103873791B CN 103873791 B CN103873791 B CN 103873791B CN 201410095468 A CN201410095468 A CN 201410095468A CN 103873791 B CN103873791 B CN 103873791B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
- H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
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- H—ELECTRICITY
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
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Abstract
The invention provides a pixel unit read-out circuit, a pixel unit read-out method, a pixel array read-out circuit and a pixel array read-out method. Each of the pixel unit read-out circuit and the pixel array read-out circuit at least comprises a voltage supply unit, a current comparison unit and a counting unit. The output end of one pixel unit and the output end of each voltage supply unit are respectively connected with two input ends of the corresponding current comparison unit. The output end of each current comparison unit is connected with the enabling end of the corresponding counting unit. The pixel unit read-out circuit and the pixel array read-out circuit, provided by the invention, have the characteristics of low power consumption and simple structure, conventional ADC (analog-to-digital conversion) modules in the pixel unit read-out circuit and the pixel array read-out circuit adopting current signals of a semi-floating gate transistor and the like as read-out signals are eliminated, and the complexity and area of each read-out circuit are reduced, so that the design cost and manufacturing cost of an image sensor chip are reduced.
Description
Technical field
The present invention relates to a kind of technical field of semiconductor device, more particularly to a kind of pixel cell reading circuit and its reading
Go out method and pel array reading circuit and its reading method.
Background technology
Imageing sensor can catch picture signal, and is converted into the signal of telecommunication, is shown on the terminal device.Mesh
Front image sensor chip has obtained widely should in fields such as consumer electronics, military project, imaging of medical and Aero-Space
With.Traditional imageing sensor is divided into charge-coupled image sensor (charge-coupled device, ccd) and complementary metal oxidation
The big type of thing quasiconductor (complementary metal-oxide-semiconductor, cmos) two.Wherein cmos image passes
Sensor can be mutually compatible and low in energy consumption with existing super large-scale integration technique, integrated level high it is easy to Function Extension, therefore
Become a kind of technology comparing main flow.
The Chinese patent of Publication No. cn101707202a discloses a kind of half floating transistor (semi-floating-
Gate transistor, sfgt), it is a kind of new semiconductor device, can act as photo-sensitive cell, basic structure such as Fig. 1
Shown.
Described half floating transistor includes: is formed in the Semiconductor substrate 500 that two shallow trenchs are isolated between sti501
Drain region 514, source region 511, the raceway groove 512 in the middle of drain region 514 and source region 511, the shallow trench isolation of source region 514 side
Between sti501 and raceway groove 512 well region 503, and be located at well region 503 in contra-doping area 502.The mixing of described well region 503
Miscellany type is identical with drain region 514, and the doping content of drain region 514/ source region 511 is more than the doping content of well region 503；Described counter mix
The doping type in miscellaneous area 502 is contrary with well region 503.
Described raceway groove 512 and described well region 503, contra-doping area 502 are formed near the top of described raceway groove 512 side
One layer of dielectric film 506, described ground floor dielectric film 506 is formed with half floating gate region 505.The doping class of wherein half floating gate region 505
Type is contrary with drain region 514, and is contacted with described contra-doping area 502 by the window 504 in ground floor dielectric film 506.
Second layer dielectric film 509 is also covered with described half floating gate region 505, described second layer dielectric film 509 is formed with
Control gate 507.
Wherein, described well region 503, drain region 514 and contra-doping area 502, half floating gate region 505 constitute light sensitive diode, can
Accept illumination when reverse-biased, produce photogenerated current, double floating gate region 505 is charged, change the potential of half floating gate region 505, lead
Cause the threshold voltage variation of transistor.
Photodiode when half floating transistor is used as photo-sensitive cell, first to contra-doping area 502 and well region 503 composition
Apply positive bias-voltage, carry out the operation that resets, empty the electric charge on half floating gate region 505；Subsequently reverse-biased electricity is applied to photodiode
So as to enter exposure status, photogenerated charge is collected into half floating gate region 505 to pressure, and its voltage raises, therefore whole half floating boom crystal
The threshold voltage vth of pipe declines, and intensity of illumination is bigger, and half floating gate region 505 voltage rises more, the journey that threshold voltage vth declines
Degree is also bigger；In the stage of reading, certain positive voltage is applied respectively to control grid electrode 507 and drain terminal electrode 513, then has electricity
Flow through drain region 514 and flow to source region 511.By reading the size of the current value of source electrode 510, reflect the power of illumination, thus
Reach photosensitive function.
It is illustrated in figure 2 half floating transistor shown in Fig. 1 as the equivalent circuit of sensor devices.As shown in Figure 2, half
Floating transistor is as sensor devices by a mos transistor 402 containing half floating gate region 403 and a light sensitive diode 404 institute
Composition.
It is illustrated in figure 3 the structural representation of traditional pixel cell based on cmos device.With traditional based on cmos
The 3t dot structure (3 transistors add a light sensitive diode) of device is compared, and the pixel cell based on half floating transistor is only
Need a transistor just can complete the operation resetting, exposing and read, therefore substantially increase the fill factor, curve factor (sense of pixel
The ratio of light region area and total pixel area), increased sensitivity and the resolution of imageing sensor.
In addition, the pel array pixel array based on half floating transistor is as shown in figure 4, include some row of several rows,
In figure only illustrates that jth arranges, jth+row, the i-th row and i+1 row, and other row or row are by diagram aligned transfer.Wherein, every string
Pixel or every one-row pixels at least include a pixel cell pixel, and each pixel cell pixel includes half floating boom crystal
Pipe, the control-grid voltage vg with half floating transistor in all pixels unit pixel of a line is connected, with all leakages of a line
Pole tension vd is all connected, and described control-grid voltage vg and drain voltage vd is as the input voltage signal of pel array；Same
The source electrode of all pixels unit pixel of row all interconnects, as the reading letter after pel array pixel array exposure
Number.
Pel array pixel array as shown in Figure 4 is reading the output current signal i(j of every string pixel) when, lead to
Often it is required for analog-digital converter (adc), to convert analog signals into certain digital signal amount.General, the power consumption of adc
Greatly, circuit structure is complicated, is all generally therefore the major part of power consumption in image sensor chip, and can occupy sizable core
Piece area, the advantage counteracting half floating transistor pixel cell high fill factor, increased cost.And traditional pixel cell
Read output signal is mostly voltage signal, directly can carry out analog digital conversion using adc；And the reading of half floating transistor pixel cell
Going out signal is current signal, and the process circuit of its read output signal is increasingly complex, and area and power consumption are all bigger.
Content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a pixel cell reading circuit and its
Reading method, pel array reading circuit and its reading method, multiple for solving reading circuit structure and sequential in prior art
Miscellaneous so that image sensor chip power consumption is big, the low problem of fill factor, curve factor.
For achieving the above object and other related purposes, the present invention provides a pixel cell reading circuit, described pixel list
Unit includes half floating transistor, includes a photodiode between the drain electrode of described half floating transistor and half floating boom, and described half
The source electrode of floating transistor is the outfan of described pixel cell, and this pixel cell reading circuit at least includes: voltage provides single
Unit, electric current comparing unit and counting unit, wherein: the outfan of described pixel cell is suitable to export the reading of described pixel cell
Signal；Described voltage providing unit is adapted to provide for the voltage of monotone variation；Described electric current comparing unit includes two inputs, respectively
Connect the outfan of described pixel cell and the outfan of described voltage providing unit, be suitable to provide described voltage providing unit
Monotone variation voltage conversion be monotone variation electric current, and be compared with the read output signal of described pixel cell, according to
Comparative result exports a voltage signal；Described counting unit includes two inputs, respectively clock signal input terminal and Enable Pin,
Described clock signal input terminal connects clock signal, and described Enable Pin connects the outfan of described electric current comparing unit, described meter
Counting unit is suitable to calculate the number of times of clock signal input pulse, and exports count value according to the control enabling end signal.
Preferably, described voltage providing unit is monotone variation voltage providing unit, is adapted to provide for monotone increasing or dullness
The voltage signal reducing；Described electric current comparing unit includes current lens unit and v-i converting unit, and described current lens unit includes
Current input terminal and current output terminal；Described v-i converting unit includes current output terminal and voltage input end, is suitable to believe voltage
Number it is converted into current signal；
Wherein, the current input terminal of described current lens unit connects the outfan of described pixel cell, described current mirror list
The current output terminal of unit is connected with the current output terminal of described v-i converting unit, the outfan of as described electric current comparing unit；
The outfan of described voltage providing unit is connected with the voltage input end of described v-i converting unit.
Preferably, described voltage providing unit is digital to analog converter.
Preferably, described current lens unit includes: a nmos transistor and the 2nd nmos transistor, a described nmos
The current input terminal that the grid of transistor is connected as described current lens unit with drain electrode, the source electrode of a described nmos transistor
Ground connection, the grid of a described nmos transistor is connected with the grid of described 2nd nmos transistor, described 2nd nmos crystal
The source ground of pipe, the current output terminal draining as described current lens unit of described 2nd nmos transistor.
Preferably, described v-i converting unit includes a pmos transistor, a described pmos transistor channel breadth length ratio
More than 50, the source electrode of a described pmos transistor accesses source voltage, and the drain electrode of a described pmos transistor turns for described v-i
Change the current output terminal of unit, the grid of a described pmos transistor is the voltage input end of described v-i converting unit.
Preferably, described half floating transistor includes: source region, drain region, contra-doping area, channel region, well region, control gate and half
Floating boom；Described source region, drain region, contra-doping area and channel region form in the semiconductor substrate, the equal position in described contra-doping area and drain region
In described well region, described contra-doping area and channel region are formed between source region and drain region；Described half floating boom is formed at described anti-
On doped region, well region and channel region, described control gate is formed on described half floating boom；Wherein, described source region, drain region and well region
Doping type is identical, and the doping type of described half floating boom is contrary with the doping type in described drain region, the doping in described contra-doping area
Type is contrary with the doping type in described drain region.
In addition, technical scheme additionally provides a pel array reading circuit, described pel array is included at least
String pixel cell, each pixel cell includes half floating transistor, and half floating boom in pixel cell described in every string is brilliant
The source electrode of body pipe interconnects and the outfan as every string pixel cell, and this pel array reading circuit at least includes: electricity
Pressure provides unit, electric current comparing unit and counting unit, wherein: the outfan of described pixel cell is suitable to export described pixel list
The read output signal of unit；Described voltage providing unit is adapted to provide for the electric current of monotone variation；It is defeated that described electric current comparing unit includes two
Enter end, electric current comparing unit described in connects the defeated of the voltage providing unit described in outfan and of every string pixel cell respectively
Go out end, be suitable to by described voltage providing unit provide monotone variation voltage conversion be monotone variation electric current, and with described
The read output signal of pixel cell is compared, and exports a voltage signal according to comparative result；Described counting unit includes two inputs
End, respectively clock signal input terminal and Enable Pin, described clock signal input terminal connects clock signal, and described Enable Pin connects
The outfan of described electric current comparing unit；Described counting unit is suitable to calculate the number of times of clock signal input pulse, and according to making
The control output count value of energy end signal.
Preferably, described voltage providing unit is monotone variation voltage providing unit, is adapted to provide for monotone increasing or dullness
The voltage signal reducing；Described electric current comparing unit includes current lens unit and v-i converting unit, and described current lens unit includes
Current input terminal and current output terminal；Described v-i converting unit includes current output terminal and voltage input end, is suitable to believe voltage
Number it is converted into current signal；Wherein, the current input terminal of described current lens unit connects the output of described every string pixel cell
End, the current output terminal of described current lens unit is connected with the current output terminal of described v-i converting unit, as described electric current ratio
Outfan compared with unit；The outfan of described voltage providing unit is connected with the voltage input end of described v-i converting unit.
Alternatively, described pel array reading circuit includes: n arranges described pixel cell, n described electric current comparing unit, n
Individual counting unit and a described voltage providing unit, wherein, n is integer while n >=2；Each column pixel cell respectively with described n
Individual electric current comparing unit corresponds and is connected, and each electric current comparing unit is corresponded with n described counting unit respectively and is connected, institute
The voltage input end stating v-i converting unit in n electric current comparing unit is connected to the outfan of described voltage providing unit.
Alternatively, described pel array reading circuit includes: n row pixel cell, a described electric current comparing unit, one
Counting unit, n gating transistor and a described voltage providing unit, wherein, n is integer while n >=2；Described gating is brilliant
Body pipe is mos transistor, and its grid connects gating signal, controls on or off by gating signal, each described gating transistor
It is connected between the outfan of each column pixel cell and described electric current comparing unit, in described electric current comparing unit, v-i conversion is single
The voltage input end of unit is connected with the outfan of described voltage providing unit, the outfan of described electric current comparing unit and described meter
The Enable Pin of counting unit connects.
Preferably, described voltage providing unit is digital to analog converter.
Preferably, described current lens unit includes: a nmos transistor and the 2nd nmos transistor；A described nmos
The grid of transistor is connected with drain electrode and draws the current input terminal of described current lens unit, the source electrode of a described nmos transistor
Ground connection, the grid of a described nmos transistor is connected with the grid of described 2nd nmos transistor, described 2nd nmos crystal
The source ground of pipe, the current output terminal of described current lens unit is drawn in the drain electrode of described 2nd nmos transistor.
Preferably, described v-i converting unit includes a pmos transistor, a described pmos transistor channel breadth length ratio
More than 50, the drain electrode of a described pmos transistor is described current output terminal, is connected with the Enable Pin of described counting unit, institute
The source electrode stating a pmos transistor accesses source voltage, and the grid of a described pmos transistor is voltage input end.
Preferably, described half floating transistor includes: source region, drain region, contra-doping area, channel region, well region, control gate and half
Floating boom, wherein: described source region, drain region, contra-doping area and channel region form in the semiconductor substrate, described contra-doping area and drain region
It is respectively positioned in described well region, described contra-doping area and channel region are formed between source region and drain region；Described half floating boom is formed at institute
State on contra-doping area, well region and channel region, described control gate is formed on described half floating boom；Described source region, drain region and well region
Doping type is identical, and the doping type of described half floating boom is contrary with the doping type in described drain region, the doping in described contra-doping area
Type is contrary with the doping type in described drain region.
Accordingly, technical scheme additionally provides a method for reading out pixel signals, provides pixel as above
Unit reading circuit.When reading the read output signal of described pixel cell, described voltage providing unit provides a monotone variation
Voltage signal, the voltage signal of described monotone variation is converted to the current signal of monotone variation by described electric current comparing unit, and
It is compared with the read output signal of described pixel cell；Meanwhile, described counting unit starts counting up under control of the clock signal,
When the read output signal of described pixel cell is equal to the current signal of described monotone variation, stop counting and exporting count value.
Accordingly, technical scheme additionally provides a pel array reading method, provides pixel as above
Array readout circuitry.When reading the read output signal of certain string pixel cell, described voltage providing unit provides a monotone variation
Voltage signal, the voltage signal of described monotone variation is converted to the current signal of monotone variation by described electric current comparing unit,
And be compared with the read output signal of described pixel cell；Meanwhile, described counting unit starts to count under control of the clock signal
Number, when the read output signal of described pixel cell is equal to the current signal of described monotone variation, stops counting and exporting count value.
As described above, the pixel cell reading circuit of the present invention and reading method, pel array reading circuit and reading side
Method, has the advantages that
Described half floating transistor is carried out as the pixel cell of photosensitive structure using electric current comparing unit and counting unit
The reading of photoreceptor signal, wherein, the simplest structure of described electric current comparing unit only includes 3 mos transistors, described counting list
The structure of unit is also very simple, and therefore reading circuit area is very little, and to have cast out conventional needle to read output signal be current signal
Adc module in pel array reading circuit, greatly reduces complexity and the circuit area of reading circuit, can carry further
The fill factor, curve factor of hi-vision sensor photosensitive structure, improves device performance, and reduce image sensor chip design cost and
Manufacturing cost.
In alternative, each column pixel cell of pel array has respective electric current comparing unit and counting unit,
Parallel read-out can be realized, improve the frame per second of imageing sensor.
In alternative, each row pixel cell of pel array shares an electric current comparing unit and a counting is single
Unit, so that described reading circuit area proportion is very little, greatly reduces complexity and the circuit area of reading circuit,
Thus ensure imageing sensor high fill factor, high performance improve chip integration simultaneously, greatly reduce image
The design cost Manufacturing cost of sensor chip.
Brief description
Fig. 1 is shown as half floating transistor as the semiconductor structure schematic diagram of sensor devices.
Fig. 2 is shown as half floating transistor as the structural representation of pixel cell.
Fig. 3 is shown as the dot structure schematic diagram in prior art based on cmos device.
Fig. 4 is shown as the structural representation of the pel array in prior art based on half floating transistor.
Fig. 5 is shown as the schematic diagram of the pixel cell/pel array reading circuit of offer in the embodiment of the present invention.
Fig. 6 is shown as the schematic diagram of the pixel cell reading circuit of offer in the embodiment of the present invention one.
Fig. 7 is shown as the schematic diagram of the pel array reading circuit of offer in the embodiment of the present invention two.
Fig. 8 is shown as the pel array reading circuit work schedule schematic diagram provide in the embodiment of the present invention two.
Fig. 9 is shown as the schematic diagram of the pel array reading circuit of offer in the embodiment of the present invention three.
Figure 10 is shown as the pel array reading circuit work schedule schematic diagram provide in the embodiment of the present invention three.
Component label instructions
100 pixel cells
200 voltage providing units
300 electric current comparing units
400 counting units
500 gating transistors
En Enable Pin
Dac digital-to-analogue converter
N1 the first nmos transistor
N2 the 2nd nmos transistor
P1 the first pmos transistor
N(j), n(j+1) the 3rd mos transistor
Clk clock signal
I(j) pixel current signal
Iramp monotone variation current signal
Vramp monotone variation voltage signal
Vc electric current comparing unit output signal
Dout(j) counting unit
M count value
Pixel array pel array
Specific embodiment
Hereinafter embodiments of the present invention are illustrated by particular specific embodiment, those skilled in the art can be by this explanation
Content disclosed by book understands other advantages and effect of the present invention easily.
Refer to Fig. 5 to Figure 10.It should be clear that structure depicted in this specification institute accompanying drawings, ratio, size etc., all only use
To coordinate the content disclosed in description, so that those skilled in the art understands and reads, being not limited to the present invention can
The qualificationss implemented, therefore do not have technical essential meaning, the tune of the modification of any structure, the change of proportionate relationship or size
Whole, under not affecting present invention effect that can be generated by and the purpose that can reach, all should still fall in disclosed skill
In the range of art content can cover.Meanwhile, in this specification cited as " on ", D score, "left", "right", " middle " and
The term of " one " etc., is merely convenient to understanding of narration, and is not used to limit the enforceable scope of the present invention, its relativeness
It is altered or modified, under no essence change technology contents, when being also considered as the enforceable category of the present invention.
Embodiment one
The present embodiment provides a pixel cell reading circuit, is adapted to the outfan of pixel cell 100, to read pixel
The read output signal of unit.Preferably, described pixel cell includes half floating transistor, the drain electrode of described half floating transistor and half
A photodiode is included, the source electrode of described half floating transistor is the outfan of described pixel cell between floating boom.
As shown in figure 5, the pixel cell reading circuit that the present embodiment provides specifically includes: voltage providing unit 200, electric current
Comparing unit 300 and counting unit 400.Wherein, the outfan of described pixel cell 100, describedization voltage providing unit 200
Outfan is connected with two inputs of described electric current comparing unit 300 respectively, the outfan of described electric current comparing unit 300 and institute
Enable Pin en stating counting unit 400 connects.
Specifically, as shown in fig. 6, described electric current comparing unit 300 includes current lens unit and v-i converting unit.Described
Current lens unit includes current input terminal and current output terminal；Described v-i converting unit includes current output terminal and control source
End, for being converted to current signal by voltage signal.Wherein, the current input terminal of described current lens unit connects described pixel list
The outfan of unit 100, the current output terminal of described current lens unit is connected with the current output terminal of described v-i converting unit；Institute
The outfan stating voltage providing unit 200 is connected with the voltage input end of described v-i converting unit.
In the present embodiment, described voltage providing unit 200 is monotone variation voltage providing unit, is adapted to provide for monotone variation
Voltage signal.Optionally, voltage providing unit 200 can be monotone increasing voltage providing unit, provides the electricity of monotone increasing
Pressure signal；Unit can also be provided for monotone decreasing small voltage, the voltage signal of dull reduction is provided.Preferably, described voltage carries
It is digital to analog converter dac for unit 200, voltage signal that is linearly increasing or reducing is provided.In other embodiments, described electricity
It can also be other voltage generation circuits that pressure provides unit.
In the present embodiment, described current lens unit includes a nmos transistor n1 and the 2nd nmos transistor n2, described
The grid of the first nmos transistor n1 is connected with drain electrode and draws the current input terminal of described current lens unit, and a described nmos is brilliant
The source ground of body pipe n1, the grid of a described nmos transistor n1 and the grid of the 2nd nmos transistor n2 are connected, described
The source ground of the 2nd nmos transistor n1, the electric current of described current lens unit is drawn in the drain electrode of described 2nd nmos transistor n2
Outfan.In other embodiments, the current mirror that described current mirror can also be constituted for pmos transistor, or other forms
1:1 current-mirror structure, one end that described current-mirror structure is connected with pixel cell 100 outfan be its current input terminal,
The other end is its current output terminal.
In the present embodiment, described v-i converting unit is a pmos transistor p1, the leakage of a described pmos transistor p1
The current output terminal of extremely described v-i converting unit, is connected with the current output terminal of current lens unit, and is connected to described counting
Enable Pin en of unit 400, the source electrode of a described pmos transistor p1 connects source voltage, and in the present embodiment, this source voltage is one
High level；The grid of a described pmos transistor p1 is voltage input end, accesses the dull change that voltage providing unit 200 provides
The voltage signal changed.In other embodiments, described v-i converting unit can also be nmos transistor, or other can be by electricity
Pressure signal is converted to circuit structure or the chip module of current signal.
In the present embodiment, counting unit 400 includes two inputs, respectively clock signal input terminal and Enable Pin en,
Wherein, clock signal input terminal incoming clock signal clk, Enable Pin en connects the outfan of electric current comparing unit 300.Count single
Unit 400 counts to the pulse number of clock signal clk input, until the electric current comparing unit 300 of Enable Pin en connection
Output signal overturns, and counting unit 400 stops counting and exporting count results dout.It should be noted that the present embodiment
In, the technological means that the circuit structure of counting unit 400 is well known to those skilled in the art, therefore not to repeat here.
Above-mentioned pixel cell reading circuit in the work process of read pixel unit 100 read output signal is:
As shown in fig. 6, the read output signal of pixel cell 100 output is current signal i, flow direction includes a nmos transistor
The current input terminal of the current lens unit of n1 and the 2nd nmos transistor n2, is converted into by current lens unit mirror image and reads electricity
Equal its current output terminal current signal i ' of stream signal i；Meanwhile, the digital-to-analogue converter dac as voltage providing unit 200 produces
The voltage signal vramp of a raw monotone variation, and export to the grid of a pmos transistor p1, a pmos transistor p1
The voltage signal vramp of monotone variation is converted to the current signal iramp of monotone variation.
Electric current comparing unit 300 is to the current output terminal current signal i ' equal with read current signal i and monotone variation
Current signal iramp be compared, meanwhile, the pulse number that counting unit 400 inputs to clock signal clk starts counting up.
As most preferred embodiment, voltage providing unit 200 provides the voltage signal vramp of a monotone increasing, and through first
Pmos transistor p1 is converted to the current signal iramp of dull reduction.
Now, when the current signal i ' of current lens unit current output terminal is less than the current signal iramp of monotone variation,
The output voltage vc=x(x of electric current comparing unit 300 is high level or low level)；Current signal iramp with monotone variation
Change, current signal i ' (the i.e. pixel cell 100 read current signal i) meeting and single of ultimate current mirror unit current output terminal
The current signal iramp of modulation is equal, and exceed the current signal iramp of monotone variation, now electric current comparing unit 300
Output voltage overturns, i.e. the reverse signal of vc=xbar(x).
In said process, the beginning that counting unit 400 works from electric current comparing unit 300 is just defeated to clock signal clk
Enter pulse to keep counting, when vc overturns, that is, during vc=xbar, counting unit 400 stops counting, i.e. now counting unit 400
Count results dout just embody the current signal i size of this pixel cell 100 read output signal, thus having reacted this pixel list
The illumination intensity of unit 100, realizes the function of photosignal reading.
It should be noted that in above-mentioned work process, the output voltage vc in order to ensure electric current comparing unit 300 occurs
Upset, it is necessary to assure the current signal iramp of initial time monotone variation0The current signal i reading more than pixel cell 100.
Based on the voltage signal vramp of monotone variation, the current signal of the monotone variation through a pmos transistor p1 translation bit
The expression formula of iramp is:Wherein a is constant, w and l is respectively first
Pmos transistor p1 raceway groove width and raceway groove are long, and vdd is the supply voltage of electric current comparing unit 300, vth,p1For a pmos crystal
The threshold voltage of pipe p1.The voltage signal vramp of the monotone increasing providing as most preferred embodiment, voltage providing unit 200 can
Start dull or dull linear to increase to vdd, therefore value iramp of initial time iramp from 00For:Under normal circumstances, the pixel cell 100 based on half floating transistor reads
Current signal i be less than 100 μ a, therefore, need only a pmos transistor p1 breadth length ratio w/l ＞ 50, you can ensure initial when
Carve the current signal iramp of monotone variation0＞ i.And the voltage signal vramp of monotone increasing eventually to increase to electric current more single
Supply voltage vdd, the now iramp=0 of unit 300, the current signal i reading certainly less than pixel cell 100.Therefore, whole mistake
Cheng Zhong, necessarily once inside out in the output voltage vc of electric current comparing unit 300, and this energizing signal may be adapted to counting unit 400
Terminate counting, and export count results dout.
As alternative embodiment, the voltage signal vramp that voltage providing unit 200 provides can also be dull reduction,
As being decreased to 0 from vdd dullness, then once inside out also necessarily in the output voltage vc of electric current comparing unit 300.With above-mentioned
The situation of voltage signal vramp monotone increasing the difference is that only, the voltage signal that voltage providing unit 200 provides
During vramp monotone increasing, output signal vc of electric current comparing unit 300 is the reverse signal overturning from x as xbar(x), and this
When, output signal vc of electric current comparing unit 300 is to overturn as x from xbar.This upset is equally applicable for counting unit 400 and terminates meter
Number, and export count results dout.Now, the count value that counting unit 400 exports in count results dout equally embodies picture
The size of plain unit 100 read current signal i, but described count value is bigger then it represents that the electric current that this pixel cell 100 reads is believed
Number i is bigger.
In the pixel cell reading circuit that the present embodiment provides, carried out using electric current comparing unit 300 and counting unit 400
The signal of described pixel cell 100 reads, and the simplest basic structure of wherein said electric current comparing unit 300 only includes 3 mos
Transistor, the structure of described counting unit 400 is also very simple, and therefore reading circuit area is very little, and has cast out conventional needle pair
Current signal, as the adc module in the pixel cell reading circuit of read output signal, greatly reduces the complexity of reading circuit
And circuit area, thus reducing the design cost Manufacturing cost of image sensor chip, image can be improved further and pass
The fill factor, curve factor of sensor photosensitive structure, improves chip integration, improves device performance.
Embodiment two
Present embodiments provide a pel array reading circuit.
Described pel array is array structure as shown in Figure 4, including at least string pixel cell 100, each pixel list
Unit 100 includes half floating transistor, and the source electrode of half floating transistor in pixel cell described in every string interconnects simultaneously
Outfan as every string pixel cell.
With continued reference to shown in Fig. 5, specifically, the pel array reading circuit that the present embodiment provides includes: voltage provides single
Unit 200, electric current comparing unit 300 and counting unit 400；The outfan of every string pixel cell 100, voltage described in one provide single
The outfan of unit 200 is connected with two inputs of electric current comparing unit 300 described in respectively, described electric current comparing unit 300
Outfan is connected with Enable Pin en of described counting unit 400.
Described voltage providing unit 200 is monotone variation voltage providing unit, is adapted to provide for the voltage signal of monotone variation.
Optionally, voltage providing unit 200 can be monotone increasing voltage providing unit, provides the voltage signal of monotone increasing；Also may be used
To provide unit for monotone decreasing small voltage, provide the voltage signal of dull reduction.Preferably, described voltage providing unit 200 is
Digital to analog converter dac, provides voltage signal that is linearly increasing or reducing.In other embodiments, described voltage providing unit
Can also be other voltage generation circuits.
Described electric current comparing unit 300 includes current lens unit and v-i converting unit.Described current lens unit includes electric current
Input and current output terminal；Described v-i converting unit includes current output terminal and voltage input end, for turning voltage signal
It is changed to current signal.Wherein, the current input terminal of described current lens unit connects the outfan of described pixel cell 100, described
The current output terminal of current lens unit is connected with the current output terminal of described v-i converting unit；Described voltage providing unit 200
Outfan is connected with the voltage input end of described v-i converting unit.
In the present embodiment, described n counting unit 400 all includes two inputs, respectively clock signal input terminal and
Enable Pin en, wherein, the clock signal input terminal of each counting unit 400 accesses identical clock signal clk, each counting unit
400 Enable Pin en connects the outfan of corresponding current comparing unit 300.When certain string pixel cell 100 is read, right
The pulse number that the counting unit 400 answered inputs to clock signal clk counts, until the corresponding current that Enable Pin en connects
The output signal of comparing unit 300 overturns, and counting unit 400 stops counting and exporting count results dout.Need explanation
, in the present embodiment, the technological means that the circuit structure of counting unit 400 is well known to those skilled in the art, here is not
Repeat.
Specifically as shown in fig. 7, described pel array pixel array includes several rows, some row pixel cells 100, often
String pixel includes at least one pixel cell 100.
Described in every string, the source electrode of pixel cell 100 interconnects and the outfan as every string pixel cell 100,
It is connected with the control gate of all pixels unit 100 of a line and accesses grid voltage vg, with the leakage of all pixels unit 100 of a line
Extremely it is connected and accesses drain voltage vd, described control-grid voltage vg and drain voltage vd is as pel array pixel array's
Input voltage signal；The source electrode of all pixels unit 100 of same row all interconnects, as pel array pixelarray
Output current signal.
If described pel array pixel array has n row pixel cell 100, in the present embodiment, described pel array reads
Circuit includes n described electric current comparing unit 300, a described voltage providing unit 200 and n counting unit 400, and n is
Integer and n >=2.Wherein, each column pixel cell 100 connects electric current comparing unit 300 described in, each electric current comparing unit 300
Connect one to one with n described counting unit 400 respectively, the electricity of v-i converting unit in described n electric current comparing unit 300
Pressure input is connected to the outfan of described voltage providing unit 200.
Below in conjunction with shown in Fig. 7, with the i-th row in pel array pixel array, i+1 row, jth arranges, jth+1 row
The structure of pel array reading circuit and the operation principle of the present embodiment offer, as a example pixel cell 100, are provided.
As shown in fig. 7, jth row, jth+1 need to carry out the picture of signal reading in arranging in described pel array pixel array
Current signal i (j) that plain unit 100 reads, i (j+1) be respectively connecting to electric current comparing unit 300 (j) of respective column level, 300
(j+1).Wherein, taking the pixel cell 100 of jth row as a example.
In the present embodiment, described electric current comparing unit 300 include a nmos transistor n1, the 2nd nmos transistor n2 and
First pmos transistor p1.
A described nmos transistor n1 and described 2nd nmos transistor n2 constitutes current lens unit.A described nmos
The current input terminal that the grid of transistor n1 is connected as described current lens unit with drain electrode, a described nmos transistor n1's
Source ground, the grid of a described nmos transistor n1 and the grid of the 2nd nmos transistor n2 are connected, described 2nd nmos
The source ground of transistor n1, the current output terminal draining as described current lens unit of described 2nd nmos transistor n2.
In other embodiments, described current lens unit can also be the current lens unit of the 1:1 of other forms, described current mirror knot
One end that structure is connected with pixel cell 100 outfan is its current input terminal, and the other end is its current output terminal.
In the present embodiment, described v-i converting unit is a pmos transistor p1.A described pmos transistor p1's
The current output terminal draining as described v-i converting unit, is connected with the current output terminal of current lens unit, and is connected to described meter
Enable Pin en of counting unit 400, the source electrode of a described pmos transistor p1 connects source voltage, and in the present embodiment, this source voltage is
One high level；The grid of a described pmos transistor p1 is voltage input end, accesses the dullness that voltage providing unit 200 provides
The voltage signal of change.In other embodiments, described v-i converting unit can also be nmos transistor, or other can be by
Voltage signal is converted to circuit structure or the chip module of current signal.
A pmos transistor p1 in the present embodiment, in the corresponding electric current comparing unit 300 of every string pixel cell 100
Be all connected to same as on the digital-to-analogue converter dac of voltage providing unit 200, provided by same digital-to-analogue converter dac
The voltage of monotone variation gives a described pmos transistor p1, and every string pixel cell 100(such as in figure jth row, jth+1
Row ... ...) it is respectively coupled string level electric current comparing unit 300, that is, in the readout process, the selected pixel cell of every string
100 can concurrently be read.
In the present embodiment, voltage providing unit 200 is digital to analog converter dac, produces the voltage signal of monotone variation
Vramp, as most preferred embodiment, the voltage signal vramp of this monotone variation is the linear voltage of monotone increasing, therefore,
It is the dull line reducing through the current signal iramp that v-i converting unit is the monotone variation that a pmos transistor p1 is converted to
Property current signal.And read current signal i (j) of pixel cell 100 is fixed value, and by a nmos transistor n1 and the
The current lens unit of two nmos transistor n2 compositions replicates current signal i (j) ' obtaining current lens unit current output terminal, and i
(j)=i(j)’.Specifically, the work schedule of the pel array reading circuit shown in Fig. 7 is as shown in Figure 8.
As shown in figure 8, from the t0 moment, entering to read output signal current signal i (j) of jth row pixel cell 100
Row reads, and now, the monotone variation voltage signal vramp that voltage providing unit 200 provides is minima it is preferable that dull become
The voltage signal vramp minima changed is 0.The voltage signal vramp of this monotone variation is logical in electric current comparing unit 300 (j)
Cross the current signal iramp that the pmos transistor p1 as v-i converting unit is converted to monotone variation.Now, described list
The current signal iramp of modulation is more than described pixel current signal i (j), current comparator module 300 (j) in therefore Fig. 7
Output voltage vc (j) is high level, and jth is arranged corresponding counting unit 400 (j) and started counting up with clock signal clk simultaneously.
In the t1 moment, the current signal iramp of monotone variation is equal to the current signal i that jth row pixel cell 100 reads
(j), i.e. p point in Fig. 8, and then begin to less than read current signal i (j), now the electric current in (t1 moment) Fig. 7 compares
Voltage signal vc (j) that unit 300 (j) exports overturns, and is changed into low level, the letter of electric current comparing unit 300 (j) output simultaneously
The upset of number vc (j) makes counting unit 400 (j) stop counting.Now, counting unit 400 (j) output count results dout
J count value m in () just embodies the size of pixel cell 100 read current signal i (j) of jth row, described count value m is got over
Greatly then it represents that current signal i (j) of jth row pixel cell 100 reading is less, thus count value m has just reacted this pixel cell
100 illumination intensity.
It should be noted that in above-mentioned work process, identical with embodiment one, in order to ensure electric current comparing unit 300
Output voltage vc overturn, it is necessary to assure the current signal iramp of initial time monotone variation0More than pixel cell 100
The current signal i reading.Under normal circumstances, the current signal i that the pixel cell 100 based on half floating transistor reads is less than
100 μ a, therefore, need only a pmos transistor p1 breadth length ratio w/l ＞ 50, voltage providing unit 200 output monotone variation
Voltage signal vramp excursion be 0～vdd, you can ensure initial time monotone variation current signal iramp0＞ i,
And iramp minima is 0, the current signal i reading certainly less than pixel cell 100.Therefore, in whole process, electric current compares
Necessarily once inside out in the output voltage vc of unit 300, and this energizing signal may be adapted to counting unit 400 and terminates counting, and defeated
Go out count results dout.
As alternative embodiment, the voltage signal vramp that voltage providing unit 200 provides can also be dull reduction,
As from vddDullness is decreased to 0, then once inside out also necessarily in the output voltage vc of electric current comparing unit 300.With above-mentioned
The situation of voltage signal vramp monotone increasing the difference is that only, the voltage signal that voltage providing unit 200 provides
During vramp monotone increasing, output signal vc of electric current comparing unit 300 is the reverse signal overturning from x as xbar(x), and this
When, output signal vc of electric current comparing unit 300 is to overturn as x from xbar.This upset is equally applicable for counting unit 400 and terminates meter
Number, and export count results dout.Now, counting unit 400 (j) exports the same body of count value m in count results dout (j)
Showed the size of pixel cell 100 read current signal i (j) of jth row, but described count value m bigger then it represents that jth row picture
Current signal i (j) that plain unit 100 reads is bigger.
In the present embodiment, each column pixel cell 100 all shares an electric current comparing unit 300 and a counting unit
400, the simplest basic structure of described electric current comparing unit 300 all only includes 3 mos transistors, described counting unit 400
Structure is also very simple, thus the circuit area of the pel array reading circuit providing in the present embodiment is less, and does not need to adopt
The very big adc module of complex structure power consumption, thus reducing design complexities and the cost of image sensor chip, and power consumption
Relatively low.
In addition in the present embodiment, each column pixel cell 100 has each self-corresponding electric current comparing unit 300 and counts single
Unit 400, therefore can realize parallel read-out, improve the frame per second of imageing sensor.
Embodiment three
Present embodiments provide a pel array reading circuit, pel array similar embodiment described in the present embodiment two.
With continued reference to shown in Fig. 5, the pel array reading circuit that the present embodiment provides includes: voltage providing unit 200, electricity
Stream comparing unit 300 and counting unit 400.The outfan of every string pixel cell 100, voltage providing unit 200 described in
Outfan is connected with two inputs of electric current comparing unit 300 described in respectively, the outfan of described electric current comparing unit 300 with
Enable Pin en of described counting unit 400 connects.
Specifically as shown in figure 9, the pel array reading circuit that the present embodiment provides is from the different of embodiment two, if institute
Stating pel array has n row pixel, then the described pel array reading circuit that the present embodiment provides includes: a described electric current compares
Unit 300, a described counting unit 400, n gating transistor 500 and a described voltage providing unit 200, n is integer
And n >=2.Wherein, each described gating transistor 500 is connected to each column pixel cell 100 outfan and described electric current comparing unit
Between 300, in described electric current comparing unit 300, the voltage input end of v-i converting unit and described voltage providing unit 200 is defeated
Go out end to be connected.
In the present embodiment, described gating transistor 500 is the 3rd mos transistor, and the 3rd mos transistor can be
Nmos transistor or pmos transistor.Preferably, in the present embodiment, the 3rd mos transistor is nmos transistor, institute
Pixel cell 100 outfan of the source electrode and described each column pixel of stating the 3rd mos transistor is connected, described 3rd mos transistor
Drain electrode be connected with the current input terminal of described current lens unit, the grid of described 3rd mos transistor accesses gating signal, leads to
Cross whether gating signal controls the gating of respective column pixel.
Below in conjunction with shown in Fig. 9, with the i-th row in pel array pixel array, i+1 row, jth arranges, jth+1 row
The structure of pel array reading circuit and the operation principle of the present embodiment offer, as a example pixel cell 100, are provided.
As shown in figure 9, the outfan of each column pixel is connected to a gating crystalline substance in described pel array pixel array
Body pipe 500, described gating transistor 500 is the 3rd mos transistor n (j), n (j+1), as the switch of row level.Described 3rd
The grid of mos transistor connects row read strobe signal col (j), col (j+1), and the source electrode phase of all 3rd mos transistors
Connect, and be connected to the current input terminal of current lens unit in described electric current comparing unit 300.Described electric current comparing unit 300
Shared by whole pel array, as embodiment two-phase, described electric current comparing unit 300 includes a nmos transistor
N1, a 2nd nmos transistor n2 and pmos transistor p1.A described nmos transistor n1 and described 2nd nmos crystal
Pipe n2 constitutes current lens unit, by the pixel cell being inputted by current lens unit current input terminal 100 read current signal i mirror image
For current lens unit current output terminal current signal i ' equal therewith.The drain electrode of a described pmos transistor p1 is described v-
The current output terminal of i converting unit, is connected to Enable Pin en of described counting unit 400, a described pmos transistor p1's
Source electrode connects source voltage, and in the present embodiment, source voltage is a high level, and the grid of a described pmos transistor p1 is changed for v-i
The voltage input end of unit, connects the outfan of the digital to analog converter dac as voltage providing unit 200.
In the present embodiment, when the signal carrying out pel array reads, selected pixel cell 100 is read by column.Tool
Body, the work schedule of the described pel array reading circuit shown in Fig. 9 is as shown in Figure 10.
As most preferred embodiment, the 3rd mos transistor is nmos transistor, and voltage providing unit 200 provides one linearly to increase
Plus voltage signal vramp, the excursion of its this voltage signal vramp is 0～vdd, and it is converted to line through v-i converting unit
Property reduce current signal iramp.Assume to start reading out from jth row pixel.From t0 moment, the row read strobe of jth row
Signal col (j) is changed into high level (when the 3rd mos transistor is pmos transistor, col (j) is changed into low level), gating jth row
Read current signal i (j) of pixel cell 100, now, the voltage vramp of the monotone variation that voltage providing unit 200 provides is
Minima, is converted to the current signal iramp of monotone variation in electric current comparing unit 300 by a pmos transistor p1,
Now, the current signal iramp of described monotone variation corresponds to maximum, and is more than described pixel cell 100 read current signal i
J (), therefore, current comparator unit 300 output voltage vc (j) in Fig. 9 is high level, and counting unit 400 is with clock simultaneously
Signal clk starts counting up.
Until the t1 moment, the current signal iramp of monotone variation is equal to read current signal i (j), i.e. q point in Figure 10,
And then begin to less than read current signal i (j), now current comparator unit 300 output signal vc (j) in Fig. 9 is sent out
Raw upset, is changed into low level, meanwhile, the upset of electric current comparing unit 300 output signal vc (j) makes counting unit 400 stop
Count.Now, count value m1 in count results dout (j) of counting unit 400 output has just been reacted jth row pixel cell and has been read
Go out the size of current signal i (j).In the present embodiment, count value m1 bigger then it represents that read current signal i (j) is less, from
And count value m1 has just reacted the illumination intensity of this pixel cell 100.So far complete the reading of jth row pixel.
It should be noted that as alternative embodiment, voltage providing unit 200 provides a dull voltage signal reducing
Vramp, and the excursion of this voltage signal vramp is vdd～0, it is changed through v-i converting unit in electric current comparing unit 300
For the dull current signal iramp increasing.Now, the upset situation of electric current comparing unit 300 output signal vc (j) and above-mentioned reality
Apply example on the contrary, and count value m1 in count results dout (j) of counting unit 400 output is bigger then it represents that read current is believed
Number i (j) is bigger.
Then, gating signal col (j+1) controls gating jth+1 row pixel, the read current signal i to jth+1 row pixel
(j+1) read, t2～t3 moment as shown in Figure 10, repeated above-mentioned operation, complete the reading of jth+1 row, finally may be used
To be similarly obtained count value m2 of jth+1 row.
In the present embodiment, whole pel array shares an electric current comparing unit 300 and a counting unit 400, institute
State the simplest circuit structure of electric current comparing unit 300 and only include 3 mos transistors, the structure of described counting unit 400 is also very
Simply, therefore reading circuit area is very little, and reading circuit does not include adc module, and therefore power consumption also decreases, thus dropping
The low design complexities Manufacturing cost of image sensor chip.
It is important to note that above-described embodiment one, embodiment two, embodiment three also include and pixel cell and pixel
The corresponding power management module of array and the piece epigraph process circuit needed for subsequently read output signal being processed and correlation
Algoritic module, this technological means being well known to the skilled person, therefore not to repeat here.
In sum, proposed by the invention had based on the pel array reading circuit of half floating transistor low in energy consumption,
The simple feature of structure, has cast out the current signals such as double floating transistor of conventional needle as the pixel cell of read output signal and picture
Adc module in primitive matrix row reading circuit, reduces complexity and the circuit area of reading circuit, thus reducing image sensing
The design cost Manufacturing cost of device chip.So, the present invention effectively overcomes various shortcoming of the prior art and has height
Industrial utilization, for large area array, high-resolution cmos imageing sensor, have higher fill factor, curve factor,
Higher integrated level and lower power consumption, substantially increase chip performance.
Above-described embodiment only principle of the illustrative present invention and its effect, not for the restriction present invention.Any ripe
The personage knowing this technology all can carry out modifications and changes without prejudice under the spirit and the scope of the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete with institute under technological thought without departing from disclosed spirit such as
All equivalent modifications becoming or change, must be covered by the claim of the present invention.
Claims (14)
1. a kind of pixel cell reading circuit, described pixel cell includes half floating transistor, the leakage of described half floating transistor
A photodiode is included, the source electrode of described half floating transistor is the outfan of described pixel cell between pole and half floating boom,
It is characterized in that, described pixel cell reading circuit at least includes: voltage providing unit, electric current comparing unit and counting unit,
Wherein:
The outfan of described pixel cell is suitable to export the read output signal of described pixel cell；
Described voltage providing unit is adapted to provide for the voltage of monotone variation；
Described electric current comparing unit includes two inputs, connects the outfan of described pixel cell respectively and described voltage provides list
The outfan of unit, is suitable to the electric current being monotone variation by the voltage conversion of the monotone variation of described voltage providing unit offer, and
It is compared with the read output signal of described pixel cell, a voltage signal is exported according to comparative result；
Described counting unit includes two inputs, respectively clock signal input terminal and Enable Pin, described clock signal input terminal
Connect clock signal, described Enable Pin connects the outfan of described electric current comparing unit, described counting unit is suitable to calculate clock
The number of times of signal input pulse, and count value is exported according to the control enabling end signal.
2. pixel cell reading circuit according to claim 1 it is characterised in that:
Described voltage providing unit is monotone variation voltage providing unit, is adapted to provide for monotone increasing or the dull voltage letter reducing
Number；
Described electric current comparing unit includes current lens unit and v-i converting unit, and described current lens unit includes current input terminal
And current output terminal；
Described v-i converting unit includes current output terminal and voltage input end, is suitable to for voltage signal to be converted to current signal；
Wherein, the current input terminal of described current lens unit connects the outfan of described pixel cell；Described current lens unit
Current output terminal is connected with the current output terminal of described v-i converting unit, the outfan of as described electric current comparing unit；Described
The outfan of voltage providing unit is connected with the voltage input end of described v-i converting unit.
3. pixel cell reading circuit according to claim 2 it is characterised in that: described voltage providing unit turns for digital-to-analogue
Parallel operation.
4. pixel cell reading circuit according to claim 2 it is characterised in that: described current lens unit includes: first
Nmos transistor and the 2nd nmos transistor, wherein:
The grid of a described nmos transistor is connected with drain electrode, as the current input terminal of described current lens unit, described the
The source ground of one nmos transistor, the grid of a described nmos transistor and the grid phase of described 2nd nmos transistor
Even, the source ground of described 2nd nmos transistor, the drain electrode of described 2nd nmos transistor is as described current lens unit
Current output terminal.
5. pixel cell reading circuit according to claim 2 it is characterised in that: described v-i converting unit includes first
Pmos transistor, a described pmos transistor channel breadth length ratio is more than 50, and the source electrode of a described pmos transistor accesses source
Voltage, the drain electrode of a described pmos transistor is the current output terminal of described v-i converting unit, a described pmos transistor
Grid be described v-i converting unit voltage input end.
6. a kind of pel array reading circuit, described pel array includes at least string pixel cell, and each pixel cell includes
Half floating transistor, the source electrode of half floating transistor in pixel cell described in every string interconnects and as every string
The outfan of pixel cell is it is characterised in that described pel array reading circuit at least includes: voltage providing unit, electric current ratio
Relatively unit and counting unit, wherein:
The outfan of described pixel cell is suitable to export the read output signal of described pixel cell；
Described voltage providing unit is adapted to provide for the electric current of monotone variation；
Described electric current comparing unit includes two inputs, and electric current comparing unit described in connects the defeated of every string pixel cell respectively
Go out the outfan of end and voltage providing unit described in, be suitable to turn the voltage of the monotone variation of described voltage providing unit offer
It is changed to the electric current of monotone variation, and is compared with the read output signal of described pixel cell, a voltage is exported according to comparative result
Signal；
Described counting unit includes two inputs, respectively clock signal input terminal and Enable Pin, described clock signal input terminal
Connect clock signal, described Enable Pin connects the outfan of described electric current comparing unit；Described counting unit is suitable to calculate clock
The number of times of signal input pulse, and count value is exported according to the control enabling end signal.
7. pel array reading circuit according to claim 6 it is characterised in that:
Described voltage providing unit is monotone variation voltage providing unit, is adapted to provide for monotone increasing or the dull voltage letter reducing
Number；
Described electric current comparing unit includes current lens unit and v-i converting unit, and described current lens unit includes current input terminal
And current output terminal；
Described v-i converting unit includes current output terminal and voltage input end, is suitable to for voltage signal to be converted into current signal；
Wherein, the current input terminal of described current lens unit connects the outfan of described every string pixel cell, described current mirror
The current output terminal of unit is connected with the current output terminal of described v-i converting unit, the output of as described electric current comparing unit
End；The outfan of described voltage providing unit is connected with the voltage input end of described v-i converting unit.
8. pel array reading circuit according to claim 7 it is characterised in that: described pel array reading circuit bag
Include:
N row pixel cell, n described electric current comparing unit, n counting unit and a described voltage providing unit, wherein, n
For integer and n >=2；
Each column pixel cell is corresponded with described n electric current comparing unit respectively and is connected, and each electric current comparing unit is individual with n respectively
Described counting unit corresponds and is connected, and in described n electric current comparing unit, the voltage input end of v-i converting unit is connected to
The outfan of described voltage providing unit.
9. pel array reading circuit according to claim 7 it is characterised in that: described pel array reading circuit bag
Include:
N row pixel cell, a described electric current comparing unit, a counting unit, n gating transistor and a described voltage
There is provided unit, wherein, n is integer and n >=2；
Described gating transistor is mos transistor, and its grid connects gating signal, and each described gating transistor is connected to each column picture
Between the outfan of plain unit and described electric current comparing unit, the control source of v-i converting unit in described electric current comparing unit
End is connected with the outfan of described voltage providing unit, the outfan of described electric current comparing unit and the enable of described counting unit
End connects.
10. pel array signal read circuit according to claim 7 it is characterised in that: described voltage providing unit is
Digital to analog converter.
11. pel array signal read circuits according to claim 7 it is characterised in that: described current lens unit includes:
First nmos transistor and the 2nd nmos transistor；
The current input terminal that the grid of a described nmos transistor is connected as described current lens unit with drain electrode, described first
The source ground of nmos transistor, the grid of a described nmos transistor is connected with the grid of described 2nd nmos transistor,
The source ground of described 2nd nmos transistor, the electric current draining as described current lens unit of described 2nd nmos transistor
Outfan.
12. pel array signal read circuits according to claim 7 it is characterised in that: described v-i converting unit includes
First pmos transistor, a described pmos transistor channel breadth length ratio is more than 50, and the drain electrode of a described pmos transistor is
Described current output terminal, is connected with the Enable Pin of described counting unit, and the source electrode of a described pmos transistor accesses source voltage,
The grid of a described pmos transistor is voltage input end, is connected with the outfan of described voltage providing unit.
A kind of 13. pixel cell reading methods are it is characterised in that include: provide as any one of claim 1 to 5
Pixel cell reading circuit；
When reading the read output signal of described pixel cell, described voltage providing unit provides the voltage signal of a monotone variation,
The voltage signal of described monotone variation is converted to the current signal of monotone variation by described electric current comparing unit, and with described pixel
The read output signal of unit is compared；
Meanwhile, described counting unit starts counting up under control of the clock signal, when the read output signal of described pixel cell is equal to
During the current signal of described monotone variation, stop counting and exporting count value.
A kind of 14. pel array reading methods are it is characterised in that include: provide as any one of claim 6 to 12
Pel array reading circuit；
When reading the output current of certain string pixel cell, described voltage providing unit provides the voltage letter of a monotone variation
Number, the voltage signal of described monotone variation is converted to the current signal of monotone variation by described electric current comparing unit, and with described
The read output signal of pixel cell is compared；
Meanwhile, described counting unit starts counting up under control of the clock signal, is equal in the read output signal of described pixel cell
During the current signal of described monotone variation, stop counting and exporting count value.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410095468.3A CN103873791B (en) | 2014-03-14 | 2014-03-14 | Pixel unit read-out circuit and method, and pixel array read-out circuit and method |
| PCT/CN2014/078385 WO2015135257A1 (en) | 2014-03-14 | 2014-05-26 | Pixel unit readout circuit and method therefor, and pixel array readout circuit and method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410095468.3A CN103873791B (en) | 2014-03-14 | 2014-03-14 | Pixel unit read-out circuit and method, and pixel array read-out circuit and method |
Publications (2)
| Publication Number | Publication Date |
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| CN103873791B true CN103873791B (en) | 2017-01-25 |
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| WO (1) | WO2015135257A1 (en) |
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| CN104376815B (en) * | 2014-12-08 | 2017-09-22 | 京东方科技集团股份有限公司 | Pixel-driving circuit, method, display panel and display device |
| CN112399106B (en) * | 2019-08-12 | 2023-04-18 | 天津大学青岛海洋技术研究院 | 4T pixel structure based on semi-floating gate |
| CN113140649B (en) * | 2021-04-13 | 2022-12-27 | 中国科学院上海高等研究院 | Novel photodiode structure, preparation method and circuit structure |
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| US6734413B2 (en) * | 2001-11-06 | 2004-05-11 | Omnivision Technologies, Inc. | Zero DC current readout circuit for CMOS image sensor using a precharge capacitor |
| JP2008136042A (en) * | 2006-11-29 | 2008-06-12 | Sony Corp | Solid-state imaging apparatus and imaging apparatus |
| JP2008187565A (en) * | 2007-01-31 | 2008-08-14 | Sony Corp | Solid-state imaging apparatus and imaging apparatus |
| KR20130000020A (en) * | 2011-06-22 | 2013-01-02 | 삼성디스플레이 주식회사 | Stage circuit and emission driver using the same |
| CN103391407B (en) * | 2013-07-31 | 2016-08-17 | 北京思比科微电子技术股份有限公司 | The dot structure of a kind of cmos image sensor and this imageing sensor |
| CN103685994B (en) * | 2014-01-03 | 2017-01-18 | 中国科学院上海高等研究院 | Fixed-pattern noise (FPN) eliminating circuit of image sensor pixel array |
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| WO2015135257A1 (en) | 2015-09-17 |
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