CN103391407B - The dot structure of a kind of cmos image sensor and this imageing sensor - Google Patents
The dot structure of a kind of cmos image sensor and this imageing sensor Download PDFInfo
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- CN103391407B CN103391407B CN201310329255.8A CN201310329255A CN103391407B CN 103391407 B CN103391407 B CN 103391407B CN 201310329255 A CN201310329255 A CN 201310329255A CN 103391407 B CN103391407 B CN 103391407B
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Abstract
The invention discloses dot structure and this imageing sensor of a kind of cmos image sensor, wherein, this dot structure includes: four pixels, is arranged as three row two column array structures, and the pixel of first row upper end is positioned in same a line with the pixel of secondary series lower end；In this array structure, each pixel is equipped with a photodiode and charge pass transistor, and the pixel of every string shares row selecting transistor, transistor is followed in source, reset transistor and floating active area；The floating active area that every string is shared respectively with the charge pass transistor of these two pixels of row, and the source of these row follows transistor and is connected with reset transistor；The row selecting transistor of these row is followed transistor with the source of these row and is connected；The reset transistor of these row is connected by the output line of this row pixel with the row selecting transistor of these row.By using dot structure disclosed by the invention and imageing sensor, metal window aperture opening ratio and the image quality of little area pixel image sensor of pixel can be effectively improved.
Description
Technical field
The present invention relates to field of semiconductor fabrication, the dot structure and this image that particularly relate to a kind of cmos image sensor pass
Sensor.
Background technology
Imageing sensor has been widely used for digital camera, cell phone, medical apparatus and instruments, automobile and other applied field
Close.Particularly CMOS(CMOS complementary metal-oxide-semiconductor) fast development of imageing sensor, make people to low merit
Consumption small size high-resolution image sensors has had higher requirement.
CMOS image sensor pixel structure of the prior art is owing to depending on the architectural feature of pixel itself, and it is two-dimentional
Pel array is it is generally required to line decoder control metal wire is respectively connecting to charge pass transistor, row selecting transistor and answers
The grid of bit transistor, needs power Metal line and row picture element signal output metal wire, in order to control pel array device and come
Realize gathering the function of photosignal.But, owing to the photosensitive area of small-sized pixel imageing sensor is little, sensitivity
Low so that the information under transmission half-light is clear not, especially employs a plurality of metal interconnecting wires in pel array, causes
Metal window aperture opening ratio is low, blocks some light and incides in photodiode.
Summary of the invention
It is an object of the invention to provide dot structure and this imageing sensor of a kind of cmos image sensor, effectively improve
The metal window aperture opening ratio of pixel, and the image quality of little area pixel image sensor.
It is an object of the invention to be achieved through the following technical solutions:
A kind of dot structure of cmos image sensor, this dot structure includes:
Four pixels, are arranged as three row two column array structures, and the pixel of first row upper end is positioned at the pixel of secondary series lower end
With in a line；Each pixel in this array structure is equipped with a photodiode and the electricity being connected with this photodiode
Lotus transmission transistor, two pixels of every string share row selecting transistor, transistor is followed in source, reset transistor and drift
Floating active area；
Wherein, floating active area that every string is shared respectively with the charge pass transistor of these two pixels of row, and these row
Source is followed transistor and is connected with reset transistor；The row selecting transistor of these row is followed transistor with the source of these row and is connected；Should
The reset transistor of row is connected by the output line of this row pixel with the row selecting transistor of these row.
A kind of cmos image sensor, this imageing sensor includes: several aforesaid dot structures, row controller,
Line decoder, signal reader and signal processing module；
Wherein, several aforesaid dot structures are arranged as m × n-pixel array structure；Described line decoder is located at this array
The side of structure, described row controller and signal reader are respectively arranged on the two ends up and down of this array structure；At described signal
Reason module is connected with described signal reader.
As seen from the above technical solution provided by the invention, by have employed alternating expression structure, save in pel array
Connect the sequencing contro metal wire of reset transistor, and row controller control line and the row pixel of reset transistor will be controlled
Output line shares a row metal wire, is therefore effectively increased the metal window aperture opening ratio of pixel, and reduces drift
The parasitic capacitance of floating active area；On the other hand, using up of little area pixel image sensor can be improved based on said structure
Efficiency and opto-electronic conversion gain, thus improve sensitivity, therefore can be effectively improved the figure of little area pixel image sensor
As quality.
Accompanying drawing explanation
In order to be illustrated more clearly that the technical scheme of the embodiment of the present invention, required use in embodiment being described below
Accompanying drawing is briefly described, it should be apparent that, the accompanying drawing in describing below is only some embodiments of the present invention, for
From the point of view of those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to obtain according to these accompanying drawings
Other accompanying drawings.
The schematic diagram of the dot structure of a kind of cmos image sensor that Fig. 1 provides for the embodiment of the present invention one；
The schematic diagram of a kind of cmos image sensor that Fig. 2 provides for the embodiment of the present invention two；
The line decoder sequential of the cmos image sensor pel array that Fig. 3 provides for the embodiment of the present invention two and row controller
Time diagram.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clearly and completely
Describe, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments.Based on
Embodiments of the invention, it is every other that those of ordinary skill in the art are obtained under not making creative work premise
Embodiment, broadly falls into protection scope of the present invention.
Embodiment one
A kind of CMOS image sensor pixel structure that the embodiment of the present invention one provides, the dot structure of this imageing sensor
Including:
Four pixels, are arranged as three row two column array structures, and the pixel of first row upper end is positioned at the pixel of secondary series lower end
With in a line；Each pixel in this array structure is equipped with a photodiode and the electricity being connected with this photodiode
Lotus transmission transistor, two pixels of every string share row selecting transistor, transistor is followed in source, reset transistor and drift
Floating active area；
Wherein, the floating active area that every string is shared respectively with the charge pass transistor of these two pixels of row, and these row
Source follow transistor and be connected with reset transistor；The row selecting transistor of these row is followed transistor with the source of these row and is connected；
The reset transistor of these row is connected by the output line of this row pixel with the row selecting transistor of these row.
Further, the processing technology of described output line uses 1 layer of metal.
Further, this dot structure can also include:
Netted power supply wire, this power line is connected with the reset transistor shared in first row, secondary series respectively, Yi Ji
The source shared in string, secondary series is followed transistor and is connected.
Further, the processing technology of described power line uses 2 layers of metal.
Further, this dot structure can also include: five sequential output control lines longitudinally arranged；Wherein, control
Line T1 is connected with the charge pass transistor within end pixel under first row；Control line T2 respectively with end pixel on first row and
Under secondary series, the charge pass transistor within end pixel is connected；On control line T3 and secondary series, the electric charge within end pixel passes
Defeated transistor is connected；The row selecting transistor that control line S1 shares with first row is connected；Control line S2 shares with secondary series
Row selecting transistor is connected.
Further, the processing technology of described sequential output control line uses 0 layer of metal.
For the ease of understanding above-mentioned dot structure, 1 it is described further below in conjunction with the accompanying drawings, as it is shown in figure 1, this pixel knot
Structure includes:
Pixel 11, pixel 21, pixel 22 and pixel 32, it is arranged as three row two column array structures, the picture of first row upper end
Element 21 is positioned in same a line with the pixel 22 of secondary series lower end；Pixel 11-pixel 32 is respectively equipped with a photodiode
(PD11-PD32) charge pass transistor (TX11-TX32), and with this photodiode being connected；First row
Two pixels (pixel 11 with pixel 21) share row selecting transistor SX1, transistor SF1, reset transistor are followed in source
RX1 and floating active area FD1；Two pixels of secondary series (pixel 22 and pixel 32) share row selecting transistor SX2,
Transistor SF2, reset transistor RX2 and floating active area FD2 are followed in source.
Wherein, floating active area FD1 respectively with charge pass transistor TX11 and the TX21 of pixel 11 and pixel 21, and
Source is followed transistor SF1 and is connected with reset transistor RX1；Row selecting transistor SX1 follows transistor SF1 and is connected with source；
Reset transistor RX1 and row selecting transistor SX1 is connected by the output line SC1 of this row pixel.
In like manner, floating active area FD2 respectively with charge pass transistor TX22 and the TX32 of pixel 22 and pixel 32, and
Source is followed transistor SF2 and is connected with reset transistor RX2；Row selecting transistor SX2 follows transistor SF2 and is connected with source；
Reset transistor RX2 and row selecting transistor SX2 is connected by the output line SC2 of this row pixel.
Further, this dot structure also includes netted power supply wire Vdd, this power line respectively with first row, secondary series
In the drain electrode of reset transistor (RX1 with RX2) shared be connected, and crystalline substance is followed in source shared in first row, secondary series
The drain electrode of body pipe (SF1 with SF2) is connected.
Further, five line decoders that this dot structure also includes longitudinally arranging sequential output control line (T1,
T2, T3, S1 and S2), wherein, the grid phase of control line T1 and charge pass transistor TX11 within pixel 11
Even；Control line T2 respectively with the grid phase of pixel 21 with the charge pass transistor (TX21 and TX22) within pixel 22
Even；Control line T3 is connected with the grid of charge pass transistor TX32 within pixel 32；Control line S1 shares with first row
Row selecting transistor SX1 grid be connected；The grid phase of the row selecting transistor SX2 that control line S2 shares with secondary series
Even.
Based on above-mentioned annexation, it is known that first row and the wire laying mode of secondary series pixel internal components in the embodiment of the present invention
Completely the same with annexation.
The embodiment of the present invention, by using alternating expression structure, saves the sequencing contro connecting reset transistor in pel array
Metal wire, and the row controller control line controlling reset transistor is shared a row metal with row picture element signal output lead
Line, is therefore effectively increased the metal window aperture opening ratio of pixel, reduces the parasitic capacitance of floating active area；And grid
Shape power Metal interconnection line solves supply voltage attenuation problem；On the other hand, little area can be improved based on said structure
The use light efficiency of pixel image sensor and opto-electronic conversion gain, thus improve sensitivity, therefore can be effectively improved little
The image quality of long-pending pixel image sensor.
Embodiment two
A kind of cmos image sensor that the embodiment of the present invention two provides, this imageing sensor includes: several embodiments
Dot structure described in one, row controller, line decoder, signal reader and signal processing module；
Wherein, the dot structure described in several embodiments one described is arranged as m × n-pixel array structure；Described row is translated
The side of this array structure is located at by code device, and described row controller and signal reader are respectively arranged on up and down the two of this array structure
End；Described signal processing module is connected with described signal reader.
Further, the sequential output control of the longitudinal arrangement with array structure pixel of the line decoder in described imageing sensor
Line processed is connected.
Further, the row controller in described imageing sensor and signal reader respectively with the letter in array structure pixel
Number output lead is connected.
In the imageing sensor of the present embodiment, dot structure is arranged as m × n, and wherein m Yu n can be any positive integer, in order to
Be easy to explanation, the value of m Yu n is all set to 3 by the present embodiment, its structural representation as shown in Figure 2:
In Fig. 2, PD00, PD02 and PD04 are the photodiode of the 1st row pixel, PD10～PD15 is the 2nd row picture
The photodiode of element, PD20～PD25 is the photodiode of the 3rd row pixel, PD30～PD35 is the 4th row pixel
Photodiode, PD40～PD45 is the photodiode of the 5th row pixel, PD50～PD55 is the 6th row pixel
Photodiode, PD61, PD63 and PD65 are the photodiode of the 7th row pixel；TX00, TX02 and TX04 are
The charge pass transistor of the 1st row pixel, TX10～TX15 is the charge pass transistor of the 2nd row pixel, TX20～
TX25 is the charge pass transistor of the 3rd row pixel, TX30～TX35 is the charge pass transistor of the 4th row pixel,
TX40～TX45 is the charge pass transistor of the 5th row pixel, TX50～TX55 is the electric charge transmission crystal of the 6th row pixel
Pipe, TX61, TX63 and TX65 are the charge pass transistor of the 7th row pixel；SX10～SX14, SF10～SF14
It is in the 1st row with RX10～RX14 respectively and the 2nd row shares the 1st in pixel, the row of 3,5 row pixels selects crystal
Transistor and reset transistor are followed in pipe, source；SX21～SX25, SF21～SF25 and RX21～RX25 are position respectively
Share the 2nd in pixel, the row selecting transistor of 4,6 row pixels in the 2nd row and the 3rd row, transistor is followed in source and reset is brilliant
Body pipe；SX30～SX34, SF30～SF34 and RX30～RX34 are in the 3rd row respectively and the 4th row is shared in pixel
The row selecting transistor of the 1st, 3,5 row pixels, source follow transistor and reset transistor；SX41～SX45,
SF41～SF45 and RX41～RX45 be in the 4th row respectively and the 5th row shares the 2nd in pixel, 4,6 row pixels
Row selecting transistor, source follow transistor and reset transistor；SX50～SX54, SF50～SF54 and RX50～
RX54 is in the 5th row respectively and the 6th row shares the 1st in pixel, the row selecting transistor of 3,5 row pixels, source are followed
Transistor and reset transistor；SX61～SX65, SF61～SF65 and RX61～RX65 be in respectively the 6th row and
7th row shares the 2nd in pixel, transistor and reset transistor are followed in the row selecting transistor of 4,6 row pixels, source.
Control line T1 is connected with the grid of charge pass transistor TX00, TX02 and TX04, and control line T2 transmits with electric charge
The grid of transistor TX10～TX15 is connected, and control line T3 is connected with the grid of charge pass transistor TX20～TX25,
Control line T4 is connected with the grid of charge pass transistor TX30～TX35, control line T5 and charge pass transistor
The grid of TX40～TX45 is connected, and control line T6 is connected with the grid of charge pass transistor TX50～TX55, control line
T7 is connected with the grid of charge pass transistor TX61, TX63 and TX65；Control line S1 and row selecting transistor
The grid of SX10～SX14 is connected, and control line S2 is connected with the grid of row selecting transistor SX21～SX25, control line
S3 is connected with the grid of row selecting transistor SX30～SX34, control line S4 and row selecting transistor SX41's～SX45
Grid is connected, and control line S5 is connected with the grid of row selecting transistor SX50～SX54, and control line S6 selects crystal with row
The grid of pipe SX61～SX65 is connected.
The source electrode of row selecting transistor SX10～SX50 of output line SC1 and the 1st row pixel is connected, and arranges with the 1st
The grid of reset transistor RX10～RX50 of pixel is connected；The row of output line SC2 and the 2nd row pixel selects crystal
The source electrode of pipe SX21～SX61 is connected, and is connected with the grid of reset transistor RX21～RX61 of the 2nd row pixel；
The source electrode of row selecting transistor SX12～SX52 of output line SC3 and the 3rd row pixel be connected, and with the 3rd row pixel
Reset transistor RX12～RX52 grid be connected；Output line SC4 and the row selecting transistor of the 4th row pixel
The source electrode of SX23～SX63 is connected, and is connected with the grid of reset transistor RX23～RX63 of the 4th row pixel；Letter
The source electrode of row selecting transistor SX14～SX54 of number output lead SC5 and the 5th row pixel is connected, and with the 5th row pixel
The grid of reset transistor RX14～RX54 is connected；Output line SC6 and the row selecting transistor of the 6th row pixel
The source electrode of SX25～SX65 is connected, and is connected with the grid of reset transistor RX25～RX65 of the 6th row pixel.
Floating active area FD in each shared pixel follows the grid of transistor SF respectively and is connected with each other with respective sources；Vdd is
Power Metal interconnection line, forms fenestral fabric, respectively with the SF transistor in each shared pixel and RX in pel array
The drain electrode of transistor is connected with each other.
Sequential output control line T1～T7, the S1-S6 of the longitudinal direction arrangement in the present embodiment are line decoder 201(and can arrange
Left side or right side at pel array) control line, in chip fabrication technique use the 0th layer of metal；Row picture element signal is defeated
Outlet SC1～SC6 is upper end or the lower end that row controller 202(may be provided at pel array) control line, in chip system
Make technique uses the 1st layer of metal；Floating active area FD in each shared pixel and respective sources follow the grid of transistor SF
Interconnective metal wire uses 1 layer of metal in processing technology；The power Metal interconnection line Vdd of fenestral fabric, at core
Sheet processing technology uses the 2nd layer of metal.
Further, image sensor pixel array photosignal be may be provided at the upper of pel array by signal reader 203(
End or lower end) read by row picture element signal output lead and preserve after, entering signal processing module 204 is further processed.
The primary structure of the cmos image sensor provided for the present invention above, 3 for this image sensing below in conjunction with the accompanying drawings
Operation principle and the flow process of device are described further.
As it is shown on figure 3, the line decoder output timing used by the cmos image sensor pel array of the present invention and row
Controller timing schematic diagram, in present invention pixel array, all uses N-type transistor, N-type transistor grid to be set to high electricity
Flat, the sequential line i.e. controlling this transistor gate is set to high level, represents and opens transistor；N-type transistor grid is set to low
Level, the sequential line i.e. controlling this transistor gate is set to low level, shows to close transistor；The N-type transistor opening time
Length, the sequential line i.e. controlling this transistor gate is set to high level time length, imageing sensor work concrete condition
Depending on；When signal-obtaining device bottom pel array reads signal, SC line is converted to letter by row controller timing control line
Number output lead, signal-obtaining device reads signal by output line.Table when SC1～SC6 sequential is solid line in figure 3
Levy SC line current potential and controlled by arranging control device, characterize SC line when its sequential is dotted line and be converted to row picture element signal output lead；
Characterize when SHR and SHS is high level and read row pixel reset signal 1 and photosignal 2, the true photosignal of pixel respectively
=reset signal 1-photosignal 2.
When cmos image sensor pel array of the present invention normally works, use row roller Exposure mode, the 1st row pixel
Being first begin to exposure, then the 2nd row pixel starts exposure, followed by the 3rd row, 4 row, 5 row, 6 row, 7 row；Row with
The order that the order of the end exposure between row pixel starts with exposure is identical；Signal-obtaining order between row and row pixel
Also identical with the order that row pixel exposure starts.When imageing sensor gathers same frame pel array signal, often row pixel
Time of exposure is equal.
Sequential operation below for the 3rd row pixel elaborates.SC1～SC6 and T3 before the pixel exposure cycle starts
Sequential do simultaneously one high level pulse operation, the electric charge in the 3rd row pixel photodiode is all removed, this journey pixel from
T3 pulse falling edge starts exposure.Before end exposure, sequential SC1～SC6 do a high level pulse operation, by pixel
In floating active area FD do one reset operation, high potential will be set to by FD, after reset operation completes, SC1～SC6 is by arranging
Controller control line is changed into row picture element signal output lead；Subsequently, S2 and S3 is set to high level, opens the 3rd row pixel
Row selecting transistor；After opening the row selecting transistor of the 3rd row pixel, SHR sequential does a high level pulse operation, reads
Take the reset potential in the 3rd row pixel FD, be denoted as signal 1；T3 sequential does a high level pulse operation subsequently, by the 3rd row
Photo-electric charge in pixel photodiode is transferred in the floating active area FD of respective pixel respectively；Photo-electric charge has shifted
Bi Hou, SHS sequential does a high level pulse operation, reads the photoelectricity electromotive force in the 3rd row pixel FD, is denoted as signal 2；Letter
Number read after, S2 and S3 is reverted to low level, and SC1～SC6 is changed into row by row picture element signal output lead
Controller control line, carries out the operation of next line pixel.
Above-mentioned sequential operation is only in pel array the sequential operation of wherein 1 row pixel, and in pel array, all row pixels are by suitable
After sequence is sequentially completed aforesaid operations, referred to as imageing sensor one frame signal reads complete.
The embodiment of the present invention, by using alternating expression structure, saves the sequencing contro connecting reset transistor in pel array
Metal wire, and the row controller control line controlling reset transistor is shared a row metal with row picture element signal output lead
Line, is therefore effectively increased the metal window aperture opening ratio of pixel, reduces the parasitic capacitance of floating active area；And grid
Shape power Metal interconnection line solves supply voltage attenuation problem；On the other hand, little area can be improved based on said structure
The use light efficiency of pixel image sensor and opto-electronic conversion gain, thus improve sensitivity, therefore can be effectively improved little
The image quality of long-pending pixel image sensor.
Those skilled in the art is it can be understood that arrive, for convenience and simplicity of description, only with above-mentioned each function mould
The division of block is illustrated, and in actual application, can distribute above-mentioned functions by different function moulds as desired
Block completes, and the internal structure of device will be divided into different functional modules, with complete described above in whole or in part
Function.
The above, the only present invention preferably detailed description of the invention, but protection scope of the present invention is not limited thereto,
Any those familiar with the art in the technical scope of present disclosure, the change that can readily occur in or replace
Change, all should contain within protection scope of the present invention.Therefore, protection scope of the present invention should be with claims
Protection domain is as the criterion.
Claims (9)
1. the dot structure of a cmos image sensor, it is characterised in that this dot structure includes:
Four pixels, are arranged as three row two column array structures, and the pixel of first row upper end is positioned at the pixel of secondary series lower end
With in a line；Each pixel in this array structure is equipped with a photodiode and the electricity being connected with this photodiode
Lotus transmission transistor, two pixels of every string share row selecting transistor, transistor is followed in source, reset transistor and drift
Floating active area；
Wherein, the floating active area that every string is shared respectively with the charge pass transistor of these two pixels of row, and these row
Source follow transistor and be connected with reset transistor；The row selecting transistor of these row is followed transistor with the source of these row and is connected；
The grid of the reset transistor of these row selects the source electrode pipe of crystal to pass through the output line phase of this row pixel with the row of these row
Even.
Dot structure the most according to claim 1, it is characterised in that make in the processing technology of described output line
With 1 layer of metal.
Dot structure the most according to claim 1, it is characterised in that this dot structure also includes:
Netted power supply wire, this power line is connected with the reset transistor shared in first row, secondary series respectively, Yi Ji
The source shared in string, secondary series is followed transistor and is connected.
Dot structure the most according to claim 3, it is characterised in that use gold in the processing technology of described power line
Belong to 2 layers.
Dot structure the most according to claim 1, it is characterised in that this dot structure also includes: longitudinally arrange for five
The sequential output control line of cloth；Wherein, control line T1 is connected with the charge pass transistor within end pixel under first row；
Control line T2 is connected with the charge pass transistor within end pixel under end pixel on first row and secondary series respectively；Control line
T3 is connected with the charge pass transistor within end pixel on secondary series；The row that control line S1 and first row are shared selects crystal
Pipe is connected；The row selecting transistor that control line S2 shares with secondary series is connected.
Dot structure the most according to claim 5, it is characterised in that the processing technology of described sequential output control line
0 layer of middle use metal.
7. a cmos image sensor, it is characterised in that this imageing sensor includes: several claim 1-6
Dot structure, row controller, line decoder, signal reader and signal processing module described in any one；
Wherein, several dot structures described in any one of claim 1-6 described are arranged as m × n-pixel array structure；Institute
Stating line decoder and be located at the side of this array structure, described row controller and signal reader are respectively arranged on this array structure
Two ends up and down；Described signal processing module is connected with described signal reader.
Imageing sensor the most according to claim 7, it is characterised in that the line decoder in described imageing sensor
It is connected with the sequential output control line of longitudinally arrangement in array structure pixel.
Imageing sensor the most according to claim 7, it is characterised in that the row controller in described imageing sensor with
Signal reader is connected with the output line in array structure pixel respectively.
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| KR20210010018A (en) * | 2019-07-19 | 2021-01-27 | 에스케이하이닉스 주식회사 | Image sensing device |
| CN111726550B (en) * | 2020-08-05 | 2023-04-07 | 锐芯微电子股份有限公司 | Image sensor pixel circuit and working method thereof |
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| US8735795B2 (en) * | 2012-01-20 | 2014-05-27 | Omnivision Technologies, Inc. | Image sensor with integrated ambient light detection |
| CN102595057B (en) * | 2012-02-27 | 2014-09-24 | 北京思比科微电子技术股份有限公司 | CMOS (complementary metal-oxide-semiconductor transistor) image sensor pixel and control time sequence thereof |
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