CN103391408B - Pixel structure of CMOS (complementary metal-oxide-semiconductor transistor) image sensor and image sensor - Google Patents
Pixel structure of CMOS (complementary metal-oxide-semiconductor transistor) image sensor and image sensor Download PDFInfo
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Abstract
The invention discloses a pixel structure of a CMOS image sensor and the image sensor. The image sensor comprises four pixels, and the four pixels are arranged into a 2*2 pixel matrix type array structure; each pixel in the array structure is provided with a photodiode and a charge transfer transistor connected with the photodiode; two pixels in each column share a row selection transistor, a source following transistor, a reset transistor and a floating active area; a floating active area shared by each column is connected with charge transfer transistors of two pixels of the column and the source following transistor and the reset transistor of the column respectively; the row selection transistor and the source following transistor of the column are connected; and the reset transistor and the row selection transistor of the column are connected through signal transmission lines of the pixels of the column. According to the pixel structure and the image sensor, the opening rate of a metal window of the pixels can be effectively increased, and the image quality of a small-area pixel image sensor is improved.
Description
Technical field
The present invention relates to field of semiconductor fabrication, more particularly, to a kind of dot structure of cmos image sensor and this image
Sensor.
Background technology
Imageing sensor has been widely used for digital camera, cell phone, medicine equipment, automobile and other application field
Close.Particularly CMOS（CMOS complementary metal-oxide-semiconductor）The fast development of imageing sensor, make people to low-power consumption little chi
Very little high-resolution image sensors have higher requirement.
, due to depending on the architectural feature of pixel itself, it is two-dimentional for CMOS image sensor pixel structure of the prior art
Pel array generally requires line decoder and controls metal wire to be respectively connecting to charge pass transistor, row selecting transistor and reset
The grid of transistor, needs power Metal line and row picture element signal output metal wire, to control pel array device to realize
The function of collection photosignal.But, because the photosensitive area of small-sized pixel sensor is little, sensitivity is low so that transmission is dark
Information under light is not clear, especially employs a plurality of metal interconnecting wires in pel array, leads to metal window aperture opening ratio low,
Block some light to incide in photodiode.
Content of the invention
It is an object of the invention to provide a kind of dot structure of cmos image sensor and this imageing sensor, effectively carry
The high metal window aperture opening ratio of pixel, and the image quality of small area pixel image sensor.
The purpose of the present invention is achieved through the following technical solutions：
A kind of dot structure of cmos image sensor, this dot structure includes：
Four pixels, are arranged as 2 × 2 picture element matrix formula array structures；Each pixel in this array structure is equipped with one
Photodiode and the charge pass transistor being connected with this photodiode, two pixels of each row are shared row and are selected crystalline substance
Body pipe, source follow transistor, reset transistor and floating active area；
Wherein, the shared floating active area charge pass transistor with this two pixel of row respectively of each row, and should
The source of row is followed transistor and is connected with reset transistor；The row selecting transistor of this row is followed transistor with the source of this row and is connected；
The reset transistor of this row is connected by the output line of this row pixel with the row selecting transistor of this row.
A kind of cmos image sensor, this imageing sensor includes：Several aforesaid pixels, row controller, row decoding
Device, signal reader and signal processing module；
Wherein, several aforesaid pixel arrangements are m × n-pixel matrix array structure；Described line decoder is located at this
The side of array structure, described row controller and signal reader are respectively arranged on the upper and lower ends of this array structure；Described signal
Processing module is connected with described signal reader.
As seen from the above technical solution provided by the invention, by employing 4T2S structure（Two, four transistors
Pixel is shared）, and eliminate the SECO metal wire connecting reset transistor in pel array, and reset controlling
The row controller control line of transistor shares a row metal wire with row picture element signal output line, therefore effectively increases pixel
Metal window aperture opening ratio, and reduce the parasitic capacitance of floating active area；On the other hand, can be improved based on said structure little
The use light efficiency of area pixel image sensor and opto-electronic conversion gain, thus improving sensitivity, therefore can effectively improve little
The image quality of area pixel image sensor.
Brief description
In order to be illustrated more clearly that the technical scheme of the embodiment of the present invention, below will be to required use in embodiment description
Accompanying drawing be briefly described it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this
For the those of ordinary skill in field, on the premise of not paying creative work, other can also be obtained according to these accompanying drawings
Accompanying drawing.
A kind of schematic diagram of the dot structure of cmos image sensor that Fig. 1 provides for the embodiment of the present invention one；
A kind of schematic diagram of cmos image sensor that Fig. 2 provides for the embodiment of the present invention two；
The line decoder sequential of the cmos image sensor pel array that Fig. 3 provides for the embodiment of the present invention two and row control
Device time diagram.
Specific embodiment
With reference to the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Ground description is it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments.Based on this
Inventive embodiment, the every other enforcement that those of ordinary skill in the art are obtained under the premise of not making creative work
Example, broadly falls into protection scope of the present invention.
Embodiment one
A kind of CMOS image sensor pixel structure that the embodiment of the present invention one provides, the dot structure of this imageing sensor
Including：
Four pixels, are arranged as 2 × 2 picture element matrix formula array structures；Each pixel in this array structure is equipped with one
Photodiode and the charge pass transistor being connected with this photodiode, two pixels of each row are shared row and are selected crystalline substance
Body pipe, source follow transistor, reset transistor and floating active area；
Wherein, the shared floating active area charge pass transistor with this two pixel of row respectively of each row, and should
The source of row is followed transistor and is connected with reset transistor；The row selecting transistor of this row is followed transistor with the source of this row and is connected；
The reset transistor of this row is connected by the output line of this row pixel with the row selecting transistor of this row.
Further, using 1 layer of metal in the manufacture craft of described output line.
Further, this dot structure can also include：
Netted power supply wire, this power line is connected with shared reset transistor in first row, secondary series respectively, Yi Ji
In one row, secondary series, shared source is followed transistor and is connected.
Further, using 2 layers of metal in the manufacture craft of described power line.
Further, this dot structure can also include：4 sequential export control lines longitudinally arranged；Wherein, control line
T1 is connected with the charge pass transistor within two pixels of the second row respectively；Control line T2 two pictures with the first row respectively
Charge pass transistor within element is connected；The row selecting transistor that control line S is shared with first row is connected；Control line S ' and the
The shared row selecting transistor of two row is connected.
Further, using 0 layer of metal in the manufacture craft of described sequential export control line.
Further, this dot structure can also include：
The top that transistor is arranged at this row pixel is followed in shared row selecting transistor in first row pixel and source, will
In secondary series pixel, the bottom that transistor is arranged at this row pixel is followed in shared row selecting transistor and source；
Or, the bottom that transistor is arranged at this row pixel is followed in shared row selecting transistor in first row pixel and source
Portion, the top that transistor is arranged at this row pixel is followed in shared row selecting transistor in secondary series pixel and source.
For the ease of understanding above-mentioned dot structure, 1 it is described further below in conjunction with the accompanying drawings, as shown in figure 1, this pixel knot
Structure includes：
Pixel 11, pixel 12, pixel 21 and pixel 22, it is arranged as 2 × 2 picture element matrix formula array structures；Pixel 11- picture
It is respectively equipped with a photodiode in element 22（PD11-PD22）, and the charge pass transistor being connected with this photodiode
（TX11-TX22）；Two pixels of first row（Pixel 11 and pixel 21）Transistor is followed in shared row selecting transistor SX1, source
SF1, reset transistor RX1 and floating active area FD1；Two pixels of secondary series（Pixel 12 and pixel 22）Shared row selects brilliant
Body pipe SX2, source follow transistor SF2, reset transistor RX2 and floating active area FD2.
Wherein, floating active area FD1 charge pass transistor TX11 and the TX21 with pixel 11 and pixel 21 respectively, and
Source is followed transistor SF1 and is connected with reset transistor RX1；Row selecting transistor SX1 follows transistor SF1 with source and is connected；Reset
Transistor RX1 is connected by the output line SC1 of this row pixel with row selecting transistor SX1.
In the same manner, floating active area FD2 charge pass transistor TX12 and the TX22 with pixel 12 and pixel 22 respectively, and
Source is followed transistor SF2 and is connected with reset transistor RX2；Row selecting transistor SX2 follows transistor SF2 with source and is connected；Reset
Transistor RX2 is connected by the output line SC2 of this row pixel with row selecting transistor SX2.
Further, also include netted power supply wire Vdd in this dot structure, this power line respectively with first row, second
Shared reset transistor in row（RX1 and RX2）Drain electrode be connected, and crystal is followed in shared source in first row, secondary series
Pipe（SF1 and SF2）Drain electrode be connected.
Further, this dot structure also includes the sequential export control line of longitudinal four line decoders arranged（T1、
T2, S and S '）, wherein, control line T1 respectively with pixel 11 and the charge pass transistor within pixel 12（TX11 and TX12）'s
Grid is connected；Control line T2 respectively with pixel 21 and the charge pass transistor within pixel 22（TX21 and TX22）Grid phase
Even；The grid of the row selecting transistor SX1 that control line S is shared with first row is connected；The row choosing that control line S ' and secondary series are shared
The grid selecting transistor SX2 is connected.
Based on above-mentioned annexation, can be by shared row selecting transistor SX1 in first row pixel in this dot structure
Follow the top that transistor SF1 is arranged at this row pixel with source, by shared row selecting transistor SX2 in secondary series pixel and source
Follow the bottom that transistor SF2 is arranged at this row pixel；Or, by shared row selecting transistor SX1 in first row pixel with
The bottom that transistor SF1 is arranged at this row pixel is followed in source, by shared row selecting transistor SX2 in secondary series pixel and source with
It is arranged at the top of this row pixel with transistor SF2.
The embodiment of the present invention adopts 4T2S structure（Two pixels of four transistors are shared）, and save in pel array
Connect the SECO metal wire of reset transistor, and row controller control lines and the row pixel that reset transistor will be controlled
Output line shares a row metal wire, therefore effectively increases the metal window aperture opening ratio of pixel, reduces floating active
The parasitic capacitance in area；And latticed power Metal interconnection line solves supply voltage attenuation problem；On the other hand, based on above-mentioned
Structure can improve use light efficiency and the opto-electronic conversion gain of small area pixel image sensor, thus improving sensitivity, therefore
The image quality of small area pixel image sensor can be effectively improved.
Embodiment two
A kind of cmos image sensor that the embodiment of the present invention two provides, this imageing sensor includes：Several embodiments
Dot structure described in one, row controller, line decoder, signal reader and signal processing module；
Wherein, the dot structure described in several embodiments one described is arranged as m × n-pixel matrix array structure；
Described line decoder is respectively arranged on this array structure located at the side of this array structure, described row controller and signal reader
Upper and lower ends；Described signal processing module is connected with described signal reader.
Further, the line decoder in described image sensor and the sequential export arranged longitudinal in array structure pixel
Control line is connected.
Further, the row controller in described image sensor and signal reader respectively with array structure pixel in
Output line is connected.
In the imageing sensor of the present embodiment, dot structure is arranged as m × n, wherein m and n can be any positive integer, be
It is easy to illustrate, the value of m and n is all set to 3 by the present embodiment, and its structural representation is as shown in Figure 2：
In Fig. 2, PD11～PD16 is the photodiode of the 1st row pixel, and PD21～PD26 is the photoelectricity two of the 2nd row pixel
Pole pipe, PD31～PD36 is the photodiode of the 3rd row pixel, and PD41～PD46 is the photodiode of the 4th row pixel, PD51
～PD56 is the photodiode of the 5th row pixel, and PD61～PD66 is the photodiode of the 6th row pixel；TX11～TX16 is
The charge pass transistor of the 1st row pixel, TX21～TX26 is the charge pass transistor of the 2nd row pixel, and TX31～TX36 is
The charge pass transistor of the 3rd row pixel, TX41～TX46 is the charge pass transistor of the 4th row pixel, and TX51～TX56 is
The charge pass transistor of the 5th row pixel, TX61～TX66 is the charge pass transistor of the 6th row pixel；SX21～SX26,
Transistor is followed in the row selecting transistor that SF21～SF26 and RX21～RX26 is in the 1st row and the 2nd row pixel respectively, source
And reset transistor, SX41～SX46, SF41～SF46 and RX41～RX46 are in the 3rd row and the 4th row pixel respectively
Row selecting transistor, source follow transistor and reset transistor, and SX61～SX66, SF61～SF66 and RX61～RX66 are respectively
Transistor and reset transistor are followed in row selecting transistor in the 5th row and the 6th row pixel, source.
Control line T1 is connected with the grid of charge pass transistor TX11～TX16 respectively, and control line T2 is passed with electric charge respectively
The grid of defeated transistor TX21～TX26 is connected, the control line T3 grid phase with charge pass transistor TX31～TX36 respectively
Even, control line T4 is connected with the grid of charge pass transistor TX41～TX46 respectively, and control line T5 transmits brilliant respectively with electric charge
The grid of body pipe TX51～TX56 is connected, and control line T6 is connected with the grid of charge pass transistor TX61～TX66 respectively.
Control line S2 is connected with the grid of SX25 with row selecting transistor SX21, SX23, and control line S2 ' selects crystal with row
Pipe SX22, SX24 are connected with the grid of SX26, and control line S4 is connected with the grid of SX45 with row selecting transistor SX41, SX43,
Control line S4 ' is connected with the grid of SX46 with row selecting transistor SX42, SX44, control line S6 and row selecting transistor SX61,
SX63 is connected with the grid of SX65, and control line S6 ' is connected with the grid of SX66 with row selecting transistor SX62, SX64.
Output line SC1 is connected with the grid of reset transistor RX21, RX41 and RX61 of the 1st row pixel, and with
The source electrode of row selecting transistor SX21, SX41, SX61 is connected；Output line SC2 and the reset transistor of the 2nd row pixel
RX22, RX42 are connected with the grid of RX62, and are connected with the source electrode of row selecting transistor SX22, SX42, SX62；Signal output
Line SC3 is connected with the grid of reset transistor RX23, RX43 and RX63 of the 3rd row pixel, and with row selecting transistor SX23,
The source electrode of SX43, SX63 is connected；The grid of reset transistor RX24, RX44 and RX64 of output line SC4 and the 4th row pixel
It is connected, and be connected with the source electrode of row selecting transistor SX24, SX44, SX64；Output line SC5 is answered with the 5th row pixel
Bit transistor RX25, RX45 are connected with the grid of RX65, and are connected with the source electrode of row selecting transistor SX25, SX45, SX65；
Output line SC6 is connected with the grid of reset transistor RX26, RX46 and RX66 of the 6th row pixel, and selects crystalline substance with row
The source electrode of body pipe SX26, SX46, SX66 is connected.
The grid that floating active area FD in each shared pixel follows transistor SF respectively with respective sources is connected with each other；Vdd
For power Metal interconnection line, pel array forms fenestral fabric, respectively with each shared pixel in SF transistor and RX
The drain electrode of transistor is connected with each other.
The sequential export control line T1 of the longitudinal direction arrangement in the present embodiment～T6, S2 and S2 ', S4 and S4 ', S6 and S6 ' are all
For line decoder 201（May be provided at the left and right sides both sides of pel array）Control line, using the 0th layer in chip fabrication technique
Metal；Row picture element signal output line SC1～SC6 is row controller 202（May be provided at upper end or the lower end of pel array）Control
Line processed, using the 1st layer of metal in chip fabrication technique；Floating active area FD in each shared pixel and respective sources follow crystal
The interconnective metal wire of grid of pipe SF is in manufacture craft using 1 layer of metal；The power Metal interconnection line of fenestral fabric
Vdd, using the 2nd layer of metal in chip fabrication technique.
Further, image sensor pixel array photosignal is by signal reader 203（May be provided at pel array
Upper end or lower end）After being read and preserved by row picture element signal output line, entering signal processing module 204 is further processed.
The primary structure of the cmos image sensor providing for the present invention above, 3 is directed to this image biography below in conjunction with the accompanying drawings
The operation principle of sensor and flow process are described further.
As shown in figure 3, the line decoder output timing being adopted by the cmos image sensor pel array of the present invention and
Row controller timing schematic diagram, in present invention pixel array, can be all using N-type transistor, N-type transistor grid is set to height
Level, that is, control the sequential line of this transistor gate to be set to high level, represent and open transistor；N-type transistor grid is set to low
Level, that is, control the sequential line of this transistor gate to be set to low level, shows to close transistor；The N-type transistor opening time is long
Short, that is, control the sequential line of this transistor gate to be set to high level time length, depending on imageing sensor work concrete condition.
During the signal-obtaining device read signal of pel array bottom, SC line is converted to signal output by row controller timing control line
Line, signal-obtaining device passes through output line read signal.SC1～SC6 sequential is for characterizing SC line current potential during solid line in figure 3
Controlled by row control device, its sequential is converted to row picture element signal output line for characterizing SC line during dotted line；SHR and SHS is high electricity
Characterize at ordinary times and read row pixel reset signal 1 and photosignal 2, the true photosignal of pixel=reset signal 1- photoelectricity respectively
Signal 2.
During cmos image sensor pel array normal work of the present invention, using row roller Exposure mode, the 1st row pixel
It is first begin to expose, then the 2nd row pixel starts to expose, followed by the 3rd row, 4 row, 5 row, 6 row；Between row and row pixel
The order that the order of end exposure is started with exposure is identical；Row and row pixel between signal-obtaining order also with row pixel exposure
The order starting is identical.When imageing sensor gathers same frame pel array signal, often the time for exposure of row pixel is equal.
Sequential operation below for the 3rd row pixel elaborates.Before the pixel exposure cycle starts SC1～SC6 and
T3 sequential do simultaneously one high level pulse operation, the electric charge in the 3rd row pixel photodiode is all removed, this journey pixel from
T3 pulse falling edge starts to expose.Before end exposure, sequential SC1～SC6 does a high level pulse operation, will float in pixel
Active area FD does a reset operation, will float active area FD and be set to high potential, and after the completion of the operation that resets, SC1～SC6 is by arranging control
Device control line processed is changed into row picture element signal output line；Subsequently, S4 and S4 ' is set to high level, opens the row choosing of the 3rd row pixel
Select transistor；After opening the row selecting transistor of the 3rd row pixel, SHR sequential does a high level pulse operation, reads the 3rd row picture
Reset potential in element floating active area FD, is denoted as signal 1；Subsequently T3 sequential does a high level pulse operation, by the 3rd row pixel
Photo-electric charge in photodiode is transferred in the floating active area FD of respective pixel respectively；After photo-electric charge transfer finishes,
SHS sequential does a high level pulse operation, reads the photoelectricity potential in the 3rd row pixel FD, is denoted as signal 2；Signal-obtaining finishes
Afterwards, S4 and S4 ' is reverted to low level, and SC1～SC6 is changed into row controller control line by row picture element signal output line；
So far, the signal-obtaining of the third line pixel finishes.
Above-mentioned sequential operation is only the sequential operation of wherein 1 row pixel in pel array, all row pixels in pel array
It is sequentially completed after aforesaid operations finish in order, referred to as imageing sensor one frame signal reads and finishes.
The embodiment of the present invention adopts 4T2S structure（Two pixels of four transistors are shared）, and save in pel array
Connect the SECO metal wire of reset transistor, and row controller control lines and the row pixel that reset transistor will be controlled
Output line shares a row metal wire, therefore effectively increases the metal window aperture opening ratio of pixel, reduces floating active
The parasitic capacitance in area；And latticed power Metal interconnection line solves supply voltage attenuation problem；On the other hand, based on above-mentioned
Structure can improve use light efficiency and the opto-electronic conversion gain of small area pixel image sensor, thus improving sensitivity, therefore
The image quality of small area pixel image sensor can be effectively improved.
Those skilled in the art can be understood that, for convenience and simplicity of description, only with above-mentioned each function
The division of module is illustrated, and in practical application, can distribute above-mentioned functions by different function moulds as desired
Block completes, and the internal structure of device will be divided into different functional modules, to complete all or part of work(described above
Energy.
The above, the only present invention preferably specific embodiment, but protection scope of the present invention is not limited thereto,
Any those familiar with the art in the technical scope of present disclosure, the change or replacement that can readily occur in,
All should be included within the scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of claims
Enclose and be defined.
Claims (9)
1. a kind of dot structure of cmos image sensor is it is characterised in that this dot structure includes：
Four pixels, are arranged as 2 × 2 picture element matrix formula array structures；Each pixel in this array structure is equipped with a photoelectricity
Diode and the charge pass transistor being connected with this photodiode, two pixels of each row are shared row and are selected crystal
Pipe, source follow transistor, reset transistor and floating active area；
Wherein, the shared floating active area charge pass transistor with this two pixel of row respectively of each row, and this row
Source is followed transistor and is connected with reset transistor；The row selecting transistor of this row is followed transistor with the source of this row and is connected；This row
Reset transistor be connected by the output line of this row pixel with the row selecting transistor of this row；
This dot structure also includes：
Netted power supply wire, this power line is connected with shared reset transistor in first row, secondary series respectively, and first
In row, secondary series, shared source is followed transistor and is connected.
2. dot structure according to claim 1 is it is characterised in that using gold in the manufacture craft of described output line
Belong to 1 layer.
3. dot structure according to claim 1 is it is characterised in that using metal 2 in the manufacture craft of described power line
Layer.
4. dot structure according to claim 1 is it is characterised in that this dot structure also includes：Four longitudinal arrangements
Sequential export control line；Wherein, control line T1 is connected with the charge pass transistor within two pixels of the second row respectively；Control
Line T2 processed is connected with the charge pass transistor within two pixels of the first row respectively；The row that control line S is shared with first row
Select transistor is connected；The row selecting transistor that control line S ' is shared with secondary series is connected.
5. dot structure according to claim 4 is it is characterised in that make in the manufacture craft of described sequential export control line
With 0 layer of metal.
6. dot structure according to claim 1 is it is characterised in that this dot structure also includes：
The top that transistor is arranged at this row pixel is followed in shared row selecting transistor in first row pixel and source, by second
In row pixel, the bottom that transistor is arranged at this row pixel is followed in shared row selecting transistor and source；
Or, the bottom that transistor is arranged at this row pixel is followed in shared row selecting transistor in first row pixel and source,
The top that transistor is arranged at this row pixel is followed in shared row selecting transistor in secondary series pixel and source.
7. a kind of cmos image sensor is it is characterised in that this imageing sensor includes：Several any one of claim 1-6
Described dot structure, row controller, line decoder, signal reader and signal processing module；
Wherein, several dot structures described in any one of claim 1-6 described are arranged as m × n-pixel matrix array knot
Structure；Described line decoder is respectively arranged on this array junctions located at the side of this array structure, described row controller and signal reader
The upper and lower ends of structure；Described signal processing module is connected with described signal reader.
8. imageing sensor according to claim 7 is it is characterised in that the line decoder in described image sensor and battle array
In array structure pixel, the sequential export control line of longitudinally arrangement is connected.
9. imageing sensor according to claim 7 is it is characterised in that the row controller in described image sensor and letter
Number reader is connected with the output line in array structure pixel respectively.
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| CN102158663A (en) * | 2011-04-15 | 2011-08-17 | 北京思比科微电子技术股份有限公司 | CMOS (Complementary Metal Oxide Semiconductor) image sensor pixel and control time sequence thereof |
| CN102868866A (en) * | 2012-09-24 | 2013-01-09 | 北京思比科微电子技术股份有限公司 | CMOS (complementary metal oxide semiconductor) image sensor column-sharing 2X2 pixel unit and CMOS image sensor pixel array |
| CN103139498A (en) * | 2013-03-21 | 2013-06-05 | 北京思比科微电子技术股份有限公司 | Pixel unit of complementary metal oxide semiconductor (CMOS) image sensor and CMOS image sensor |
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