CN108848326A - A kind of high dynamic range MCP detector front end reading circuit and its reading method - Google Patents
A kind of high dynamic range MCP detector front end reading circuit and its reading method Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
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Abstract
The invention discloses a kind of high dynamic range MCP detector front end reading circuit and its reading methods, belong to semiconductor image detection technology field, including signal input module, dynamic range expansion module, buffer module, high-speed comparator module, time-to-digital converter module and application of logic circuit module；Wherein, photo-signal from detector, enter front end reading circuit by signal input module, then the processing of integral and dynamic range expansion is carried out by dynamic range expansion module, voltage signal after integral carries out buffered by buffer module, it is then transferred to high-speed comparator module, the high speed comparison module includes first comparator and the second comparator.The present invention is used for the decision process of input signal power to be put into inside pixel and be handled, and without complicated back-end processing procedures, is simplified the design process of back-end circuit, is kept whole chip architecture simple, and pixel packing ratio is high, and chip area utilization rate is good.
Description
Technical field
The invention belongs to semiconductor image detection technology fields, specifically design a kind of high dynamic range MCP detector front end
Reading circuit and its reading method.
Background technique
Fast neutron radiography technology is analysed in depth by measuring targets, can obtain detailed material internal characteristic,
To realize the function of carrying out non-destructive testing to complex article and structure, in condensed state physics, Materials Science and Engineering, the earth
Science with and multiple basic science fields such as bioscience have extensive demand and application.
Applied to the single-photon detector in fast neutron radiography field, single-photon sensitivity is not only needed to have, it is also necessary to energy
High time stamp accuracy is carried out to the photon that each moment reaches, and records the high-precision spatial two-dimensional coordinate of the photon simultaneously,
Require the three-dimensional high-spatial and temporal resolution detector of single-photon sensitivity.
Microchannel plate (Microchannel plate, abbreviation MCP) can work under pulse-counting mode, while have both several
Ten picoseconds of response time and several microns of spatial resolving power become the face battle array photoelectric conversion of single-photon detector first choice
One of device combines it with different charge distribution and processing apparatus, can be formed with single-photon sensitivity it is three-dimensional at
As detector.In addition, MCP has many advantages, such as can to work under high-intensity magnetic field, dark noise is very small.
Dynamic range (DR) is an important indicator of single-photon detector, indicates the light intensity that the detector can be handled
The unit of range, dynamic range is indicated with decibel (dB).One of factor of limited dynamic range is exactly the integral electricity inside pixel
Hold size (i.e. trap capacity), the more big detectable light intensity of capacitor is bigger.
During single photon detection, the characteristics of to meet photon emission source super brightness and ultra-wide power spectrum, reading circuit
There must be very high dynamic range, but if only increase integrating capacitor, will lead to unit pixel area and be consequently increased.
So to consider the compromise of performance and area in the design process of front end reading circuit, area should be reduced, reduce power consumption,
Dynamic range is improved again.
In recent years, the research of fast neutron radiography technical field causes academia and widely pays close attention to, in the world also continuous
It is proposed the scientific achievement of new material, high performance MCP single-photon detector, but in terms of MCP detector reading circuit
Research sets foot in less, aims at the research of high-performance ASIC chip that MCP detector signal reads and designs and is substantially at blank.
In addition, there is no make optimization for this performance parameter of dynamic range in traditional MCP detector front end reading circuit design
Processing, causes the input reference signal of entire single-photon detection system very small, application field compares limitation.
In order to give full play to the advantages of MCP possesses single photon detection ability, is applied in fast neutron radiography system, adopted
It not can guarantee under the conditions of high count rate with traditional reading circuit structure while having obtained high-precision spatial resolution capability and height
Precision Time resolution capability, when the electric charge number of MCP output is excessive, traditional circuit framework based on charge amplifier can cause
Signal saturation, can not accurate calculated charge number.Currently, existing read output signal processing scheme is improving system performance such as dynamic
The effect is unsatisfactory for range and resolution ratio etc., and dynamic range can be improved and can reduce by not proposing one kind in the industry
The ideal scheme of chip area.
Summary of the invention
In order to solve the above-mentioned technical problems, the present invention provides a kind of high dynamic range MCP detector front end reading circuits
And its reading method, using multiple electric charge transfer logic (similar to the asynchronous logic gradual approaching redistributed based on charge
Number converter), it is possible to provide the input signal dynamic range of ultra-wide.
The present invention is achieved through the following technical solutions：
A kind of high dynamic range MCP detector front end reading circuit, including signal input module, dynamic range expansion mould
Block, buffer module (AMP), high-speed comparator module (CMP), time-to-digital converter module (TDC) and application of logic circuit module
(LOGIC)；Wherein, from the photo-signal of detector, enter front end reading circuit by signal input module, then pass through
Dynamic range expansion module carries out the processing of integral and dynamic range expansion, and the voltage signal after integrating passes through buffer mould
Block carries out buffered, is then transferred to high-speed comparator module, the high speed comparison module includes first comparator CMP1
And the second comparator CMP2, the comparison result of first comparator are converted into digital signal by time-to-digital converter module, then
Data storage is carried out, the comparison result of the second comparator generates the switch control of dynamic range expansion module by application of logic circuit module
Signal processed.
Further, the signal input module includes two input signal electrodes of PAD and TP, and wherein PAD is MCP
Electron cloud charge collection electrode, TP are the input signal electrode of test, and the two is connected to same by test switch Test
Output node.
Further, the dynamic range expansion module, including the first sampling capacitance C1, the second sampling capacitance C2,
One switch S1, second switch S2And third switch S3；Wherein, the first sampling capacitance C1With the second sampling capacitance C2For carrying out charge
Storage, C1One terminated wires ground terminal (GND), the other end and S1It connects together, node A；C2One terminated wires ground connection
End, the other end and S2It connects together, node B, S1And S2The other end is all connected to reference potential VREF, S3Both ends be coupled with
Node A and B.
Further, the buffer module is unit gain amplifier, it is using Differential Input Single-end output
Amplifier architecture, reverse input end connects together with output end, makes closed loop gain 1.
Further, the threshold voltage of the first comparator and the second comparator is different；First comparator is used to sentence
Determine the time of input signal arrival；Second comparator is used to determine the saturation state of front end reading circuit.
Further, the time-to-digital converter module includes thick counting module and carefully counts module, thick counting module
For being counted roughly to arrival time, carefully counts module for counting arrival time in detail, to improve resolution ratio,
Then count results static random access memory (SRAM) is output to store.
Further, the logic module, including not overlapped by the combinational logic part constituted with door or door and two-phase
Clock generates part, calculates first switch S according to the output signal of the second comparator1, second switch S2, third switch S3's
Signal logic relationship is controlled, dynamic range expansion module is then returned to.
Above-mentioned high dynamic range MCP detector front end reading circuit can be according to S1、S2、S3The control signal of three switches
Logical relation (is provided) by logic module, by charge respectively in C1、C2It is shifted between two integrating capacitors, it is higher to obtain
Input signal dynamic range.Specifically, the reading method of high dynamic range MCP detector front end reading circuit, specific steps
It is as follows：
One, when initial state, first switch S1, second switch S2It closes, third switch S3It opens, to the first sampling capacitance C1、
Second sampling capacitance C2Reset to VREF, reference voltage VREFFor supply voltage 3.3V；
Two, when there is the transmitting of electron cloud signal, the emitting portion of detection system can generate an enabling signal：START letter
Number, when the START signal arrives, circuit starts to start, first switch S1, second switch S2It opens；
Three, time-to-digital converter module starts timing after receiving enabling signal, and entire reading circuit waits electron cloud
The arrival of signal；After PAD receives input charge, the first sampling capacitance C1Start to integrate, the integral voltage is via buffering
Device module transfer gives high-speed comparator module；
Four, the reference voltage V of first comparator CMP1TH1For supply voltage 3.3V, when there is charge input, comparator
Output is flipped, STOP signal of the comparison result as time-to-digital converter module, so that it is stopped timing, during which time number
Arrival time measured by word conversion module is converted into digital signal deposit SRAM memory；
Five, the output signal of buffer module can also pass to the second comparator CMP2, with reference voltage VTH2Compare, really
Recognize whether reading circuit reaches saturation state；If input node voltage is negative value, illustrate that circuit is in a saturated state, if into
After saturation state, then second switch S is opened2, close third switch S3, by the first sampling capacitance C1In half charge be injected into
Second sampling capacitance C2, to increase the first sampling capacitance C1On voltage；Then again by second switch S2Conducting, third switch
S3It disconnects, disconnects the first sampling capacitance C1With the second sampling capacitance C2Connection, to the second sampling capacitance C2Carry out reset discharge；
The first sampling capacitance C is judged again1Charge size is again turned on second switch S2, close third switch S3, carry out the first sampling
Capacitor C1, the second sampling capacitance C2Between charge transfer；So circulation, until circuit is detached from saturation state, i.e. buffer mould
The input terminal voltage of block rises to 0V or more, and the second comparator CMP2 restores initial potential；
Six, by first switch S1, second switch S2And third switch S3It all disconnects, buffer module output the first sampling electricity
Hold C1Integral voltage, record the first sampling capacitance C1The times N of electric discharge and its residual voltage V of outputs, release of discharging it is total
The quantity of electric charge is Q0, the residual charge of output is Qs=C1Vs, total input charge amount is Q0+Qs。
Compared with prior art, advantages of the present invention is as follows：
1, the characteristics of dark current (not being dark counting), is not had based on MCP, in conjunction with high dynamic cmos image sensor circuit frame
The advantages of structure, reading circuit of the invention is using multiple electric charge transfer logic (similar to the asynchronous logic redistributed based on charge
Gradual approaching A/D converter), it is possible to provide the input signal dynamic range of ultra-wide.
2, the dynamic range expansion modular structure that the present invention uses is simple, it is only necessary to can be realized more using two capacitors
Big dynamic range reduces pixel area.
3, level of integrated system is high, and the decision process of input signal power is put into inside pixel and handles by the present invention, nothing
Complicated back-end processing procedures are needed, the design process of back-end circuit is simplified, keeps whole chip architecture simple, pixel packing ratio
Height, chip area utilization rate are good.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of traditional MCP detector front end reading circuit；
Fig. 2 is the structural schematic diagram of MCP detector front end reading circuit of the invention；
Fig. 3 is the working timing figure of MCP detector front end reading circuit of the invention；
Fig. 4 is the transient working characteristic and simulation result of the embodiment of the present invention 1；
Specific embodiment
MCP neutron detector reading circuit of the present invention and 0.18 μm of standard CMOS process are completely compatible, tie below
Drawings and examples are closed the chip is described in detail.
Embodiment 1
As shown in Fig. 2, a kind of high dynamic range MCP detector front end reading circuit, including signal input module, dynamic model
Enclose expansion module, buffer module (AMP), high-speed comparator module (CMP), time-to-digital converter module (TDC) and logic electricity
Road module (LOGIC)；Wherein, from the photo-signal of detector, enter front end reading circuit by signal input module, so
The processing of integral and dynamic range expansion is carried out by dynamic range expansion module afterwards, the voltage signal after integrating is through too slow
It rushes device module and carries out buffered, be then transferred to high-speed comparator module, the high speed comparison module compares including first
The comparison result of device CMP1 and the second comparator CMP2, first comparator are converted into digital letter by time-to-digital converter module
Number, data storage is then carried out, the comparison result of the second comparator generates dynamic range expansion module by application of logic circuit module
Switch control signal.
The signal input module includes two input signal electrodes of PAD and TP, and wherein PAD is MCP electron cloud charge
Passive electrode, TP are the input signal electrode of test, and the two is connected to same output node by testing switch Test.
Wherein, signal input module includes two electrodes of PAD and TP, is the importation of entire front end reading circuit, they are all
Individually defined metal layer, related to technique in CMOS technology.
The dynamic range expansion module, including the first sampling capacitance C1, the second sampling capacitance C2, first switch S1,
Two switch S2And third switch S3；Wherein, the first sampling capacitance C1With the second sampling capacitance C2For carrying out the storage of charge, and
Its capacitance size is equal.C1One terminated wires ground terminal (GND), the other end and S1It connects together, node A；C2One termination electricity
Line ground terminal, the other end and S2It connects together, node B, S1And S2The other end is all connected to reference potential VREF, S3Both ends point
It is not connected to node A and B.First switch S1With second switch S2All as the reset switch of integrating capacitor, they are using complementation
CMOS structure design.And in order to further optimize the efficiency of electric charge transfer, third switch S3It is switched using Boostrap.
In order to save area and reduce the parasitic influence to capacitance, the first sampling capacitance C1With the second sampling capacitance C2It is all made of MOM
Capacitance structure.
The buffer module is unit gain amplifier (AMP), it puts using Differential Input Single-end output
Big device structure, reverse input end are connected together with output end, make closed loop gain 1.
Amplifier can directly adopt Willy Sansen and exist using track to track amplifier architecture《Analogous Integrated Electronic Circuits
Design is succinct》In circuit structure.
The high-speed comparator module is to be compared to analog signal, to obtain time data and dynamic model
The switching logic relationship of expansion module is enclosed, it compares device by Pyatyi Cascade cascade amplifier and cross-coupling and forms,
Middle cross coupled amplifier can directly adopt Phillip E.Allen and exist《CMOS analogue layout (second edition)》In
The structure of P386.The threshold voltage of the first comparator and the second comparator is different；First comparator is used to determine to input
The time that signal reaches；Second comparator is used to determine the saturation state of front end reading circuit.
For the time-to-digital converter module using the working principle of vernier method, it includes thick counting module and thin meter
Digital-to-analogue block, what thick counting module obtained is high-order count results, and what carefully counts module obtained is the count results of low level, they
The digital signal for indicating arrival time is collectively constituted, SRAM is then output to and is stored.
The logic module, including being generated by the combinational logic part constituted with door or door and the not overlapping clock of two-phase
Part, it is therein to be made of with door and/or door the standard logical unit that CMOS technology provides.According to the output of the second comparator
Signal calculates first switch S1, second switch S2, third switch S3Control signal logic relationship, be then returned to dynamic model
Enclose expansion module.
The working sequence of the present embodiment is shown in Fig. 3, and when course of work is such：
System clock of the present invention is 320MHz.When initial state, S1、S2It closes, S3It opens, to two integral electricity
Hold C1、C2Reset to VREF.In the present invention, reference voltage VREFFor as supply voltage 3.3V.When enabling signal START arrives,
Circuit starts to start, switch S1、S2It opens.TDC module starts timing after receiving enabling signal, and entire reading circuit waits
The arrival of electron cloud signal.After PAD receives input charge, C1Capacitor starts to integrate.The integral voltage increases via unit
Beneficial amplifier AMP is transferred to high-speed comparator module.Arrival time determines the reference voltage VTH1 of comparator CMP1 for power supply electricity
Press 3.3V, as long as therefore have charge input, the output of comparator will be flipped.The comparison result is as TDC module
STOP signal makes it stop timing, and arrival time measured by period TDC module is converted into digital signal deposit SRAM storage
In device.
In addition, the output signal of AMP can also pass to input dynamic range comparator CMP2, with reference voltage VTH2Than
Compared with whether confirmation reading circuit reaches saturation state.It, can be due to charging when the electron cloud electric charge number that PAD is received is larger
Capacitor C1It is smaller that voltage is caused to be rapidly decreased to negative value, cause amplifier AMP output saturation, AMP input node voltage 0V.CMP2
Reference voltage be set as 0V, when circuit reaches saturation state, C1The integral voltage at place is negative value, and AMP output voltage is maintained at
0V, CMP2 is overturn at this time.The comparison result generates S by LOGIC module2、S3Control signal.After entering saturation state, beat
Open S2, close S3, by C1In half charge be injected into C2, to increase C1On voltage.Then again by S2Conducting, S3It disconnects,
Disconnect C1With C2Connection, to C2Carry out reset discharge.C is judged again1Charge size is said if input node voltage is still negative value
Bright circuit is again turned on S still in saturation state2, close S3, carry out C1、C2Between charge transfer.So circulation, Zhi Dao electricity
Road is detached from saturation state, and AMP input terminal voltage rises to 0V or more, and CMP2 is restored to initial potential.Finally, by all switches
S1、S2、S3It all disconnects, buffer module exports C1Integral voltage.Record capacitor C1The times N of electric discharge and its residual voltage of output
VsInput charge amount Q=C can be obtained in (can be converted further into digital signal)1×(VREF-VS)×2N。
Fig. 4 is the simulation result carried out to circuit front-end analog portion, and horizontal axis is simulation time, unit ns.When emulation,
Input charge amount is set as 1 × 107Electronics, the integrating capacitor C in pixel circuit1、C2It is 200fF.According to Q=CV, tradition electricity
The quantity of electric charge reaches 4.125 × 10 when road input capacitance is 200fF6When circuit, circuit can reach saturation state.Whole system when
Clock is 320MHz, and 20ns is divided between reset signal twice.For utility C2To C1Charge will not be lost during electric discharge,
S2、S3Control switch signal need to for two-phase not overlap clock.Due to C1、C2Capacitance size is identical, therefore each electric charge transfer
Amount should be the half of input charge total amount, as can be known from Fig. 4, input charge 107It needs to input by discharging twice when electronics
Voltage is just positive value.By emulation it is found that input voltage is finally maintained at 1.3838V, capacitor residue charging voltage 2.026V,
Then initial charge voltage is 22× 2.013=8.042V (ideally should be 8V).
Claims (8)
1. a kind of high dynamic range MCP detector front end reading circuit, which is characterized in that including signal input module, dynamic model
Enclose expansion module, buffer module, high-speed comparator module, time-to-digital converter module and application of logic circuit module；Wherein, it comes from
The photo-signal of detector enters front end reading circuit by signal input module, then passes through dynamic range expansion module
The processing for carrying out integral and dynamic range expansion, the voltage signal after integrating carry out buffered by buffer module,
It is then transferred to high-speed comparator module, the high speed comparison module includes first comparator CMP1 and the second comparator
The comparison result of CMP2, first comparator are converted into digital signal by time-to-digital converter module, then carry out data storage,
The comparison result of second comparator generates the switch control signal of dynamic range expansion module by application of logic circuit module.
2. a kind of high dynamic range MCP detector front end reading circuit as described in claim 1, which is characterized in that described
Signal input module includes two input signal electrodes of PAD and TP, and wherein PAD is MCP electron cloud charge collection electrode, and TP is to survey
Input signal electrode on probation, the two are connected to the same output node by testing switch Test.
3. a kind of high dynamic range MCP detector front end reading circuit as described in claim 1, which is characterized in that described
Dynamic range expansion module, including the first sampling capacitance C1, the second sampling capacitance C2, first switch S1, second switch S2And third
Switch S3；Wherein, the first sampling capacitance C1With the second sampling capacitance C2For carrying out the storage of charge, C1One terminated wires ground connection
End, the other end and S1It connects together, node A；C2One terminated wires ground terminal, the other end and S2It connects together, node B,
S1And S2The other end is all connected to reference potential VREF, S3Both ends be coupled with node A and B.
4. a kind of high dynamic range MCP detector front end reading circuit as described in claim 1, which is characterized in that described
Buffer module is unit gain amplifier, using the amplifier architecture of Differential Input Single-end output, reverse input end
It is connected together with output end, makes closed loop gain 1.
5. a kind of high dynamic range MCP detector front end reading circuit as described in claim 1, which is characterized in that described
The threshold voltage of first comparator and the second comparator is different；First comparator is used to determine the time that input signal reaches；The
Two comparators are used to determine the saturation state of front end reading circuit.
6. a kind of high dynamic range MCP detector front end reading circuit as described in claim 1, which is characterized in that described
Time-to-digital converter module includes thick counting module and carefully counts module, and thick counting module is by carrying out based on roughly arrival time
Count results, to improve resolution ratio, are then output to static state for being counted in detail to arrival time by number, carefully counts module
Random access memory is stored.
7. a kind of high dynamic range MCP detector front end reading circuit as described in claim 1, which is characterized in that described
Logic module, including generating part by the combinational logic part constituted with door or door and the not overlapping clock of two-phase, according to the second ratio
Output signal compared with device calculates first switch S1, second switch S2, third switch S3Control signal logic relationship, then return
Back to dynamic range expansion module.
8. a kind of reading method of high dynamic range MCP detector front end reading circuit as described in claim 1, feature
It is, specific step is as follows：
One, when initial state, first switch S1, second switch S2It closes, third switch S3It opens, to the first sampling capacitance C1, second
Sampling capacitance C2Reset to VREF, reference voltage VREFFor supply voltage 3.3V；
Two, when there is the transmitting of electron cloud signal, the emitting portion of detection system can generate an enabling signal：START signal,
Circuit starts to start when the START signal arrives, first switch S1, second switch S2It opens；
Three, time-to-digital converter module starts timing after receiving enabling signal, and entire reading circuit waits electron cloud signal
Arrival；After PAD receives input charge, the first sampling capacitance C1Start to integrate, the integral voltage is via buffer mould
Block is transferred to high-speed comparator module；
Four, the reference voltage V of first comparator CMP1TH1For supply voltage 3.3V, when there is charge input, the output of comparator
It is flipped, STOP signal of the comparison result as time-to-digital converter module, it is made to stop timing, during which time figure turns
Arrival time measured by mold changing block is converted into digital signal deposit SRAM memory；
Five, the output signal of buffer module can also pass to the second comparator CMP2, with reference voltage VTH2Compare, confirmation is read
Whether circuit reaches saturation state out；If input node voltage is negative value, illustrate that circuit is in a saturated state, if entering saturation
After state, then second switch S is opened2, close third switch S3, by the first sampling capacitance C1In half charge be injected into second
Sampling capacitance C2, to increase the first sampling capacitance C1On voltage；Then again by second switch S2Conducting, third switch S3It is disconnected
It opens, disconnects the first sampling capacitance C1With the second sampling capacitance C2Connection, to the second sampling capacitance C2Carry out reset discharge；Again
Judge the first sampling capacitance C1Charge size is again turned on second switch S2, close third switch S3, carry out the first sampling capacitance
C1, the second sampling capacitance C2Between charge transfer；So circulation, until circuit is detached from saturation state, i.e., buffer module is defeated
Enter to hold voltage to rise to 0V or more, the second comparator CMP2 restores initial potential；
Six, by first switch S1, second switch S2And third switch S3It all disconnects, buffer module exports the first sampling capacitance C1's
Integral voltage records the first sampling capacitance C1The times N of electric discharge and its residual voltage V of outputs, the total electricity for release of discharging every time
Lotus amount is Q0, the residual charge of output is Qs=C1Vs, total input charge amount is Q0+Qs。
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| CN115086580A (en) * | 2022-07-18 | 2022-09-20 | 昆明钍晶科技有限公司 | Pixel-level analog-to-digital conversion digital reading circuit and infrared detector |
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