CN110926623B - Time-amplitude conversion circuit with high dynamic range and measurement method thereof - Google Patents
Time-amplitude conversion circuit with high dynamic range and measurement method thereof Download PDFInfo
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Abstract
The invention discloses a time-amplitude conversion circuit with a high dynamic range, which belongs to the technical field of single photon detection and comprises an integral timing module and a row selection reading module, wherein the input end of the integral timing module is respectively connected with the output ends of integral signal generation logic and feedback control logic, and the output end of the integral timing module is respectively connected with the input ends of the feedback control logic and the row selection reading module; the invention also discloses a measuring method thereof, which utilizes a scheme of detecting the photon flight time at a simulation timing, adopts a folding integral method and monitors the charge of the positive plate of the integral capacitor, effectively improves the dynamic range of voltage swing, improves time resolution and measuring precision while ensuring small layout area, low power consumption and pixel filling factor of a circuit, reduces clock feed-through effect at a switch node, effectively slows down electric leakage phenomenon after the switch is closed, improves retention time, reduces manufacturing cost, has good performance consistency among circuits and high yield.
Description
Technical Field
The invention belongs to the technical field of single photon detection, and particularly relates to a time-amplitude conversion circuit with a high dynamic range and a measuring method thereof.
Background
The Single-Photon Avalanche photodiode (SPAD) has the remarkable advantages of high Avalanche gain, high Single-Photon response speed, high detection sensitivity, low manufacturing cost, low power consumption and the like, can obtain time and space information of Photon signals, and has wide application prospects in the aspects of laser ranging, bioluminescence life imaging, 3D imaging and the like.
At present, a photon flight Time measurement method based on Time-to-Digital conversion (TDC) is mainly adopted for a Time-to-Digital converter (TDC) based single photon imaging chip, although a TDC circuit has high Time resolution and strong noise suppression capability and anti-interference capability, the TDC circuit is complex in structure, large in transistor quantity, high in power consumption and large in occupied chip area, filling factors of pixel units of an integrated detector are seriously influenced, and array density and integration degree are low.
Under the large background that the process size is continuously reduced, the detection accuracy, the distance resolution and the time resolution are effectively improved, the area of a pixel unit needs to be reduced, and the improvement of the filling factor of the pixel unit becomes a problem to be solved urgently.
The circuit implementation scheme of the Time-to-Amplitude conversion (TAC) method is simple, the number of the adopted transistors is far smaller than that of the TDC circuit, and the fill factor of the pixel unit can be significantly improved, so that further research on the TAC circuit is necessary.
However, the integrated voltage of the existing TAC circuit is limited by the power supply voltage, the voltage swing range is small, the voltage cannot be quantized with high precision, and the problems of short full-scale time, low time resolution and the like exist, so that a novel TAC circuit structure is very necessary to be provided.
Disclosure of Invention
The purpose of the invention is as follows: the invention aims to provide a time-amplitude conversion circuit with a high dynamic range and a measuring method thereof, which are applied to a single photon detector, wherein within a fixed integral duration, the voltage integral range is improved in multiples, so that the measuring range is enlarged, the time resolution is improved, the complexity of the circuit and the area of the circuit are reduced, the filling factor of a pixel unit is effectively increased, and the integration level of an array can be greatly improved.
The technical scheme is as follows: in order to achieve the purpose, the invention provides the following technical scheme:
a time-amplitude conversion circuit with a high dynamic range comprises an integral timing module and a row selection reading module, wherein the input end of the integral timing module is respectively connected with the output ends of an integral signal generation logic and a feedback control logic, and the output end of the integral timing module is respectively connected with the input ends of the feedback control logic and the row selection reading module; the input signals of the integration timing module comprise an external reset signal Rst and an external input reference voltage VbiasAnd the output end of the integration Signal generating logic is used for generating an Integral _ Signal which is input to the integration timing module; the input signals of the integration signal generating logic comprise an external Photon avalanche signal Photon, an external Start signal Start and an external Stop signal Stop; the input signal of the row selection reading module is an external row selection reading signal Read, and the row selection is performedThe output Out of the sense module is connected to an external output.
Further, the integrated signal generating logic comprises two RS flip-flops AND an AND gate AND1, wherein the two RS flip-flops are RSFF1 AND RSFF2 respectively; the 1 setting end S of the RSFF1 is connected with an external Photon avalanche signal Photon, the 0 setting end R of the RSFF1 is connected with an external Stop signal Stop, AND an Integral Enable signal Integral _ Enable generated by the output end Q of the RSFF1 is connected with one input end of an AND gate 1; the 1 setting end S of the RSFF2 is connected with an external Start Signal Start, the 0 setting end R of the RSFF2 is connected with an external Stop Signal Stop, an integration interval Signal Integral _ Range generated at the Q end of the output end of the RSFF2 is connected with the other input end of the AND gate AND1, AND an Integral _ Signal Signal output by the AND gate AND1 is connected with an integration timing module.
Furthermore, the integration timing module comprises two integration capacitors, three NMOS (N-channel metal oxide semiconductor) tubes, a first PMOS (P-channel metal oxide semiconductor) tube, an operational amplifier A1 and a constant current source Ibias(ii) a The two integrating capacitors are respectively C1 and C2, the three NMOS transistors are respectively MN0, MN1 and MN4, and the first PMOS transistor is MP 0; the gate of MN4 is connected with the integrated Signal Integral _ Signal generated at the output end of the AND gate AND1 in the integrated Signal generation logic, the drain of MN4 is connected with the constant current source IbiasThe negative electrode of the constant current source I is connected with the negative electrode of the anodebiasThe positive electrodes of the C1 and the C2 are connected with each other and are connected with the source electrode of MN4, the drain electrode of MN0 and the non-inverting input end of the operational amplifier A1; the inverting input end of the operational amplifier A1 is connected with the Flag signal Flag generated by the output end of the operational amplifier A1 and is connected to the non-inverting input end of the operational amplifier A2 in the feedback control logic; the negative plate of the C1 is mutually connected to the ground, and the negative plate of the C2 is connected with the drain of MN1 and the drain of MP 0; the gate of the MN0 is connected to an external reset signal Rst, the source of MN0 is connected to ground, the source of MN1 is connected to ground, the gate of MN1 and the gate of MP0 are connected together with feedback control logic, and the source of MP0 is connected to a power supply voltage VDD.
Further, the feedback control logic comprises an operational amplifier A2, two NMOS transistors, a second PMOS transistor, an AND gate AND0, AND oneNOR gate NOR and an inverter INV 0; the two NMOS transistors are respectively MN2 and MN3, and the second PMOS transistor is MP 1; wherein, the non-inverting input end of the operational amplifier A2 is connected with a Flag signal Flag generated by the output end of the operational amplifier A1 in the integral timing module; the inverting input end of the operational amplifier A2 is connected with an external input reference voltage VbiasThe output end of the operational amplifier A2 is respectively connected with the drain of MN2, the gate of MN3 and the gate of MP 1; the gate of the MN2 is connected with an external reset signal Rst, and the source of the MN2 is connected with the ground; the source of the MP1 is connected with a power supply voltage VDD, the drain of the MP1 is connected with the drain of the MN3 AND is connected with one input end of an AND gate 0, AND the drain of the MN3 is connected with the ground; the other input end of the AND gate AND0 is connected with the output end of the inverter INV0, the output end of the AND gate AND0 is connected to one input end of the NOR gate NOR, the other input end of the NOR gate NOR is connected to the external reset Signal Rst, the output end of the NOR gate NOR is connected with the input end of the inverter INV0, AND the quadratic integration enable Signal Second _ Signal generated by the NOR gate NOR is connected with the integration timing module.
Further, the row selection readout module comprises a third PMOS transistor, and the third PMOS transistor comprises MP2 and MP 3; the gate of the MP2 is connected to the positive plate of the C1, the positive plate of the C2, the drain of the MN0, the source of the MN4 and the non-inverting input terminal of the operational amplifier a1, the drain of the MP2 is connected to ground, the source of the MP2 is connected to the drain of the MP3, the gate of the MP3 is connected to the external row selection Read signal Read, and the source of the MP3 is connected to the output terminal Out.
Furthermore, an integrating capacitor C2, MOS transistors MP0 AND MN1, AND an AND gate AND0, a NOR gate NOR AND an inverter INV0 in the feedback control logic in the integration timing module form a double folding type integration measuring circuit, when n times of folding integral measurement is carried out, n-2 groups of integral folding measurement units are added in the twice folding integral measurement circuit by the n times of folding integral measurement circuit, the integral folding measurement unit comprises an integral capacitor Cn, a PMOS tube MP, an NMOS tube MN, a Buffer, an OR gate Or, an AND gate AND, a NOR gate NOR AND an inverter INV, the output of the Or gate Or is connected with an AND gate AND in the feedback control logic, one input end of the Or gate Or is connected with the drains of a PMOS transistor MP1 AND an NMOS transistor MN3, the other input end of the Or gate Or is connected with the output end of a Buffer, AND the input end of the Buffer is connected with the output end of INV0 in the original twice-folding integral measuring circuit; in addition, the input end of the NOR gate NOR is connected with an external reset signal Rst, the output end of the NOR gate NOR is connected with the grids of a PMOS tube MP and an NMOS tube MN and is recorded as an n-time integral enabling signal n _ Enable, the positive plate of the integral capacitor Cn is connected with the positive plates of the integral capacitors C1 and C2, the negative plate of the NOR gate NOR is connected with the drain electrodes of the NMOS tube MN and the PMOS tube MP, the source electrode of the MN is grounded, and the source electrode of the MP is connected with a power supply VDD, wherein n is more than or equal to 3.
Further, a measuring method of a time-amplitude conversion circuit with a high dynamic range, namely measuring on a double folding type integrating circuit, comprises the following steps:
1) starting a reset phase: when a system is powered on, resetting and clearing are carried Out on the system, an external reset signal Rst becomes a high level, the voltages on the positive plates of C1 and C2 are cleared, and the output end Out of the system is cleared; the output end secondary integration Enable signal Second _ Enable of the NOR gate NOR is in low level, and the system only needs to integrate the voltage not to exceed the external input reference voltage V in the first period of integration processbiasThe Second integral Enable signal Second _ Enable is always kept at a low level; then, the Start signal for emitting laser changes to high level, the system starts emitting laser to detect an object, the integration Enable signal integration _ Enable is triggered by the Start signal Start to change to high level under the action of the RSFF2, the circuit starts integrating, and the system waits for photons returning;
2) and (3) an integration timing stage: when the Photon signal Photon returns to be detected, the constant current source IbiasThe first charging period of C1 begins, when the integrated voltage fails to reach the external input reference voltage VbiasThe output end of the operational amplifier A2 is at low level, so that C2 is not turned on and cannot participate in the integration of the first stage; when the integrated voltage of C1 rises to the external input reference voltage VbiasValue of (A)When the negative plate of the integrating capacitor C2 is pulled to a low level, the integrating capacitor C1 and the integrating capacitor C2 are connected in parallel and enter the integration of the second stage together until the external Stop signal Stop becomes a high level;
3) a timing stopping stage: when the external Stop Signal Stop becomes high level, the output Integral Signal Integral _ Signal also becomes low level, the constant current source IbiasStopping supplying current to the integrating capacitors C1 and C2, stopping integrating, and keeping the voltage values on C1 and C2 unchanged; at the moment, the circuit realizes folding integration, and the voltage swing is multiplied;
4) a signal reading stage: when the external Stop signal Stop is ended, the external row selection Read signal Read is changed from the initial high level to the low level, and the voltage values on C1 and C2 are transmitted to the output end Out; the invention releases the first section of integration voltage by using a comparator and using C2, restarts the integration of a new section of integration to expand the swing range of the integration voltage, and judges that the first section of integration voltage is necessary to be the external input reference voltage V if the Second integration Enable signal Second _ Enable is high levelbiasThen the total voltage value is Vtotal=Vbias+VsecondWhile the magnitude of the second integrated voltage is varied by adjusting the value of C2; if the Second integration Enable signal Second _ Enable is at a low level, it indicates that the integrated voltage fails to reach the external input reference voltage value, and then the voltage value is directly read out; therefore, when the time of the returned Photon signal Photon is detected to be early, the integration time is long, two-section integration is carried out, and the voltage swing is large; if the returned Photon signal Photon is detected late, the integration time is short, then a section of integration is carried out, and the voltage swing is small; therefore, the integral voltage swing amplitude is enlarged, and the measurement range and the time resolution are directly improved; the integral voltage value is in linear proportional relation with the photon flight time, so that the measuring time T is calculated according to the output voltage valuemeasureWhile the time interval T of the external Start signal Start and the external Stop signal Stop is knowntotalAccording to the formula TOF = Ttotal-TmeasureThe photon time of flight TOF is calculated.
Further, more than three folding integrals are realized on the basis of the twice folding integrals, AND firstly, a control logic of an integral capacitor Cn, a PMOS tube MP, an NMOS tube MN, a Buffer, an OR gate Or, an AND gate AND, an NOR gate NOR AND an inverter INV is added; secondly, connecting a newly added three-time integration enabling signal n _ Enable output by AND-OR gate control logic to the gates of a PMOS tube MP and an NMOS tube MN for controlling three-time integration enabling, wherein the measuring method comprises the following steps of clearing a positive plate of C1 when a first-time integration voltage reaches an external input reference voltage Vbias, sending a second feedback signal to C2 to start secondary folding integration, invalidating the three-time integration enabling signal n _ Enable if the integration voltage does not exceed the external reference voltage Vbias when the second-time folding integration is started, not triggering the third-time folding integration, enabling the three-time integration enabling signal by the three-time control logic output by an operational amplifier A2 if the integration voltage exceeds the external reference voltage Vbias, and starting an integration capacitor Cn to be connected with the C1 and the C2 in parallel, namely entering the third-time folding integration; if more than three folding integrals are needed, the integral measurement unit is folded and increased, and the same logic process is carried out on the n integral enabling times on the basis of three times, namely, the folding integrals more than three times are realized.
Has the advantages that: compared with the prior art, the time-amplitude conversion circuit with the high dynamic range adopts two integrating capacitors C1, C2 and 9 MOS transistors, selects the minimum-size MOS and the small-size integrating capacitor, thereby ensuring the circuit density and the integration level, and adopts the CMOS process for manufacturing, thereby having low manufacturing cost, good consistency of each level of circuit and high yield; the circuit adopts a logic control unit comprising two RSFF1 AND RSFF2, two operational amplifier units A1 AND A2, two AND gates AND0 AND AND1, a NOR gate NOR AND an inverter INV0, adopts a simplest five-tube comparison unit AND a simplest gate-level logic, ensures that the layout area is small, AND effectively improves the filling factor of a pixel unit; the measuring method of the invention integrates the voltage and the external input reference voltage VbiasThe obtained level change information is compared to control the integrating capacitor C2 to discharge zero clearing and twice integration, thereby realizing the obvious result of expanding the swing range of the integrated voltageEven under the power voltage of 1.8V, the total output range of the integral voltage can be increased to 2.2V, so that the fault-tolerant threshold of the lowest voltage difference and the noise voltage can be ensured even if higher-order digital quantization is carried out on the integral voltage, the time resolution and the measurement precision are effectively improved, and the measurement range is increased; meanwhile, the invention improves on the basis of a secondary folding type integral circuit, if more than three folding integrals are needed, the integral measuring unit is folded and increased, and the same logic process is carried out on the n integral enabling again on the basis of three times, namely the folding integrals of more than three times are realized.
Drawings
Fig. 1 is a block diagram of the overall structure of a time-amplitude conversion circuit;
FIG. 2 is a schematic diagram of a time-to-amplitude conversion circuit;
FIG. 3 is a timing diagram of the operation of the time-to-amplitude conversion circuit;
FIG. 4 is a schematic diagram of a triple folding integrator circuit based on a time-amplitude conversion circuit;
fig. 5 is a diagram of simulation results of the time-amplitude conversion circuit.
Detailed Description
For a better understanding of the contents of the present patent application, the technical solutions of the present invention will be further described below with reference to the accompanying drawings and specific examples.
As shown in fig. 1 to 5, a time-amplitude conversion circuit with a high dynamic range includes an integration timing module and a row selection readout module, wherein an input end of the integration timing module is connected to output ends of an integration signal generation logic and a feedback control logic, respectively, and an output end of the integration timing module is connected to input ends of the feedback control logic and the row selection readout module, respectively; the input signals of the integration timing module comprise an external reset signal Rst and an external input reference voltage VbiasAnd an Integral _ Signal input by the output end of the Integral Signal generating logic to the Integral timing module; input signals of the integrated signal generation logic comprise an external Photon avalanche signal Photon, an external Start signal Start and an external Stop signal Stop; the input signal of the row selection Read module is an external row selection Read signal Read, rowThe output terminal Out of the select read module is connected to an external output terminal.
The integrated signal generation logic comprises two RS flip-flops AND an AND gate AND1, wherein the two RS flip-flops are RSFF1 AND RSFF2 respectively; a1 setting end S of the RSFF1 is connected with an external Photon avalanche signal Photon, a 0 setting end R of the RSFF1 is connected with an external Stop signal Stop, AND an Integral Enable signal Integral _ Enable generated by an output end Q of the RSFF1 is connected with one input end of an AND gate 1; the 1 setting end S of the RSFF2 is connected with an external Start Signal Start, the 0 setting end R of the RSFF2 is connected with an external Stop Signal Stop, an integration interval Signal Integral _ Range generated at the Q end of the output end of the RSFF2 is connected with the other input end of the AND gate AND1, AND an Integral _ Signal output by the AND gate AND1 is connected with the integration timing module.
The integration timing module comprises two integration capacitors, three NMOS tubes, a first PMOS tube, an operational amplifier A1 and a constant current source Ibias(ii) a The two integrating capacitors are respectively C1 and C2, the three NMOS transistors are respectively MN0, MN1 and MN4, and the first PMOS transistor is MP 0; the gate of MN4 is connected with the integrated Signal Integral _ Signal generated at the output end of AND gate AND1 in the integrated Signal generation logic, the drain of MN4 is connected with a constant current source IbiasIs connected with the negative pole of the constant current source IbiasThe positive plates of C1 and C2 are connected to each other and to the source of MN4, the drain of MN0 and the non-inverting input of the operational amplifier a 1; the inverting input end of the operational amplifier A1 is connected with the Flag signal Flag generated by the output end of the operational amplifier A1 and is connected to the non-inverting input end of the operational amplifier A2 in the feedback control logic; the negative plate of C1 is connected to ground, the negative plate of C2 is connected with the drain of MN1 and the drain of MP 0; the gate of MN0 is connected to external reset signal Rst, the source of MN0 is connected to ground, the source of MN1 is connected to ground, the gate of MN1 and the gate of MP0 are connected together with feedback control logic, and the source of MP0 is connected to power supply voltage VDD.
The feedback control logic comprises an operational amplifier A2, two NMOS transistors, a second PMOS transistor, an AND gate AND0, a NOR gate NOR AND an inverter INV 0; the two NMOS transistors are respectively MN2 and MN3, and the second PMOS transistor is MP 1; wherein, the non-inverting input end of the operational amplifier A2 is connected with a Flag signal Flag generated by the output end of the operational amplifier A1 in the integral timing module; the inverting input end of the operational amplifier A2 is connectedExternally input reference voltage VbiasThe output end of the operational amplifier A2 is respectively connected with the drain of MN2, the gate of MN3 and the gate of MP 1; the gate of MN2 is connected to the external reset signal Rst, and the source of MN2 is connected to ground; the source of MP1 is connected to the supply voltage VDD, the drain of MP1 is connected to the drain of MN3 AND to one input of AND gate AND0, the drain of MN3 is connected to ground; the other input terminal of the AND gate AND0 is connected to the output terminal of the inverter INV0, the output terminal of the AND gate AND0 is connected to one input terminal of the NOR gate NOR, the other input terminal of the NOR gate NOR is connected to the external reset Signal Rst, the output terminal of the NOR gate NOR is connected to the input terminal of the inverter INV0, AND the quadratic integration enable Signal Second _ Signal generated by the NOR gate NOR is connected to the integration timing block.
The row selection reading module comprises a third PMOS tube, and the third PMOS tube comprises MP2 and MP 3; the gate of MP2 is connected to the positive plate of C1, the positive plate of C2, the drain of MN0, the source of MN4 and the non-inverting input of op-amp a1, the drain of MP2 is connected to ground, the source of MP2 is connected to the drain of MP3, the gate of MP3 is connected to the external row selection Read signal Read, and the source of MP3 is connected to the output Out.
An integrating capacitor C2, MOS transistors MP0 AND MN1 in the integrating timing module, AND an AND gate AND0, a NOR gate NOR AND an inverter INV0 in the feedback control logic form a double folding type integrating measurement circuit, when n times of folding integral measurement is carried out, n-2 groups of integral folding measurement units are added in the twice folding integral measurement circuit by the n times of folding integral measurement circuit, each integral folding measurement unit comprises an integral capacitor Cn, a PMOS pipe MP, an NMOS pipe MN, a Buffer, an OR gate Or, an AND gate AND, a NOR gate NOR AND an inverter INV, the output of the Or gate Or is connected with an AND gate AND in the feedback control logic, one input end of the Or gate Or is connected with the drains of a PMOS transistor MP1 AND an NMOS transistor MN3, the other input end of the Or gate Or is connected with the output end of a Buffer, AND the input end of the Buffer is connected with the output end of INV0 in the original twice-folding integral measuring circuit; in addition, the input end of the NOR gate NOR is connected with an external reset signal Rst, the output end of the NOR gate NOR is connected with the grids of a PMOS tube MP and an NMOS tube MN and is recorded as an n-time integral enabling signal n _ Enable, the positive plate of the integral capacitor C is connected with the positive plates of the integral capacitors C1 and C2, the negative plate of the NOR gate NOR is connected with the drain electrodes of the NMOS tube MN and the PMOS tube MP, the source electrode of the MN is grounded, and the source electrode of the MP is connected with a power supply VDD, wherein n is more than or equal to 3.
A measuring method of a time-amplitude conversion circuit with a high dynamic range is to measure on a double folding type integrating circuit, and comprises the following steps:
(1) starting a reset phase: when the system is powered on, resetting and clearing are carried Out on the system, an external reset signal Rst becomes high level, an NMOS (N-channel metal oxide semiconductor) tube MN0 is started, the voltages on positive plates of integrating capacitors C1 and C2 are cleared, the output end Out of the system is cleared, and the potential is pulled to the ground. Meanwhile, the NMOS transistor MN2 is also turned on, and the output of the operational amplifier a2 is also pulled low. In addition, the other input terminal of the NOR gate NOR is at a high level, and the Second integration Enable signal Second _ Enable at the output terminal thereof is at a low level, so that the NMOS transistor MN1 is turned off, the PMOS transistor MP0 is turned on, and the negative plate of the integrating capacitor C2 is at a high level, and the integrating capacitor C2 does not participate in the integration during the first stage of the integration. The Second integration Enable signal Second _ Enable is high level after passing through the inverter, and the integration voltage does not exceed the external input reference voltage V since the integration has not yet startedbiasThe operational amplifier a2 is at low level as a result of comparison by the comparator, AND becomes at high level through the inverter composed of the NMOS transistor MN3 AND the PMOS transistor MP1, AND this signal is kept at high level together with the inverted signal of the twice-integration Enable signal Second _ Enable through the action of the AND gate AND0, so long as the integrated voltage does not exceed the external input reference voltage V0biasAt this time, the twice integration Enable signal Second _ Enable is always kept at the low level. Subsequently, the Start signal for emitting laser light changes to high level, the system starts emitting laser light to detect the object, the integration Enable signal integration _ Enable is triggered by the Start signal Start to change to high level under the action of RSFF2, the circuit can Start integrating, and the system waits for photons to return.
(2) And (3) an integration timing stage: when the Photon signal Photon return is detected, the integration interval signal Integral _ Range is pulled high via RSFF1, and the signal is then summed withThe Integral Enable Signal Integral _ Enable is used as AND gate logic, the obtained Integral Signal Integral _ Signal turns on the NMOS tube MN4, and the constant current source IbiasThe first charging period of the integrating capacitor C1 is started, and the integrated voltage fails to reach the external input reference voltage VbiasThe output of the operational amplifier a2 is low, so the integrating capacitor C2 is not turned on and cannot participate in the first stage of integration. When the integrated voltage of the integrating capacitor C1 rises to the external input reference voltage VbiasWhen the output voltage of the NOR gate is high, the operational amplifier a2 as a comparator outputs high level, AND then becomes low level through the inverter composed of the NMO transistor MN3 AND the PMOS transistor MP1, AND at this time, the output of the AND gate AND0 becomes low level, so that the output of the NOR gate is high level regardless of the state of the other input terminal of the NOR gate. At this time, the NMOS transistor MN1 is turned on, the PMOS transistor MP0 is turned off, the negative plate of the integrating capacitor C2 is pulled to a low level, and the integrating capacitor C1 and the integrating capacitor C2 are connected in parallel to perform the second stage of integration until the external Stop signal Stop becomes a high level.
(3) A timing stopping stage: when the external Stop Signal Stop becomes high level, the integration Enable Signal Integral _ Enable at the Q end of the RSFF1 AND the integration interval Signal Integral _ Range at the output end of the RSFF2 are pulled to low level together, the integration Signal Integral _ Signal output by the integration Enable Signal Integral _ Enable AND the integration interval Signal Integral _ Range after passing through the AND gate 1 also becomes low level, the NMOS transistor MN4 is turned off, AND the constant current source IbiasThe supply of current to the integrating capacitors C1 and C2 is stopped, and integration is stopped, and the voltage values of the integrating capacitors C1 and C2 are kept constant. At this time, the circuit realizes folding integration, and the voltage swing is multiplied.
(4) A signal reading stage: when the external Stop signal Stop is ended, the external row selection Read signal Read changes from the initial high level to the low level, and at this time, the PMOS transistor MP3 is turned on, so as to transmit the voltage values of the integrating capacitors C1 and C2 to the output terminal Out. The invention releases the first section of integration voltage by using the comparator and the integrating capacitor C2, restarts the integration of a new section of integration to expand the swing range of the integration voltage, if the Second integration Enable signal Second _ Enable is high level, the first section of integration voltage can be judged to be the external input reference voltage VbiasThat isTotal voltage value is Vtotal=Vbias+VsecondAnd the magnitude of the second integrated voltage may be varied by adjusting the value of the integrating capacitor C2. If the Second integration Enable signal Second _ Enable is at a low level, it indicates that the integrated voltage fails to reach the external input reference voltage value, and then the voltage value is directly read. Therefore, when the time of the returned Photon signal Photon is detected to be early, the integration time is long, two-section integration is carried out, and the voltage swing is large; if the returned Photon signal Photon is detected late, the integration time is short, then a segment of integration is performed and the voltage swing is small. Therefore, the integral voltage swing is enlarged, and the measuring range and the time resolution are directly improved. The integral voltage value is in linear proportional relation with the photon flight time, so that the measuring time T can be calculated according to the output voltage valuemeasureWhile the time interval T of the external Start signal Start and the external Stop signal Stop is knowntotalAccording to the formula TOF = Ttotal-TmeasureThe photon time of flight TOF can be calculated.
The folding integration of more than three times is realized on the basis of the secondary folding integration, namely, the improvement is carried out on the basis of a secondary folding integration circuit, AND firstly, the control logics of an integration capacitor Cn, a PMOS (P-channel metal oxide semiconductor) tube MP, an NMOS (N-channel metal oxide semiconductor) tube MN, a Buffer, an OR gate Or, an AND gate AND, a NOR gate NOR AND an inverter INV are added; secondly, connecting a newly added three-time integration enabling signal n _ Enable output by AND-OR gate control logic to the gates of a PMOS tube MP and an NMOS tube MN for controlling three-time integration enabling, wherein the measuring method comprises the following steps of clearing a positive plate of C1 when a first-time integration voltage reaches an external input reference voltage Vbias, sending a second feedback signal to C2 to start secondary folding integration, invalidating the three-time integration enabling signal n _ Enable if the integration voltage does not exceed the external reference voltage Vbias when the second-time folding integration is started, not triggering the third-time folding integration, enabling the three-time integration enabling signal by the three-time control logic output by an operational amplifier A2 if the integration voltage exceeds the external reference voltage Vbias, and starting an integration capacitor Cn to be connected with the C1 and the C2 in parallel, namely entering the third-time folding integration; if more than three folding integrals are needed, the integral measurement unit is folded and increased, and the same logic process is carried out on the n integral enabling times on the basis of three times, namely, the folding integrals more than three times are realized.
Examples
The linear time-analog conversion circuit based on the charging timing of the integrating capacitors C1 and C2 is simulated based on a standard 0.18 mu m CMOS process, and the simulation parameters are as follows: the timing capacitor C takes 100fF, and the Photon signal Photon is set to have a waveform with a pulse width of 1 ns; based on the simulation parameters, the invention carries out the simulation with the duration of 2000ns, the integration time is 100ns, and obtains a simulation result chart as shown in figure 5. In the figure, the abscissa represents simulation time, and the ordinate represents the voltage value at the output terminal. Starting reset, wherein a reset signal Rst is changed into high level, the system carries out reset operation on the whole, and the timing capacitor C1 is reset to 10 mV; subsequently, the Start signal Start starts emitting laser light, and the system waits for the Photon signal Photon to return. When the Photon signal Photon is detected, the integrating capacitor C1 starts to be charged in a first section of integration, and the voltage starts to rise; then, when the integrated voltage reaches the operational amplifier A2 and the external input reference voltage VbiasWhen the comparison is equal, the negative plate of the integrating capacitor C2 is pulled to a low level through the feedback control logic, the integrating capacitor C2 clears the first section of integrating voltage, and then is connected with the integrating capacitor C1 in parallel to perform the second section of integration. Stopping integration when the external Stop signal Stop becomes a high level; at this time, it is completed to measure the time interval from the Photon signal Photon to the external Stop signal Stop. The waveform of the output end voltage in the mode shows good linear change along with simulation time. By design, the external input reference voltage Vbias is set to be 1V, the 100fF capacitor can realize integration timing in the range of 100ns, the voltage swing is 1V +1.2V =2.2V, 9bit quantization is carried out on the voltage swing, the voltage resolution can still reach 4.3mV, the time resolution reaches 195ps, and the DNL reaches
0.1LSB, compared with the traditional TAC and current integral TAC circuits, the circuit not only ensures lower power consumption and smaller layout area, but also expands the electricityThe voltage swing improves the time resolution and enlarges the detection distance. Further, if the folding is carried out for three times, the voltage swing amplitude can reach 3.2V, the voltage swing amplitude can be quantized by 10 bits, the time resolution is further improved to reach 98ps, the voltage resolution is also ensured to be 3.1mV, and the measurement precision is ensured.
In order to realize high-precision time-amplitude conversion, reduce clock feed-through effect, prolong retention time, greatly reduce layout area, reduce circuit power consumption and improve filling factor of pixel unit, the invention utilizes a scheme of analog timing detection Photon flight time, adopts a time-amplitude conversion circuit with high dynamic range, utilizes a folding voltage integration method, selects 100fF integrating capacitors C1 and C2, monitors charges on a positive plate, adopts a time interval from recording Photon signals Photon to arrival of external Stop signals Stop, namely when a system detects that Photon signals Photon are high level, carries out folding integration on integrating capacitors C1 and C2, when the external Stop signals Stop, the integrating capacitors C1 and C2 Stop integration, and finally calculates the Photon flight time according to the voltage size corresponding to the reset voltage size and the voltage size corresponding to the arrival time of the external Stop signals Stop, namely the round trip time of the detected Photon, when the time of the returned Photon signal Photon is detected to be early, the integration time is long, then two-section integration is carried out, and if the time of the returned Photon signal Photon is detected to be late, the integration time is short, then one-section integration is carried out.
The whole conversion process comprises four stages, namely a reset stage, a folding integration timing stage, an integration stopping stage and a signal reading stage, wherein the four stages are signals of one frame, 500 frames are continuously measured in the actual test process to obtain a group of voltage data, and then a group of time data is obtained. The invention adopts the idea of folding integration, utilizes the small-size MOS tube and the small-size capacitor, has simple control circuit structure, finally achieves the high dynamic range and high linearity integration, reduces clock feed-through, has the effect of longer retention time, greatly improves the time resolution and the measurement precision, simultaneously ensures the area of a circuit layout and the whole power consumption of the circuit, and can also effectively improve the filling factor of a pixel.
Claims (5)
1. A high dynamic range time-to-amplitude conversion circuit, characterized by: the integrated timing control circuit comprises an integrated timing module and a row selection reading module, wherein the input end of the integrated timing module is respectively connected with the output ends of an integrated signal generating logic and a feedback control logic, and the output end of the integrated timing module is respectively connected with the input ends of the feedback control logic and the row selection reading module; the input signals of the integration timing module comprise an external reset signal Rst and an external input reference voltage VbiasAnd the output end of the integration Signal generating logic is used for generating an Integral _ Signal which is input to the integration timing module; the input signals of the integration signal generating logic comprise an external Photon avalanche signal Photon, an external Start signal Start and an external Stop signal Stop; the input signal of the row selection reading module is an external row selection reading signal Read, and the output end Out of the row selection reading module is connected to an external output end; the integrated signal generating logic comprises two RS triggers AND an AND gate AND1, wherein the two RS triggers are RSFF1 AND RSFF2 respectively; the 1 setting end S of the RSFF1 is connected with an external Photon avalanche signal Photon, the 0 setting end R of the RSFF1 is connected with an external Stop signal Stop, AND an Integral Enable signal Integral _ Enable generated by the output end Q of the RSFF1 is connected with one input end of an AND gate 1; a1 setting end S of the RSFF2 is connected with an external Start Signal Start, a 0 setting end R of the RSFF2 is connected with an external Stop Signal Stop, an integration interval Signal Integral _ Range generated at an output end Q end of the RSFF2 is connected with the other input end of the AND gate AND1, AND an Integral _ Signal Signal output by the AND gate AND1 is connected with an integration timing module; the integration timing module comprises two integration capacitors, three NMOS tubes, a first PMOS tube, an operational amplifier A1 and a constant current source Ibias(ii) a The two integrating capacitors are respectively C1 and C2, the three NMOS transistors are respectively MN0, MN1 and MN4, and the first PMOS transistor is MP 0; the gate of MN4 is connected with the integrated Signal Integral _ Signal generated at the output end of the AND gate AND1 in the integrated Signal generation logic, the drain of MN4 is connected with the constant current source IbiasThe negative electrode of the constant current source I is connected with the negative electrode of the anodebiasThe positive electrodes of the C1 and the C2 are connected with each other and are connected with the source electrode of MN4, the drain electrode of MN0 and the non-inverting input end of the operational amplifier A1; the inverting input end of the operational amplifier A1 is connected with the Flag signal Flag generated by the output end of the operational amplifier A1 and is connected to the non-inverting input end of the operational amplifier A2 in the feedback control logic; the negative plate of the C1 is mutually connected to the ground, and the negative plate of the C2 is connected with the drain of MN1 and the drain of MP 0; the gate of the MN0 is connected to an external reset signal Rst, the source of MN0 is connected to ground, the source of MN1 is connected to ground, the gate of MN1 and the gate of MP0 are connected together with feedback control logic, and the source of MP0 is connected to a power supply voltage VDD; the feedback control logic comprises an operational amplifier A2, two NMOS transistors, a second PMOS transistor, an AND gate AND0, a NOR gate NOR AND an inverter INV 0; the two NMOS transistors are respectively MN2 and MN3, and the second PMOS transistor is MP 1; wherein, the non-inverting input end of the operational amplifier A2 is connected with a Flag signal Flag generated by the output end of the operational amplifier A1 in the integral timing module; the inverting input end of the operational amplifier A2 is connected with an external input reference voltage VbiasThe output end of the operational amplifier A2 is respectively connected with the drain of MN2, the gate of MN3 and the gate of MP 1; the gate of the MN2 is connected with an external reset signal Rst, and the source of the MN2 is connected with the ground; the source of the MP1 is connected with a power supply voltage VDD, the drain of the MP1 is connected with the drain of the MN3 AND is connected with one input end of an AND gate 0, AND the drain of the MN3 is connected with the ground; the other input end of the AND gate AND0 is connected with the output end of the inverter INV0, the output end of the AND gate AND0 is connected to one input end of the NOR gate NOR, the other input end of the NOR gate NOR is connected to the external reset Signal Rst, the output end of the NOR gate NOR is connected with the input end of the inverter INV0, AND the quadratic integration enable Signal Second _ Signal generated by the NOR gate NOR is connected with the integration timing module.
2. A high dynamic range time-to-amplitude conversion circuit as claimed in claim 1, wherein: the row selection readout module comprises a third PMOS (P-channel metal oxide semiconductor) transistor, and the third PMOS transistor comprises MP2 and MP 3; the gate of the MP2 is connected to the positive plate of the C1, the positive plate of the C2, the drain of the MN0, the source of the MN4 and the non-inverting input terminal of the operational amplifier a1, the drain of the MP2 is connected to ground, the source of the MP2 is connected to the drain of the MP3, the gate of the MP3 is connected to the external row selection Read signal Read, and the source of the MP3 is connected to the output terminal Out.
3. A high dynamic range time-to-amplitude conversion circuit as claimed in claim 1, wherein: an integrating capacitor C2, MOS transistors MP0 AND MN1 in the integration timing module, AND an AND gate AND0, a NOR gate NOR AND an inverter INV0 in feedback control logic form a double-folding type integration measuring circuit, when n times of folding integral measurement is carried out, n-2 groups of integral folding measurement units are added in the twice folding integral measurement circuit by the n times of folding integral measurement circuit, the integral folding measurement unit comprises an integral capacitor Cn, a PMOS tube MP, an NMOS tube MN, a Buffer, an OR gate Or, an AND gate AND, a NOR gate NOR AND an inverter INV, the output of the Or gate Or is connected with an AND gate AND in the feedback control logic, one input end of the Or gate Or is connected with the drains of a PMOS transistor MP1 AND an NMOS transistor MN3, the other input end of the Or gate Or is connected with the output end of a Buffer, AND the input end of the Buffer is connected with the output end of INV0 in the original twice-folding integral measuring circuit; in addition, the input end of the NOR gate NOR is connected with an external reset signal Rst, the output end of the NOR gate NOR is connected with the grids of the PMOS tube MP and the NMOS tube MN and is recorded as an n-time integral enabling signal n _ Enable, the positive plate of the integral capacitor Cn is connected with the positive plates of the integral capacitors C1 and C2, the negative plate of the NOR gate NOR is connected with the drain electrodes of the NMOS tube MN and the PMOS tube MP, the source electrode of the MN is grounded, and the source electrode of the MP is connected with a power supply voltage VDD, wherein n is more than or equal to 3.
4. A method of measuring a high dynamic range time-to-amplitude converter circuit as claimed in any one of claims 1 to 3, wherein the measurement is performed on a double folded integrator circuit, comprising the steps of:
1) starting reset stageSection (2): when a system is powered on, resetting and clearing are carried Out on the system, an external reset signal Rst becomes a high level, the voltages on the positive plates of C1 and C2 are cleared, and the output end Out of the system is cleared; the output end secondary integration Enable signal Second _ Enable of the NOR gate NOR is in low level, and the system only needs to integrate the voltage not to exceed the external input reference voltage V in the first period of integration processbiasThe Second integral Enable signal Second _ Enable is always kept at a low level; then, the Start signal for emitting laser changes to high level, the system starts emitting laser to detect an object, the integration Enable signal integration _ Enable is triggered by the Start signal Start to change to high level under the action of the RSFF2, the circuit starts integrating, and the system waits for photons returning;
2) and (3) an integration timing stage: when the Photon signal Photon returns to be detected, the constant current source IbiasThe first charging period of C1 begins, when the integrated voltage fails to reach the external input reference voltage VbiasThe output end of the operational amplifier A2 is at low level, so that C2 is not turned on and cannot participate in the integration of the first stage; when the integrated voltage of C1 rises to the external input reference voltage VbiasWhen the negative plate of the integrating capacitor C2 is pulled to a low level, the integrating capacitor C1 and the integrating capacitor C2 are connected in parallel and enter the integration of the second stage until the external Stop signal Stop becomes a high level;
3) a timing stopping stage: when the external Stop Signal Stop becomes high level, the output Integral Signal Integral _ Signal also becomes low level, the constant current source IbiasStopping supplying current to the integrating capacitors C1 and C2, stopping integrating, and keeping the voltage values on C1 and C2 unchanged; at the moment, the circuit realizes folding integration, and the voltage swing is multiplied;
4) a signal reading stage: when the external Stop signal Stop is ended, the external row selection Read signal Read is changed from the initial high level to the low level, and the voltage values on C1 and C2 are transmitted to the output end Out; the first section of integration voltage is released by using a comparator and C2, the integration of a new section is restarted to expand the swing range of the integration voltage, and if the Second integration Enable signal Second _ Enable is at high level, the first section of integration voltage is judgedThe voltage must be the external input reference voltage VbiasThen the total voltage value is Vtotal＝Vbias+VsecondWhile the magnitude of the second integrated voltage is varied by adjusting the value of C2; if the Second integration Enable signal Second _ Enable is at a low level, it indicates that the integrated voltage fails to reach the external input reference voltage value, and then the voltage value is directly read out; therefore, when the time of the returned Photon signal Photon is detected to be early, the integration time is long, two-section integration is carried out, and the voltage swing is large; if the returned Photon signal Photon is detected late, the integration time is short, then a section of integration is carried out, and the voltage swing is small; therefore, the integral voltage swing amplitude is enlarged, and the measurement range and the time resolution are directly improved; the integral voltage value is in linear proportional relation with the photon flight time, so that the measuring time T is calculated according to the output voltage valuemeasureWhile the time interval T of the external Start signal Start and the external Stop signal Stop is knowntotalAccording to the formula TOF ═ Ttotal-TmeasureThe photon time of flight TOF is calculated.
5. The method of claim 4, wherein the step of measuring comprises: the folding integration of more than three times is realized on the basis of the secondary folding integration, AND firstly, an integration capacitor Cn, a PMOS tube MP, an NMOS tube MN, a Buffer, an OR gate Or, an AND gate AND, an NOR gate NOR AND the control logic of a phase inverter INV are added; secondly, connecting a newly added three-time integration enabling signal n _ Enable output by AND-OR gate control logic to the gates of a PMOS (P-channel metal oxide semiconductor) tube MP and an NMOS (N-channel metal oxide semiconductor) tube MN for controlling three-time integration enabling, wherein the measuring method comprises the following steps of clearing a positive plate of C1 and sending a second feedback signal to C2 to start secondary folding integration when a first-time integration voltage reaches an external input reference voltage Vbias, invalidating the three-time integration enabling signal n _ Enable and not triggering the three-time folding integration if the integration voltage does not exceed the external reference voltage Vbias when the second-time folding integration is started, enabling the three-time integration enabling signal by the output of an operational amplifier A2 through the three-time control logic if the integration voltage exceeds the external reference voltage Vbias, and starting an integration capacitor C to be connected with the C1 and the C2 in parallel, namely entering the three-time folding integration; if more than three folding integrals are needed, the integral measurement unit is folded and increased, and the same logic process is carried out on the n integral enabling times on the basis of three times, namely, the folding integrals more than three times are realized.
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