CN110347031B - Pixel-level high-precision amplitude-time conversion circuit - Google Patents
Pixel-level high-precision amplitude-time conversion circuit Download PDFInfo
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- CN110347031B CN110347031B CN201910715901.1A CN201910715901A CN110347031B CN 110347031 B CN110347031 B CN 110347031B CN 201910715901 A CN201910715901 A CN 201910715901A CN 110347031 B CN110347031 B CN 110347031B
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
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Abstract
The invention discloses a pixel-level high-precision amplitude-time conversion circuit. The invention realizes a pixel-level high-precision amplitude-time conversion circuit, namely, an amplitude-time conversion circuit is integrated in each pixel in the read-out circuit, so that in one detection, all pixels can give out the intensity information of different echo signals. The amplitude-time conversion circuit is less limited by the clock frequency, so that the conversion precision is greatly improved, the voltage representing the strength of the echo signal is directly output in a digital format, the on-chip ADC is not required to carry out 2 times of quantization, and the difficulty of on-chip system design is reduced.
Description
Technical Field
The invention relates to a high-precision amplitude-time conversion circuit, and belongs to the technical field of circuits.
Background
The laser radar is an active detection technology capable of accurately and rapidly acquiring three-dimensional space information of the ground or the atmosphere, and can be used for ranging, angle measurement and the like, so that the laser radar is widely applied to the military and civil fields. Imaging lidars fall into a variety of modes of operation, such as scanning imaging with a unit or line detector and non-scanning imaging with an array detector. The scanning imaging working distance of the unit or line detector can be far, but the imaging speed can be limited to a certain extent; the imaging speed of the array detector is very high, the defects of large scanning size, heavy mass and poor reliability are overcome, the array detector plays a vital role in the relative navigation application of space targets with high real-time and volume requirements, and the array detector is currently becoming the focus and hot spot of many national researches.
The APD array has the characteristics of an all-solid structure, high quantum efficiency and the like, and can maintain a good signal-to-noise ratio under high gain. The laser three-dimensional imaging radar based on the APD array adopts laser to flood irradiate a target scene, and a three-dimensional image of the target can be obtained through one laser pulse. When the bias voltage of an APD is lower than its avalanche voltage, linear amplification of incident photoelectrons is achieved, and this operating state is referred to as a linear mode. In the linear mode, the higher the reverse voltage, the greater the gain. The linear APD amplifies the input photoelectrons with equal gain to form continuous current, and a laser continuous echo signal with time information and intensity information is obtained.
The linear APD detector of the large area array needs to be matched with a laser radar reading circuit of the large area array, but the current domestic laser radar reading circuit mainly comprises discrete devices or small area arrays, and has lower resolution and imaging rate. When the APD scale reaches 64×64 pixels or even larger, the laser radar reading circuit can only be realized by adopting a monolithic integration method. The large area array laser radar reading circuit chip is realized based on a standard CMOS process, so that the volume of a control system can be reduced, the weight can be reduced, the power consumption can be reduced, the anti-interference capability can be improved, the reliability can be improved, and the high-precision time resolution can be obtained while the high-frame frequency capturing of a target is realized.
The current large-area array three-dimensional imaging laser reading circuit is limited by the pixel area, and generally has only a timing and ranging function, namely, a high-precision time-digital conversion circuit is integrated in each pixel, so that only the time information of echo signals can be extracted. For extracting the echo signal intensity information, the circuit can only adopt one ADC shared by each column or a plurality of columns to solve the problem, the amplitude of the corresponding pixel is selected through a row/column control signal, and the ADC conversion is carried out on the amplitude information of each pixel one by one. This approach severely limits the operating frequency of the readout circuitry and thus the imaging speed of the linear APD detector.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and provides a pixel-level high-precision amplitude-time conversion circuit which can integrate an amplitude-time conversion circuit in each pixel in a read-out circuit, so that all pixels can give high-precision digital quantized intensity information of different echo signals in one detection.
In order to solve the technical problems, the invention adopts the following technical scheme:
the high-precision amplitude-time conversion circuit of the pixel level is characterized by comprising a plurality of D triggers, a latch unit, a 2-selection-1 multiplexer, a comparator, a gate circuit and a capacitor;
the inverting input end of the comparator is connected with the peak voltage-maintaining voltage, and the non-inverting input end of the comparator is connected with the detection port for charging and discharging the capacitor;
the output signals of the first D flip-flop and the comparator generate a Control signal Control through a gate circuit, and the Control signal Control is used for controlling other D flip-flops to be in a state of an amplitude conversion period or a data reading period;
the N D triggers are sequentially connected to form a trigger group, and the output end of the former trigger is connected with the input end of the latter trigger; during amplitude conversion: the trigger group serves as a counter; during data readout, the flip-flop group serves as a shift register;
the other D triggers are sequentially connected with the trigger group, and serve as a memory for storing the phase state of each clock signal during amplitude conversion; as a shift register during data readout;
the latch unit is used for latching the phase state of the clock signal and storing the latch signal into the rest D flip-flops;
the capacitor is controlled to charge or discharge by a Control Start signal Start, and the 2-to-1 multiplexer is controlled according to different generated Control signals to select and transmit corresponding one-way data according to the amplitude conversion period or the data reading period.
Further, a control Start signal Start is input to the gate of the MOS switch tube, and the constant current source I is controlled to charge or discharge the capacitor by controlling the MOS switch tube.
Further, when the control Start signal Start controls the gate voltage of the MOS switch tube to be high, the capacitor C discharges;
when the control Start signal Start controls the gate voltage of the MOS switch transistor to be low, the capacitor C is charged.
Further, the clock signal includes a reference clock signal and a plurality of clock signals formed by a plurality of delay units.
Further, the two-way data transmitted by the 2-out-of-1 multiplexer includes the data of the previous pixel and the output data of the four-input exclusive-or gate.
Further, the output signal of the comparator is subjected to NOT gate and then is subjected to AND gate with the output signal of the first D trigger to generate a Control signal Control.
Further, when the Control signal control=0, a data readout period is entered;
when the Control signal control=1, the amplitude conversion period is entered.
The invention has the beneficial effects that:
the invention realizes a pixel-level high-precision amplitude-time conversion circuit, namely, each pixel in the reading circuit is integrated with an amplitude-time conversion circuit, so that all pixels can give the intensity information of different echo signals; meanwhile, the amplitude-time conversion circuit is less limited by the clock frequency, and the conversion precision is greatly improved. The voltage representing the strength of the echo signal is directly output in a digital format, and 2 times of quantization is not needed by the ADC on the chip, so that the difficulty of system on chip design is reduced.
Drawings
Fig. 1 is a high-precision amplitude-to-time conversion circuit at the pixel level.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical aspects of the present invention, and are not intended to limit the scope of the present invention.
As shown in fig. 1, the conversion circuit in the present embodiment is composed of 16D flip-flops 1D to 16D, LATCH units LATCH1 to LATCH4, DELAY units DELAY1 to DELAY3, select 1 circuit 2, comparator com, gate circuit, MOS switch tube M0, constant current source I, capacitor C, and the like.
The circuit external signals are a control Start signal Start, a peak voltage VR, and a clock signal CLK.
The D flip-flops 1D to 16D are 16 identical falling edge triggered D flip-flops.
The D triggers 1D-12D form a trigger group, the D triggers are sequentially connected, the output end of the former trigger is connected with the input end of the latter trigger, and clocks of all the triggers are clock signals ck1. During amplitude conversion: the trigger group is used as a counter; during data reading, the flip-flop group is used as a shift register.
The clock signals of the three D flip-flops 13D to 15D are ck1. During amplitude conversion: the 13D-15D trigger is used as a memory; during the data reading period, 13D to 15D are used as shift registers.
In other embodiments, other numbers of D flip-flops may be used, depending primarily on the clock period and signal size.
The D flip-flop 16D generates a Control signal Control via a gate with the Control Start signal Start and the comparator com. The output signal of the comparator com is not-gated and then is coupled with the output signal phase of the D flip-flop 16D and then outputs the Control signal Control.
When the Control signal control=1, the circuit is in the amplitude conversion period;
when the Control signal Control is changed from 1 to 0, the circuit enters a data readout period.
The clock signal CLK can be latched by the LATCH unit LATCH1, and the phase state of the latched clock signal ck1 is stored in the D flip-flop 13D; the clock signal CLK2 is obtained by a delay unit DEALY1 and can be latched by a LATCH unit LATCH2, and the latched phase state signal ck2 is stored in the D flip-flop 14D; the clock signal CLK3 is obtained by a delay unit DEALY2 for the clock signal CLK 2; the clock signal CLK4 is obtained by a delay unit DEALY3 for the clock signal CLK3, and the clock signal CLK3 and the clock signal CLK4 are respectively latched by a LATCH unit LATCH3 and LATCH4, and the latched phase state signals are output and stored in the D flip-flop 15D through the exclusive nor gate.
The LATCH unit LATCH is used to LATCH states of the clock signals CLK, CLK2, CLK3, and CLK 4.
The Control signal control=1, 2 selects the end A of 1 circuit selection, the end A links with output of the four-input exclusive OR gate circuit; control signal control=0, 2 select 1 circuit selects the B terminal. The principle of the 2-selection-1 circuit, namely the two-way selection circuit, is that under the action of a control signal, data of an A end are transmitted or data of a B end are transmitted. The data at the end B is the data of the previous pixel, and the data at the end A is the output of the four-input exclusive-OR gate circuit.
The inverting input end of the comparator com is connected with the peak voltage maintaining voltage VR, and the non-inverting input end is a detection port VC for charging and discharging the capacitor C by the constant current source I.
The MOS switch tube M0 controls the capacitor C to charge or discharge, and when the control Start signal Start controls the grid voltage of the MOS switch tube M0 to be high, the capacitor C performs discharging operation; when the control Start signal Start controls the gate voltage of the MOS switch transistor M0 to be low, the capacitor C performs a charging operation.
Working principle:
the linear APD photosensitive chip converts the received laser narrow pulse echo signal into a current signal, and converts the current signal into a voltage signal with a certain amplitude through a transimpedance amplifier, wherein the voltage signal represents the intensity of the laser echo signal; the peak protection circuit keeps the voltage signal as the peak protection voltage VR. The amplitude-time conversion circuit of the invention carries out digital quantization processing on the peak voltage VR, and is convenient for integrating with the time information of the echo signal so as to realize rapid transmission.
First each D flip-flop clears 0. After the control Start signal Start is changed from high to low, the amplitude-time conversion according to the present invention starts.
The constant current source I charges the capacitor C, and the voltage of the detection port VC gradually increases from 0. Meanwhile, the trigger group is used as an integer counter, and the D triggers 13D-15D are used as accurate counters until the voltage VC of the detection port is greater than the peak voltage VR. The Control start signal Control is that the end B is selected by a 1-set 0, 2-select 1 circuit, under the effect of the falling edge of the next clock signal CLK, the peak voltage VR representing the echo intensity is sequentially read out from the D triggers 1D-15D at the falling edge of 15 clock signals ck1, so that the seamless connection of voltage conversion and data output of the pixels is realized.
When the voltage VC of the detection port is less than the peak voltage VR, the LATCH units LATCH1 to LATCH4 are not latched; when the voltage VC of the detection port is greater than the peak voltage VR, the LATCH units LATCH1 to LATCH4 are triggered to LATCH the phase states of the clock signals CLK, CLK2, CLK3 and CLK4 at that time, and the states are driven into the D flip-flops 13D to 15D for storage.
The counting accuracy of the accurate counter can be adjusted according to the DELAY unit DELAY. The number of the clock signals and the latch units are matched according to the number of the delay units.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and variations could be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and variations should also be regarded as being within the scope of the invention.
Claims (7)
1. The high-precision amplitude-time conversion circuit of the pixel level is characterized by comprising a plurality of D triggers, a latch unit, a 2-selection-1 multiplexer, a comparator, a gate circuit and a capacitor;
the inverting input end of the comparator is connected with the peak voltage-maintaining voltage, and the non-inverting input end of the comparator is connected with the detection port for charging and discharging the capacitor;
the output signals of the first D flip-flop and the comparator generate a Control signal Control through a gate circuit, and the Control signal Control is used for controlling other D flip-flops to be in a state of an amplitude conversion period or a data reading period;
the N D triggers are sequentially connected to form a trigger group, and the output end of the former trigger is connected with the input end of the latter trigger; during amplitude conversion: the trigger group serves as a counter; during data readout, the flip-flop group serves as a shift register;
the other D triggers are sequentially connected with the trigger group, and serve as a memory for storing the phase state of each clock signal during amplitude conversion; as a shift register during data readout;
the latch unit is used for latching the phase state of the clock signal and storing the latch signal into the rest D flip-flops;
the capacitor is controlled to charge or discharge by a Control Start signal Start, and the 2-to-1 multiplexer is controlled according to different generated Control signals to select and transmit corresponding one-way data according to the amplitude conversion period or the data reading period.
2. The high-precision amplitude-to-time conversion circuit of a pixel level according to claim 1, wherein a control Start signal Start is inputted to a gate of a MOS switch transistor, and a constant current source I is controlled to charge or discharge a capacitor by controlling the MOS switch transistor.
3. The high-precision amplitude-to-time conversion circuit at a pixel level according to claim 1, wherein the capacitor C discharges when the control Start signal Start controls the gate voltage of the MOS switch transistor to be high;
when the control Start signal Start controls the gate voltage of the MOS switch transistor to be low, the capacitor C is charged.
4. The high-precision amplitude-to-time conversion circuit of claim 1, wherein the clock signal comprises a reference clock signal and a plurality of clock signals delayed by a plurality of delay units.
5. A high precision amplitude to time conversion circuit at pixel level according to claim 1, wherein the two paths of data transmitted by the 2-to-1 multiplexer include the data of the previous pixel and the output data of the four-input exclusive nor gate.
6. The high-precision amplitude-to-time conversion circuit of claim 1, wherein the output signal of the comparator is not-gated and then is-phase-locked with the output signal of the first D flip-flop to generate the Control signal.
7. The high-precision amplitude-to-time conversion circuit at a pixel level according to claim 1, wherein when the Control signal control=0, a data readout period is entered;
when the Control signal control=1, the amplitude conversion period is entered.
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