CN106527098B - Low power consumption high-precision array type time-to-digital conversion circuit based on multiple VCO - Google Patents
Low power consumption high-precision array type time-to-digital conversion circuit based on multiple VCO Download PDFInfo
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- CN106527098B CN106527098B CN201610901004.6A CN201610901004A CN106527098B CN 106527098 B CN106527098 B CN 106527098B CN 201610901004 A CN201610901004 A CN 201610901004A CN 106527098 B CN106527098 B CN 106527098B
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
Abstract
The invention discloses a kind of low power consumption high-precision array type time-to-digital conversion circuit based on multiple VCO, chain is latched including freeboard section TDC circuits, high section TDC circuits, stage casing TDC circuits, low section of TDC circuit and DFF, it is that pixel exclusively enjoys circuit and is placed in pixel that wherein freeboard section TDC circuits, high section TDC circuits and DFF, which latch chain, and stage casing TDC circuits and low section of TDC circuit are globally shared circuit and are placed in outside pixel；The measurement of time interval is completed with freeboard section TDC circuits, high section TDC circuits, stage casing TDC circuits and low section of four partial order of TDC circuits, final to realize that time interval, which is converted to digital value, to be indicated.The low-power consumption of the present invention, the four-part form array type time-to-digital conversion circuit of high-precision, wide scope, can be used for array type detector timekeeping system, can significantly improve systemic resolution and reduce system power dissipation.
Description
Technical field
The present invention relates to a kind of low based on multiple VCO (Voltage Controlled Oscillator, voltage-controlled ring shake)
Power consumption high-precision array type time-to-digital conversion circuit is a kind of low power consumption high-precision can be applied to infrared sensing reading circuit
Four-part form array type time-to-digital conversion circuit, the circuit can effectively improve system under the premise of not influencing elemental area
Resolution ratio simultaneously reduces system power dissipation.
Background technology
According to TOF (Time of Flight) time measuring principle, infrared ROIC (Readout Integrated
Circuit) different pixels single photon transmitting-receiving interval time corresponds to different space lengths in reading circuit, by pel array
Relative distance between each pixel can show the profile of object under test, and the TDC circuits of high-precision, wide scope are then to visit
Examining system can obtain the guarantee of more precise information in farther distance, however under the application conditions of pel array, area and
The limitation of power consumption significantly increases the realization of TDC (Time-to-Digital Converter, time-to-digital converter) quantization performance
Technical difficulty, therefore array type TDC is more difficult to compared to general single pixel TDC in design.
For the application suitable for big array structure, current overwhelming majority TDC is using shared or local shared structure, the knot
TDC under structure is not instead of single pixel detection service, for multiple or even global pixel service.But due to general multistage
There is thinner error extraction and quantizing process in formula structure, it is necessary to and there are the response times, can not detect another time quantum simultaneously,
Therefore multisection type TDC is difficult to apply in big array, so the array type TDC for being suitable for big array at present is concentrated mainly on two sections
In formula structure.The restriction of TDC framework Gonna breakthrough range and precision applied to array detection timekeeping system, it is necessary to pursue multisection type
TDC structures.
Invention content
Goal of the invention：In order to alleviate the problem of range, precision and power consumption mutually restrict in the prior art to a certain extent,
The present invention provides a kind of novel low power consumption high-precision array type time-to-digital conversion circuits based on multiple VCO, in typical case
Two-part array type TDC technical foundation on, by introducing asynchronous subtraction count device structure and multiple respectively in high section and low section
Ring shakes the mode of structure so that under the premise of not influencing system pixel area and range, realizes raising and the work(of systemic resolution
The reduction of consumption.
Technical solution：To achieve the above object, the technical solution adopted by the present invention is：
A kind of low power consumption high-precision array type time-to-digital conversion circuit based on multiple VCO, including freeboard section TDC electricity
Road, high section TDC circuits, stage casing TDC circuits, low section of TDC circuit and DFF latch chain, wherein freeboard section TDC circuits, high section TDC electricity
It is that pixel exclusively enjoys circuit and is placed in pixel that road and DFF, which latch chain, and stage casing TDC circuits and low section of TDC circuit are globally shared electricity
It road and is placed in outside pixel；The measurement of time interval is by freeboard section TDC circuits, high section TDC circuits, stage casing TDC circuits and low section of TDC
The cooperation of four partial order of circuit is completed, final to realize that time interval, which is converted to digital value, to be indicated；
LFSR counter (the Linear Feedback Shifting of the freeboard section TDC circuit configuration double modes
Register, linear feedback shift register), the asynchronous subtraction count device of high section TDC circuit configuration double modes, stage casing TDC electricity
The road configuration voltage-controlled ring in stage casing shakes and double rotary single circuit, the low section of circuit TDC circuit configuration Dual-DLL and VCO, the circuits VCO by
X join with the out of phase low section of voltage-controlled ring vibration level of frequency, and each low section of voltage-controlled ring shakes by Y identical low section of delays
Unit cascaded to form, each low section of voltage-controlled ring cascades a low section of delay path before shaking, and i-th low section of delay path is by XiIt is a complete
Exactly the same delay unit cascades, X >=2, Y >=2；LFSR counter forms mixing after being serially connected in asynchronous subtraction count device
Counter, the shake high frequency clock signal H_CK of generation of the voltage-controlled ring in stage casing drives asynchronous subtraction count device, through asynchronous subtraction count device
The high frequency clock signal H_LFSR of frequency dividing synchronizes driving LFSR counter；
The quantized result of freeboard section TDC circuits is latched in LFSR counter by the pattern by switching LFSR counter,
The quantized result of high section TDC circuits is latched in asynchronous subtraction count device by the pattern by switching asynchronous subtraction count device, in
The quantized result of section TDC circuits and low section of TDC circuit latches chain by DFF and is latched；The LFSR counter asynchronous subtracts
Method counter and DFF latch chain and are mainly made of DFF, are reading freeboard section TDC circuits, high section TDC circuits, stage casing TDC electricity
When the quantized result of road and low section of TDC circuit, latch data by corresponding DFF (d type flip flop) connect after in binary form
The Serial output by turn from a high position to low level.
Time-to-digital conversion circuit proposed by the present invention passes through freeboard section TDC circuits, high section TDC circuits, stage casing TDC electricity
Road and low section of TDC circuit are completed to quantify to time interval respectively, can be under the premise of not influencing system range so that array TDC
Precision break through digital gate circuit minimum delay；Meanwhile asynchronous subtraction count device being added before the lowest order of LFSR counter,
The high frequency clock signal H_CK of generation of the voltage-controlled ring in stage casing being shaken divides and drives LFSR counter, to reduce LFSR counter
Synchronised clock frequency；Since LFSR counter and asynchronous subtraction count device are placed in pixel, freeboard section TDC circuits and height
The design of section TDC circuits can effectively reduce system power dissipation under the premise of not influencing system range.
Specifically, in the low section of TDC circuit, Dual-DLL is that (Delay Locked Loop postpone locking phase to two-stage DLL
Ring) structure, it is divided into main DLL and time DLL, is acted on by the close loop negative feedback of Dual-DLL and shake offer with work to low section of voltage-controlled ring
The highly stable voltage-controlled voltage of skill, supply voltage, temperature change；
Be provided in main DLL by N number of master delay it is unit cascaded made of main voltage controlled delay line, the input signal of main DLL is
External reference clock signal REF_CLK and Dual-DLL enabling signal START_DLL, output signal are voltage-controlled voltage Vctrf, will
External reference clock signal REF_CLK and N grades of master delay units carry out phase state phase demodulation, voltage-controlled voltage VctrfAutomatic adjustment
Main voltage controlled delay line keeps the phase state of external reference clock signal REF_CLK and N grades of master delay units identical；
Time voltage controlled delay line made of M delay cell cascades is provided in secondary DLL, the input signal of secondary DLL is
External reference clock signal REF_CLK and Dual-DLL enabling signal START_DLL, output signal are voltage-controlled voltage Vctrs, root
Go out n-th grade of master delay unit according to the delay selection of required secondary voltage controlled delay line, by n-th grade of master delay unit and M levels
Delay cell carries out phase state phase demodulation, voltage-controlled voltage VctrsAutomatic adjustment time voltage controlled delay line makes n-th grade of master delay unit
Phase state is identical as the phase state of M level delay cells.
Specifically, the voltage-controlled voltage VctrfIt is supplied to all low section of delays of all low sections voltage-controlled ring centers of percussion single simultaneously
Member, voltage-controlled voltage VctrsAll delay units being supplied to simultaneously in all low section of delay paths；It starts counting up signal EN and passes through X
Delay time different low section of delay path controls X low section of voltage-controlled rings and shake respectively starts starting of oscillation, and adjacent low section voltage-controlled
Ring shakes since starting of oscillation first phase is different thus generates delay time error, which passes through voltage-controlled voltage VctrsIt accurately controls, passes through
Adjust voltage-controlled voltage VctrsMeet certain sequential between so that adjacent low section of voltage-controlled ring is shaken, finally so that X low section of voltage-controlled rings shake
Between seamless linking cooperation.
In low section of TDC circuit, the split-phase number that single low section of voltage-controlled ring shakes is extended to 4Y by 2Y, entire low section of TDC electricity
The split-phase number on road reaches 4YX, solve traditional low section of TDC circuit can not take into account frequency of oscillation that single low section of voltage-controlled ring shakes and
Contradiction between split-phase number is shaken mutual cooperation by multiple low section of voltage-controlled rings, and systemic resolution can be made to break through digital gate circuit
Minimum delay, significantly improves systemic resolution.The low section of TDC circuit is direct when count stop signal STOP rising edges arrive
The quantized result of freeboard section TDC circuits, high section TDC circuits, stage casing TDC circuits and low section of TDC circuit is latched, need not be additional
Array application may be implemented in response time.
Specifically, the stage casing TDC circuits are designed based on time difference quantization principles, and use DLL-OSC frameworks, i.e., it is logical
The close loop negative feedback of the main DLL crossed in Dual-DLL is acted on shakes offer with technique, supply voltage, temperature change to the voltage-controlled ring in stage casing
Highly stable voltage-controlled voltage Vctrf；The voltage-controlled ring in stage casing shakes including poor made of being cascaded by N/2 differential delay cells
Divide delay line (noise that can effectively inhibit power supply and substrate using differential delay line) and Logic control module：When starting counting up
When signal EN rising edges arrive, differential delay line is opened by Logic control module；It arrives when starting counting up signal EN failing edges
When, differential delay line is turned off by Logic control module；The output end of each grade of differential delay cells connects a double turns of single electricity
The both-end difference output of differential delay cells is converted to Single-end output by double rotary single circuit, and is carried out to output signal by road
Shaping.TDC circuits in stage casing proposed by the present invention, when the multi-phase clock to be shaken using the voltage-controlled ring in stage casing is to one of high section TDC circuits
The clock period is uniformly differentiated, and the N/2 node state that the voltage-controlled ring in stage casing shakes will produce N group states per circulation primary, work as counting
When stop signal STOP rising edges arrive, the state that chain latches current N/2 node is latched by DFF, you can complete stage casing TDC
The quantization of circuit.
Specifically, the clock signal input terminal and data signal input of each DFF in asynchronous subtraction count device
One multiple selector of preceding each setting as Logic control module, believe by the control for starting counting up signal EN as multiple selector
Number：When it is high level to start counting up signal EN, the voltage-controlled ring in stage casing shakes provides high frequency clock signal H_ for asynchronous subtraction count device
CK, asynchronous subtraction count device are operated in count mode；When it is low level to start counting up signal EN, external low-frequency clock signal is
Asynchronous subtraction count device provides low-frequency clock signal, and asynchronous subtraction count device is operated in mode of serial transmission；It is counted by being multiplexed
And transmission structure, circuit area can be reduced, reduce system power dissipation.When count stop signal STOP arrives, LFSR counter
It is simultaneously stopped input high frequency clock signal with asynchronous subtraction count device, and current quantisation result is latched, signal to be started counting up
By the quantized result of latch successively Serial output when EN failing edges arrive.
Advantageous effect：Low power consumption high-precision array type time-to-digital conversion circuit provided by the invention based on multiple VCO,
Structure improvement and optimization design have been carried out on the basis of classical two-part TDC：It is added before the lowest order of LFSR counter different
Step subtraction count device divides the high frequency clock signal of input, it is ensured that system work(is reduced under the premise of system range
Consumption；Stage casing TDC circuits use DLL-OSC frameworks, and introduce the close loop negative feedback circuit of DLL, improve the property of stage casing TDC circuits
It can be horizontal；Low section of TDC circuit introduces multiple VCO structures, controls and using its relative phase, it can be achieved that split-second precision is differentiated.
Four sections of TDC circuits of the present invention can be latched by count stop signal STOP, not need addition extra latency or sound
The work of circuit is completed between seasonable, thus can meet the needs of array application.
Description of the drawings
Fig. 1 is the schematic diagram of the low power consumption high-precision array type time-to-digital conversion circuit of double VCO；
Fig. 2 is the circuit diagram for the mixing counter for constituting freeboard section TDC circuits and high section TDC circuits；
Fig. 3 is the circuit diagram of stage casing TDC circuits；
Fig. 4 is the circuit diagram of the differential delay cells in the TDC circuits of stage casing；
Fig. 5 is the circuit diagram of the double rotary single circuit in the TDC circuits of stage casing；
Fig. 6 is the sequence diagram of stage casing TDC circuits；
Fig. 7 is the circuit diagram of the Dual-DLL in low section of TDC circuit；
Fig. 8 is the circuit diagram that type TDC circuits are distinguished in high-precision phase position subdivision；
Fig. 9 is the sequence diagram of low section of TDC circuit.
Specific implementation mode
The present invention is further described below in conjunction with the accompanying drawings.
It is as shown in Figure 1 a kind of low power consumption high-precision array type time-to-digital conversion circuit based on double VCO, between the time
Every measurement quantified by freeboard section TDC circuits, high section TDC circuits, stage casing TDC circuits and low section of four partial segments of TDC circuits
At realization clocking capability.The freeboard section TDC circuits and high section TDC circuits that can be placed in pixel be respectively adopted LFSR counter and
Asynchronous subtraction count device is designed, and under the premise of the wide-range time needed for realizing is detected, passes through asynchronous subtraction count device
The synchronization high frequency clock signal of LFSR counter is divided, and then greatly reduces system power dissipation.
Valid period when starting counting up signal EN and being high level, external reference clock signal REF_CLK drivings are pressurized
Control voltage VctrfThe voltage-controlled ring in stage casing of control shakes work, generates and just aligns and with technique, the height of supply voltage, temperature change
Stable embedded clock HCK drives the integral multiple that high section TDC circuits complete the clock cycle to count, realizes the thick amount of time detection
Change function；Meanwhile the uniform clock of multiphase of stage casing TDC circuits quantifies the time margin of high section TDC circuits into row interpolation, completes
The score of clock cycle counts again.Low section of TDC circuit is that type TDC circuits are distinguished in high-precision phase position subdivision, is provided by Dual-DLL
Two different voltage-controlled voltage VctrfAnd Vctrs, start two due to starting counting up signal EN by two low section of delay paths
Low section of voltage-controlled ring shakes, and will produce two with the out of phase ring retard of frequency, is completed to stage casing TDC circuits by the double VCO structures
High frequency clock signal frequency multiplication, and then the time margin of stage casing TDC circuits is quantified into row interpolation using frequency multiplied clock signal.
In Digital Logical Circuits, it is equipped with the square-like clock signal that a switching frequency is f, then the work(of the Digital Logical Circuits
Consuming P is：
The power consumption P of Digital Logical Circuits is from gate circuit to load capacitance C under on off stateLThe electric energy of charge and discharge disappears
Consumption, therefore power consumption P and load capacitance CL, supply voltage VDDQuadratic sum switching frequency f it is directly proportional, it is contemplated that gate circuit it is quiet
Only non-switch state, insertion switch activity factor α (0≤α≤1) modify to power consumption.Broadly, Digital Logical Circuits can be with
Time-sharing work is at different switching frequency f, therefore α f can also be equivalent to the average frequency of switching of Digital Logical Circuits.
High section TDC circuits are mainly used for improving count upper-limit, and then expanded range；In view of structure is simplified and high frequency draws
With we expect using LFSR counter.Since LFSR counter is driven using synchronised clock, so when switching frequency increases
When, the power consumption of LFSR counter also can linearly increase therewith, cause the LFSR counter power consumption under high frequency very big；Since LFSR is counted
Number device is built in pixel, therefore to reduce the power consumption of pel array, need to reduce the clock frequency f of driving LFSR counterCLK。
Under the premise of not interfering with other performances, it is contemplated that asynchronous counter has a division function, therefore we are by high section TDC circuits
It is designed as the mode that LFSR counter is combined with asynchronous counter, to reduce power consumption；In addition, we have also carried out examining as follows
Consider：(1) asynchronous counter belongs to asynchronous clock control circuit, and per more one, clock will postpone the delay of a DFF, in order to
The measurement accuracy of system is not influenced, and the digit of asynchronous subtraction count device should not be too large；(2) between in order to realize counting and transmit
Pattern is converted, and is respectively arranged one before the clock signal input terminal and data signal input of each DFF in asynchronous counter
A multiple selector is as Logic control module；(3) due to the output end rising edge of asynchronous subtraction count device can be designed with
The even-multiple rising edge alignment of high frequency clock signal H_CK, is more convenient for counting, therefore asynchronous counter selects asynchronous subtraction count
Device；(4) in order to achieve the purpose that simplify area, asynchronous subtraction count device is built in pixel.Consider factor above, we
It is built-in mixing counter by high section TDC circuit designs, as shown in Fig. 2, wherein asynchronous subtraction count device is 2bit, LFSR meters
Number device is 7bit.
Middle section TDC circuits are using DLL-OSC frameworks, as shown in figure 3, shake including the voltage-controlled ring in stage casing turns single electricity with double
Road, the voltage-controlled ring in stage casing shake including differential delay line and Logic control module made of being cascaded by 4 differential delay cells, middle section
TDC circuits provide clock frequency for high section TDC circuits, and remainder error is carefully quantified by low section TDC circuits, plays and hold
On open under key effect.In order to realize the voltage-controlled ring in stage casing shake it is controllable and determine its original state, be added Logic control module into
Row control：When starting counting up the arrival of signal EN rising edges, differential delay line is opened by Logic control module, keeps its first phase true
It is fixed, initial phase errors are eliminated it is not necessary that additional circuit is added, facilitate counting；When starting counting up the arrival of signal EN failing edges, pass through
Logic control module turns off differential delay line, to reduce system power dissipation.But the introducing of Logic control module can make difference at different levels
There are serious mismatches for delay cell, reduce system linear degree；In order in ensureing section TDC circuit multi-phase clocks it is uniform
Property should readjust the delay of Logic control module and first order differential delay cells, make logic control to realize effective resolution
Molding block and the sum of the delay of first order differential delay cells are exactly equal to the sum of delay of other differential delay cells.It presses in stage casing
Main DLL control of the frequency that control ring shakes in by low section of TDC circuit, is generated by the close loop negative feedback effect of main DLL with technique, electricity
The highly stable voltage-controlled voltage V of source voltage, temperature changectrf, stablize the frequency shaken of the voltage-controlled ring in stage casing, reduce its by technique,
The influence of supply voltage, temperature change.
In order to reduce phase noise and extend output voltage swing, the voltage-controlled ring in stage casing, which shakes, uses differential delay line, single difference
Divide delay unit as shown in Figure 4；The differential delay cells are by one group of NMOS input to (MN1 and MN2), one group of PMOS positive feedback pair
(MP2 and MP3), one group of PMOS Diode are to (MP1 and MP4) and by control voltage VctrlThe MP5 of control is formed, wherein MP2
The oscillation that positive feedback maintains the voltage-controlled ring in stage casing to shake is constituted with MP3.Control voltage VctrlThe bias voltage of the MP5 of control props up to change
Road electric current, as control voltage VctrlBranch current becomes hour when increase, and the mutual conductance of MP1 and MP4 become smaller but equivalent resistance becomes larger, most
Eventually so that the output resistance and timeconstantτ of differential delay cells increase, i.e., so that the delay of difference delay unit becomes larger；Cause
This, voltage V is controlled by changectrlThe frequency that the voltage-controlled ring in the stage casing being made of the differential delay cells shakes can be controlled.In addition,
MP2 and MP3 is connected directly to supply voltage VDD, therefore output voltage swing is improved, carrier power is increased, and can also reduce and make an uproar
Acoustical power improves phase noise performance.
The key component of double rotary single circuit section TDC circuits as in turns the both-end difference output of differential delay cells
For Single-end output, circuit structure is as shown in Figure 5；It is double to turn single module mainly and have following effect or feature：(1) to differential delay list
The output of member carries out shaping；(2) node state of Single-end output latches convenient for data；(3) the clock frequency f of Single-end outputCLKIt can
To directly drive high section TDC circuits；(4) since middle section TDC circuits are using DLL-OSC frameworks, low section of TDC electricity
The master delay unit of main DLL in road is also required to use differential delay cells, and phase discriminator be to main voltage controlled delay line first
A and the last one signal carries out phase state phase demodulation, and it is Single-end output also to require main voltage controlled delay line at this time.When starting counting up
When signal EN is high level, backfeed loop conducting, the voltage-controlled ring in stage casing shakes unlatching, and the voltage-controlled ring in stage casing shakes sequential such as Fig. 6 of each node
It is shown.
In order to provide two stable delay times to low section of TDC circuit, using Dual-DLL structures, as shown in Figure 7；
Dual-DLL is two-stage DLL structures, is divided into main DLL and time DLL, the frequency of external reference clock signal REF_CLK is fREF.It is main
In DLL, pass through voltage-controlled voltage VctrfMain voltage controlled delay line is automatically adjusted, external reference clock signal REF_CLK and N grades of masters are made
The phase state of delay cell is identical, and the delay for obtaining every grade of master delay unit is t1=1/ (N × fREF)；In secondary DLL, pass through
Voltage-controlled voltage VctrsAutomatic adjustment time voltage controlled delay line, makes the phase state and M level delay cells of n-th grade of master delay unit
Phase state it is identical, obtain every level delay cell delay be t2=n/ (M × N × fREF).Pass through the closed loop of Dual-DLL
Negative feedback shakes offer with technique, the highly stable delay time of supply voltage, temperature change to low section of voltage-controlled ring；
As shown in figure 8, low section of TDC circuit shakes with two low section of delay road including the identical low section of voltage-controlled ring of two structures
Diameter, each low section of voltage-controlled ring shake including two-stage by same voltage-controlled voltage VctrfLow section of delay unit of control；Prolonged by two low section
When it is unit cascaded made of low section of voltage-controlled ring to shake be that low section of voltage-controlled ring of simple structure shakes, ring vibration frequency is relative to three or more
It is highest that low section of voltage-controlled ring, which shakes, made of low section of delay unit cascade.Signal EN is not started counting up by two delay times respectively not
Identical low section of delay path controls two low section of voltage-controlled rings and shake respectively starts starting of oscillation, and two low section of voltage-controlled rings shake due at the beginning of starting of oscillation
Mutually different thus generation delay time error, the delay time error pass through voltage-controlled voltage VctrsIt accurately controls, by adjusting voltage-controlled voltage Vctrs
Meet certain sequential between so that two low section of voltage-controlled rings is shaken, finally so that two low section of voltage-controlled rings shake between it is seamless linking match
It closes.The split-phase number that single low section of voltage-controlled ring shakes is extended to 8 by 4, and the split-phase number of entire low section of TDC circuit reaches 16, solves
Traditional low section of TDC circuit can not take into account single contradiction between the low section of voltage-controlled ring frequency of oscillation shaken and split-phase number.And in list
A low section of voltage-controlled ring center of percussion, if the series of low section of delay unit is more, although split-phase number increases, ring vibration frequency can also drop therewith
It is low, therefore resolution ratio is not improved actually.
The resolution ratio of array type TDC circuits that low section TDC circuits can make breaks through the minimum delay of digital gate circuit, significantly carries
High systemic resolution.It shakes to match the voltage-controlled ring in stage casing, needs that dummy circuits are added, but this can make entire array type TDC circuits
There are fixed 3ns delay time errors, i.e. dead time；Therefore it when carrying out timing using such array type TDC circuits, needs to add
The constant time lag of upper 3ns.This case is to needing the sequential of low section of TDC circuit and stage casing TDC circuits strictly to match, although at low section
Dummy circuits are introduced in TDC circuits, but still can not completely eliminate error, it is therefore desirable to calibration circuit be added, entire circuit is done
Further calibration.
Fig. 9 is the sequence diagram Q of low section of TDC circuitL4~QL1The phase state of composition changes between following 8 states：
1110→1100→1000→1001→0001→0011→0111→0110→1110
When count stop signal STOP rising edges arrive, each section of TDC circuit is simultaneously stopped work, and by each section of quantization
As a result be latching in corresponding DFF, wait start counting up signal EN failing edges arrive when, under the driving of low-frequency clock signal L_CK by
Bits Serial exports.
The above is only a preferred embodiment of the present invention, it should be pointed out that：For the ordinary skill people of the art
For member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also answered
It is considered as protection scope of the present invention.
Claims (6)
1. a kind of low power consumption high-precision array type time-to-digital conversion circuit based on multiple VCO, it is characterised in that：Including superelevation
Section TDC circuits, high section TDC circuits, stage casing TDC circuits, low section of TDC circuit and DFF latch chain, wherein freeboard section TDC circuits, height
It is that pixel exclusively enjoys circuit and is placed in pixel that section TDC circuits and DFF, which latch chain, and stage casing TDC circuits and low section of TDC circuit are the overall situation
It shares circuit and is placed in outside pixel；The measurement of time interval by freeboard section TDC circuits, high section TDC circuits, stage casing TDC circuits and
Low section of four partial order of TDC circuits cooperation is completed, final to realize that time interval, which is converted to digital value, to be indicated；
The LFSR counter of the freeboard section TDC circuit configuration double modes, the asynchronous subtraction meter of high section TDC circuit configuration double modes
Number device, the voltage-controlled ring in stage casing TDC circuit configurations stage casing shakes and double rotary single circuit, and low section of TDC circuit configurations Dual-DLL and VCO are returned
Road, the circuits VCO are joined by X with the out of phase low section of voltage-controlled ring vibration level of frequency, and each low section of voltage-controlled ring shakes complete by Y
Low section of exactly the same delay unit cascades, one low section of delay path of cascade before each low section of voltage-controlled ring shakes, i-th low section
Delay path is by XiA identical delay unit cascades, X >=2, Y >=2；LFSR counter is serially connected in asynchronous subtraction meter
Forming mixing counter after number device, the shake high frequency clock signal H_CK of generation of the voltage-controlled ring in stage casing drives asynchronous subtraction count device,
High frequency clock signal H_LFSR through asynchronous subtraction count device frequency dividing synchronizes driving LFSR counter；
The quantized result of freeboard section TDC circuits is latched in LFSR counter by the pattern by switching LFSR counter, is passed through
The quantized result of high section TDC circuits is latched in asynchronous subtraction count device by the pattern for switching asynchronous subtraction count device, stage casing TDC
The quantized result of circuit and low section of TDC circuit latches chain by DFF and is latched；The LFSR counter, asynchronous subtraction meter
Number devices and DFF latch chain be mainly made of DFF, read freeboard section TDC circuits, high section TDC circuits, stage casing TDC circuits and
When the quantized result of low section of TDC circuit, latch data by corresponding DFF connect after in binary form from a high position to low level by
Bits Serial exports；
In the low section of TDC circuit, Dual-DLL is two-stage DLL structures, is divided into main DLL and time DLL, passes through closing for Dual-DLL
Ring negative feedback shakes offer with technique, the highly stable voltage-controlled voltage of supply voltage, temperature change to low section of voltage-controlled ring.
2. the low power consumption high-precision array type time-to-digital conversion circuit according to claim 1 based on multiple VCO, special
Sign is：
Be provided in main DLL by N number of master delay it is unit cascaded made of main voltage controlled delay line, the input signal of main DLL is outside
Reference clock signal REF_CLK and Dual-DLL enabling signal START_DLL, output signal are voltage-controlled voltage Vctrf, will be external
Reference clock signal REF_CLK and N grades of master delay units carry out phase state phase demodulation, voltage-controlled voltage VctrfAutomatically adjust main pressure
Delay line is controlled, keeps the phase state of external reference clock signal REF_CLK and N grades of master delay units identical；
Time voltage controlled delay line made of M delay cell cascades is provided in secondary DLL, the input signal of secondary DLL is outside
Reference clock signal REF_CLK and Dual-DLL enabling signal START_DLL, output signal are voltage-controlled voltage Vctrs, according to institute
The delay selection of the secondary voltage controlled delay line needed goes out n-th grade of master delay unit, and n-th grade of master delay unit and M levels are postponed
Unit carries out phase state phase demodulation, voltage-controlled voltage VctrsAutomatic adjustment time voltage controlled delay line, makes the phase of n-th grade of master delay unit
State is identical as the phase state of M level delay cells.
3. the low power consumption high-precision array type time-to-digital conversion circuit according to claim 2 based on multiple VCO, special
Sign is：The voltage-controlled voltage VctrfIt is supplied to all low section of delay units of all low sections voltage-controlled ring centers of percussion, voltage-controlled electricity simultaneously
Press VctrsAll delay units being supplied to simultaneously in all low section of delay paths；When starting counting up signal EN and being postponed by X items
Between different low section of delay path control X low section of voltage-controlled rings respectively and shake and start starting of oscillation, adjacent low section of voltage-controlled ring shake due to
Starting of oscillation first phase it is different thus generate delay time error, which passes through voltage-controlled voltage VctrsIt accurately controls, it is voltage-controlled by adjusting
Voltage VctrsMeet certain sequential between so that adjacent low section of voltage-controlled ring is shaken, finally so that X low section of voltage-controlled rings are seamless between shaking
Gap linking cooperation.
4. the low power consumption high-precision array type time-to-digital conversion circuit according to claim 2 based on multiple VCO, special
Sign is：The stage casing TDC circuits are designed based on time difference quantization principles, and use DLL-OSC frameworks, that is, pass through Dual-
The close loop negative feedback of main DLL in DLL is acted on shakes offer with technique, the height of supply voltage, temperature change to the voltage-controlled ring in stage casing
Stable voltage-controlled voltage Vctrf；The voltage-controlled ring in stage casing shakes including differential delay made of being cascaded by N/2 differential delay cells
Line and Logic control module：When starting counting up the arrival of signal EN rising edges, differential delay line is opened by Logic control module；
When starting counting up the arrival of signal EN failing edges, differential delay line is turned off by Logic control module；Each grade of differential delay list
The output end of member connects a double rotary single circuit, is converted to the both-end difference output of differential delay cells by double rotary single circuit
Single-end output, and shaping is carried out to output signal.
5. the low power consumption high-precision array type time-to-digital conversion circuit according to claim 1 based on multiple VCO, special
Sign is：Respectively it is arranged before the clock signal input terminal and data signal input of each DFF in asynchronous subtraction count device
One multiple selector starts counting up control signals of the signal EN as multiple selector as Logic control module：Work as beginning
When count signal EN is high level, the voltage-controlled ring in stage casing shakes provides high frequency clock signal H_CK for asynchronous subtraction count device, asynchronous to subtract
Method counter works are in count mode；When it is low level to start counting up signal EN, external low-frequency clock signal is asynchronous subtraction
Counter provides low-frequency clock signal, and asynchronous subtraction count device is operated in mode of serial transmission.
6. the low power consumption high-precision array type time-to-digital conversion circuit according to claim 1 based on multiple VCO, special
Sign is：The low section of TDC circuit directly latches freeboard section TDC circuits, height when count stop signal STOP rising edges arrive
The quantized result of section TDC circuits, stage casing TDC circuits and low section of TDC circuit.
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| DE102019205731A1 (en) | 2019-04-18 | 2020-10-22 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Time-to-digital converter arrangement |
| CN113900368B (en) * | 2021-06-29 | 2022-12-06 | 西安电子科技大学芜湖研究院 | Time-to-digital converter applied to array laser radar |
| CN114237019B (en) * | 2021-12-29 | 2023-03-14 | 东南大学 | Event-driven time-to-digital converter applied to array system and conversion method |
| CN114967409B (en) * | 2022-03-28 | 2023-06-20 | 中山大学 | PVT variation-resistant high-precision time-to-digital converter and implementation method thereof |
| CN114935886B (en) * | 2022-04-21 | 2023-04-28 | 中国科学院上海微系统与信息技术研究所 | Two-stage superconducting time-to-digital converter and superconducting detector imaging system |
| CN117368698A (en) * | 2023-11-01 | 2024-01-09 | 上海合芯数字科技有限公司 | Chip circuit and testing method thereof |
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