CN109104190A - A kind of time-to-digital conversion circuit based on multiple repairing weld - Google Patents
A kind of time-to-digital conversion circuit based on multiple repairing weld Download PDFInfo
- Publication number
- CN109104190A CN109104190A CN201811142043.8A CN201811142043A CN109104190A CN 109104190 A CN109104190 A CN 109104190A CN 201811142043 A CN201811142043 A CN 201811142043A CN 109104190 A CN109104190 A CN 109104190A
- Authority
- CN
- China
- Prior art keywords
- signal
- ring
- counter
- register
- delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1071—Measuring or testing
-
- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
Abstract
The present invention provides a kind of time-to-digital conversion circuit based on multiple repairing weld, including enabled reset signal generation module, Start ring retard, Stop ring retard, signal detector, Start ring retard and Stop postpone inner loop counter, counter register, ROM memory, ROM memory register, data processor, data processor register.In Start, Stop signal input circuit, it respectively enters and is propagated in Start and Stop ring retard, linkage counter after the last one delay cell of each ring retard, output connection register, enabled reset signal generation module connects on counter, the output of each ring retard simultaneously connects 16 signal detectors respectively and carries out multiple repairing weld to signal, sampled result inputs in ROM memory, output connection register, input of the result as data processor of counter register, ROM memory register, output connection register.Technical solution of the present invention solves the problems, such as that existing time-to-digit converter measurement accuracy is low, realizes higher measurement accuracy.
Description
Technical field
Fields of the present invention are IC design, and in particular to a kind of time-to-digital converter electricity based on multiple repairing weld
Road.
Background technique
Time as scientific research test and various engineering technology in the fundamental physical quantity that refers to, research always by
Concern.The measurement of especially high-precision time interval, in some laser rangings, Physical Experiment, satellite monitoring, biologic medical etc.
Field plays increasingly important role.Time-to-digital conversion circuit is a basic means at time of measuring interval, with one
Continuous simulated time amount amount is converted discrete digital quantity by fixed quantified precision, and then realizes the survey to interval of time
Amount, the quantified precision of the time-to-digit converter of different structure are different, i.e., resolution ratio is different.
In recent years, the research of time-to-digital conversion circuit is received and greatly paid close attention to, including some flash-types, vernier prolong
The structures such as slow chain, differential delay type and two-step, but the time-to-digit converter of these structures from the method for measurement with
And from the point of view of specific circuit structure aspect, respective disadvantage is suffered from, for example flash-type digit time converter needs to abandon it
Measurement range, to obtain higher resolution ratio, while its dynamic range and area and power consumption are also deposited in contradictory relation；Vernier prolongs
Slow chain, in special process bottom sheet mismatch can indirect resolution limiting size, meanwhile, the length of dynamic range and delay chain
There is the relationship to condition each other between degree；Two-step time-to-digit converter needs to be exchanged for biggish area and power consumption higher
Resolution ratio.
Summary of the invention
By the research to the prior art, there are aiming at the problem that, the present invention provides a kind of time based on multiple repairing weld
Digital conversion circuit.
Technical solution of the present invention:
The present invention provides a kind of time-to-digital conversion circuits based on multiple repairing weld, comprising:
Counter for generating counter enable signal and counter reset signal enables and reset signal generation module；
Whether the signal for detecting each delay cell output in ring retard has the signal detector changed from 1 to 0；
The Start signal delay inner loop counter of circle number is propagated and for recording for recording Start signal in prolonging ring
Stop signal propagates the Stop signal delay inner loop counter of circle number in ring；
The ROM memory specifically numbered for delay cell in ring retard where output signal；
Data register for memory counter count value, ROM memory output valve and data processor numerical value；
For handling the data processor of the binary numeral of ROM memory output；
Start signal delay ring, stop signal delay ring；
In Start signal and Stop signal input circuit, respectively enters the Start signal delay ring and Stop signal prolongs
Slow ring is propagated, and connects a counter respectively after the last one delay cell of each ring retard, the counter it is defeated
Outlet linkage counter register, the enabled reset signal generation module are connected on counter, the output of each ring retard
End is separately connected 16 signal detectors for the multiple repairing weld to signal, and sampled result inputs in ROM memory, the ROM
The output end of memory connects ROM memory register, saves ROM memory output as a result, counter register, ROM storage
Input of the result of device register as data processor, the output end connection data processor deposit of the data processor
Device saves processing result.
Further, the Start signal delay ring and Stop signal delay ring are two completely identical in structure delays
Ring is made of 16 delay cells and an alternative multiple selector respectively.
Further, the counter includes propagating the Start signal of circle number for recording Start signal in prolonging ring to prolong
Slow inner loop counter and propagates the Stop signal delay inner loop counter for enclosing number for recording Stop signal in ring.
Further, the data register includes arriving for storing Start signal delay inner loop counter in Stop signal
Come when count value, Start signal delay inner loop counter Stop signal arrival after count value, Stop signal delay ring count
The counter register of the count value of device, the ROM memory register of value for storing two ROM memories and for depositing
Store up the data processor register of the binary numeral of data processor output.
Further, the data processor includes one for handling the binary numeral of ROM memory output, is subtracted each other
The subtracter exported afterwards with true form.
Further, the delay cell in the ring retard is to postpone identical phase inverter.
The present invention provides a kind of implementation methods of time-to-digital conversion circuit based on multiple repairing weld, including following step
It is rapid:
The input of step 1:Start signal, Start signal are propagated in ring retard；
Step 2:Start signal delay inner loop counter counts the propagation circle number of Start signal in Start ring retard
Number；
The input of step 3:Stop signal, while Star signal t delay inner loop counter exports current count value, and continues to count
Number, Stop signal are propagated in ring retard identical with Start signal；
Step 4:Stop signal delay inner loop counter counts the propagation circle number of signal in Stop ring retard；
Step 5: while signal input, using propagating period τ small sampling clock in ring retard than signal to letter
Number position is detected, and is numbered by the delay cell of ROM memory output signal position, while Start signal delay
Inner loop counter and Stop signal delay inner loop counter export current count value respectively；
Step 6: by comparing the position of ring retard where Start signal and Stop signal, being obtained by data processing
Time interval between Start signal and Stop signal.
The present invention also provides a kind of design method of time-to-digital conversion circuit based on multiple repairing weld,
A kind of time-to-digital conversion circuit based on multiple repairing weld is realized, using method of designing integrated circuit to the knot
Structure is designed, comprising the following steps:
Step S1: it by the logical relation of each signal in analysis time digital quantizer, is required, is carried out according to specific implementation
The division of functions of modules；
Step S2: the circuit diagram of each functional module of Cadence software design is utilized；
Step S3: the graphical diagram of each functional module in generation step S2, and simulating, verifying is carried out, judge the correct of design
Property；By simulating, verifying, the circuit diagram of each functional module is optimized, is optimal the performance of each section circuit, it will be each
Functional module forms complete circuit structure；Integrated circuit is emulated using Cadence software, and it is whole to carry out Time-Series analysis detection
Whether body circuit can be realized purpose function；
Step S4: after functional simulation is verified, modules are formed into complete time-to-digital conversion circuit structure.
Compared with the prior art, a kind of time-to-digital conversion circuit based on multiple repairing weld of the invention, with other structures
Time-to-digital conversion circuit compare, have the advantage that
1, provided by the invention a kind of based on the time-to-digital conversion circuit based on multiple repairing weld, it is complete using two structures
16 delay cells with same delay, i.e. phase inverter are respectively adopted in identical ring retard, and structure is simple, and each
Phase inverter is added after the output of odd numbered delay units, so that signal, in ring retard in communication process, the signal detected is always
It is to maintain identical variation pattern, convenient for detection；
2, circuit provided by the invention the data that ROM memory exports directly are handled using subtracter obtain as a result,
The sequencing for not needing the position for distinguishing that Start signal and Stop signal detect in ring, simplifies circuit structure；
3, circuit provided by the invention in measurement using be less than the sampling clock of ring retard period tau to Start signal and
Stop signal is detected, and has higher measurement accuracy.
To sum up, it applies the technical scheme of the present invention and utilizes two identical ring retards and adopting less than ring retard period tau
Sample clock realizes the high-acruracy survey to time interval.Therefore, technical solution of the present invention solves measurement in the prior art
The problems such as precision is not high.
The present invention can be widely popularized in fields such as high-acruracy surveys based on the above reasons.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to do simply to introduce, it should be apparent that, the accompanying drawings in the following description is this hair
Bright some embodiments for those of ordinary skill in the art without any creative labor, can be with
It obtains other drawings based on these drawings.
Fig. 1 is circuit structure diagram of the present invention.
Fig. 2 is circuit implementing method flow chart of the present invention.
Fig. 3 is circuit design method flow chart of the present invention.
Fig. 4 is measured signal time interval schematic diagram of the present invention.
Fig. 5 is the time interval measurement timing diagram in the embodiment of the present invention.
Fig. 6 is the measurement overall structure diagram of the time-to-digital conversion circuit in the embodiment of the present invention.
Fig. 7 is the Start ring structure schematic diagram in the embodiment of the present invention.
Fig. 8 is the Stop ring structure schematic diagram in the embodiment of the present invention.
Fig. 9 is the signal detector structural schematic diagram in the embodiment of the present invention.
Figure 10 is the ROM memory structural schematic diagram in the embodiment of the present invention.
Figure 11 is the ROM memory register architecture schematic diagram in the embodiment of the present invention.
Figure 12 is the tetrad counter structure schematic diagram in the embodiment of the present invention.
Figure 13 is that the counter in the embodiment of the present invention enables and reset signal generation module structural schematic diagram.
Figure 14 is the counter register structural schematic diagram in the embodiment of the present invention.
Figure 15 is the data processor architecture schematic diagram in the embodiment of the present invention.
Figure 16 is the data processor register architecture schematic diagram in the embodiment of the present invention.
Figure 17 is the signal detector graphical diagram in the embodiment of the present invention.
Figure 18 is the ROM memory graphical diagram in the embodiment of the present invention.
Figure 19 is the ROM memory register graphical diagram in the embodiment of the present invention.
Figure 20 is the counter graphical diagram in the embodiment of the present invention.
Figure 21 is that the counter in the embodiment of the present invention enables and reset signal generation module structure symbol figure.
Figure 22 is the counter register graphical diagram in the embodiment of the present invention.
Figure 23 is the data processor graphical diagram in the embodiment of the present invention.
Figure 24 is the data processor register graphical diagram in the embodiment of the present invention.
Specific embodiment
In order to enable those skilled in the art to better understand the solution of the present invention, below in conjunction in the embodiment of the present invention
Attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only
The embodiment of a part of the invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill people
The model that the present invention protects all should belong in member's every other embodiment obtained without making creative work
It encloses.
It elaborates with reference to the accompanying drawing to specific implementation of the invention.
As shown in Figure 1, the present invention provides a kind of time-to-digital conversion circuits based on multiple repairing weld, comprising: for giving birth to
At the counter of counter enable signal and counter reset signal is enabled and reset signal generation module；
Whether the signal for detecting each delay cell output in ring retard has the signal detection module changed from 1 to 0；
The Start signal delay inner loop counter of circle number is propagated and for recording for recording Start signal in prolonging ring
Stop signal propagates the Stop signal delay inner loop counter of circle number in ring；
The ROM memory specifically numbered for delay cell in ring retard where output signal；
Data register for storing data, including storage Start signal delay inner loop counter is respectively used in Stop
Count value, the Stop signal delay of count value, Start signal delay inner loop counter after the arrival of Stop signal when signal arrives
Six data of the binary numeral of the count value of inner loop counter, the value of two ROM memories and data processor output are posted
Storage；
For handle ROM memory output binary numeral data processor, including one for handle ROM storage
The binary numeral of device output, the subtracter exported after subtracting each other with true form；
Start signal delay ring, stop signal delay ring are two completely identical in structure ring retards, respectively by 16
A delay cell and an alternative multiple selector are constituted, and the delay cell in ring retard is to postpone identical phase inverter.
In Start signal and Stop signal input circuit, respectively enters the Start signal delay ring and Stop signal prolongs
Slow ring is propagated, and connects a counter respectively after the last one delay cell of each ring retard, the counter it is defeated
Outlet linkage counter register, the enabled reset signal generation module are connected on counter, the output of each ring retard
End is separately connected 16 signal detectors for the multiple repairing weld to signal, and sampled result inputs in ROM memory, the ROM
The output end of memory connects ROM memory register, saves ROM memory output as a result, counter register, ROM storage
Input of the result of device register as data processor, the output end connection data processor deposit of the data processor
Device saves processing result.
The working principle of time-to-digital conversion circuit based on multiple repairing weld: using two identical ring retards and prolong
The delay of each delay cell in slow ring is identical, is indicated, is quantified to the simulated time amount of input, with discrete number with tp
The form of amount exports, and quantified precision depends on the difference between the period of sampling clock and the period of ring retard.Using described
The time interval between two measured signal failing edges is measured based on the time-to-digital conversion circuit of multiple repairing weld, if
Two successive input signals are respectively Start signal and Stop signal, and Start signal prolongs in advance in Stop signal into Start
Slow ring is propagated, while Start signal delay inner loop counter counts the circle number that Start signal is propagated in ring,
Stop signal arrive after, propagated in Stop ring retard, at the same Stop signal delay inner loop counter to signal in Start ring retard
In propagation circle number counted, Start signal delay inner loop counter export current propagation circle number；Postponing using than signal
The sampling clock that a period small fixed value τ is propagated in ring carries out multiple repairing weld to signal, obtains in the ring retard where signal
Position, measurement accuracy is τ at this time, when Start signal and Stop signal are propagated in ring retard, detect respectively signal have by
When 1 to 0 variation, export the current value of two counters respectively, and obtain the number of the delay cell where signal, by with
The propagation of upper counter output encloses number and calculates the time between Start signals and Stop signal by how many groups of delay cells
Interval.
A kind of rudimentary algorithm of the time-to-digital conversion circuit based on multiple repairing weld is as follows:
If the delay for being used for transmission each delay cell of the ring retard of two signals is tp, since ring retard is by one two
A multiple selector and 16 delay cells is selected to constitute, if Start signal is propagated in ring retard when Stop signal arrives
Number is enclosed as X circle, i.e. the count value that Start postpones inner loop counter is X, and counter O reset at this time starts to count again, works as Start
Signal and Stop signal are propagated in ring retard, and when detecting that signal has the variation by 1 to 0 respectively, Start signal is in ring retard
The circle number of middle propagation is N, i.e. the value that Start postpones inner loop counter is N, and the circle number that Stop signal is propagated in ring retard is M, i.e.,
The value that Stop postpones inner loop counter is M, detects that the position of Start signal is the P delay cell, detects Stop signal
Position is the Q delay cell, then the calculation formula of time interval T are as follows:
T=X16tp+ (P-Q) tp+ (N-M) τ
As shown in Fig. 2, the present invention provides a kind of implementation method of time-to-digital conversion circuit based on multiple repairing weld, packet
Include following steps:
The input of step 1:Start signal, Start signal are propagated in ring retard；
Step 2:Start signal delay inner loop counter counts the propagation circle number of Start signal in Start ring retard
Number；
The input of step 3:Stop signal, while Star signal t delay inner loop counter exports current count value, and continues to count
Number, Stop signal are propagated in ring retard identical with Start signal；
Step 4:Stop signal delay inner loop counter counts the propagation circle number of signal in Stop ring retard；
Step 5: while signal input, using propagating period τ small sampling clock in ring retard than signal to letter
Number position is detected, and is exported by ROM memory, while Start signal delay inner loop counter and Stop signal delay ring meter
Number device exports current count value respectively；
Step 6: by comparing the position of ring retard where Start signal and Stop signal, being obtained by data processing
Time interval between Start signal and Stop signal.
As shown in figure 3, the present invention also provides a kind of design method of time-to-digital conversion circuit based on multiple repairing weld,
The following steps are included:
Step S1: it by the logical relation of each signal in analysis time digital quantizer, is required, is carried out according to specific implementation
The division of functions of modules；The present embodiment is designed the present embodiment base to time-to-digit converter using method of designing integrated circuit
In multiple repairing weld time-to-digital conversion circuit overall structure as shown in Figure 1, including: that counter is enabled according to function division module
With reset signal generation module, Start ring retard, Stop ring retard, signal detector, Start ring retard and Stop ring retard
Counter, ROM memory, ROM memory register, counter register, data processor, data processor register.
Step S2: the circuit diagram of each functional module of Cadence software design is utilized；When in order to measure shown in Fig. 4
Between be spaced, the present embodiment based on multiple repairing weld measurement method measures it using higher precision, when time interval measurement
Sequence schematic diagram as shown in figure 5, using be less than ring retard period tau sampling clock Start signal and Stop signal are sampled,
Realize high-acruracy survey.
As shown in fig. 6, the whole measurement structure of time-to-digital conversion circuit of the present embodiment based on multiple repairing weld, when annular
Between digital quantizer kernel by a Start ring retard, a Stop ring retard, 16 phase inverters, 32 signal detectors
Composition, Start ring retard and Stop ring retard are made of 16 same delay units and an alternative Port Multiplier selector.
Start signal is propagated in Start ring retard after entering ring retard, and Stop signal enters in ring retard to be passed in Stop ring retard
It broadcasts, if the delay units delay of ring retard is tp, the output of every group of delay cell accesses signal detector, wherein odd numbered delay list
The output of member accesses signal detector after connecing a phase inverter, detects signal by 1 to 0 variation.As shown in Figure 7,8, this implementation
Two ring retards of example are made of an alternative Port Multiplier and 16 identical phase inverters, and each delay cell all has instead
Phase function.As shown in figure 9, Start ring retard, Stop ring retard signal detector in the present embodiment, for detecting signal by 1
To 0 variation.Include 32 identical signal detectors in the present embodiment, shares 32 in Start ring retard and Stop ring retard
Delay cell is organized, is all connected with a signal detector behind the output of every group of delay cell；As shown in Figure 10, in the present embodiment
ROM memory, using the storage array of 16 × 4 storage units, for storing from 0000 to 1111 totally 16 binary numerals,
16 phase inverters are respectively indicated, whether there is or not pipes to carry out table with the unit for each basic unit of storage storage content in storage array
Show.WL0-WL15 is as input, and wherein certain wordline is selected exports high level, so that being connected to all NMOS in this wordline
Pipe conducting, the bit line that the drain electrode of these pipes is connect are low level, make data output end output information 0.As shown in figure 11, this reality
Applying the ROM memory in example is four bit registers, the tetrad numerical value that the bit line for storing ROM memory exports；Such as
Shown in Figure 12, be the present embodiment in Start ring retard and Stop ring retard tetrad counter module, counter by
Four d type flip flop compositions, trigger has 0 and 1 two states, therefore can indicate a binary system with a trigger
Number, 4 triggers, which are stringed together, indicates 4 bits, including propagating circle number in prolonging ring for recording Start signal
Start signal delay inner loop counter and the Stop signal delay inner loop counter that circle number is propagated for recording Stop signal in ring；
As shown in figure 13, enable signal and reset signal that reset signal generation module generates counter respectively are enabled；As shown in figure 14,
Start ring retard, Stop ring retard counter register in the present embodiment are all four bit registers, are respectively used to storage Stop
Start delay inner loop counter and Stop delay after the current value of Start delay inner loop counter, Stop signal arrive when signal arrives
The value of inner loop counter；As shown in figure 15, the data processing structure of the present embodiment, including two tetrad adders, by 4
The carry input of a full adder cascade, each processing one, least significant bit is usually arranged as 0, and the carry of each full adder is defeated
It is connected to the carry input of high one-bit full addres out.According to the subtraction of the complement of two's two's complement, two tetrads subtract each other can
To be realized by full adder.ROM [0] _ reg_Q four in Figure 15 is normally to input, and ROM [1] _ reg_Q four is
Input is negated, low level inputs to 1 to high-order carry C, to realize ROM [0] _ reg_Q-ROM [1] _ reg_Q subtraction,
The result of output is handled using second adder, is finally exported in the form of true form；As shown in figure 16, the present embodiment
Data processor register be five bit registers, for storing data processor output tetrad numerical value and one into
Place value.
Step S3: the graphical diagram of each functional module in generation step S2, and simulating, verifying is carried out, judge the correct of design
Property；By simulating, verifying, the circuit diagram of each functional module is optimized, is optimal the performance of each section circuit, it will be each
Functional module forms complete circuit structure；Integrated circuit is emulated using Cadence software, and it is whole to carry out Time-Series analysis detection
Whether body circuit can be realized purpose function；As shown in figure 17, the signal detector graphical diagram of the present embodiment, signal detector
Pin is Start [i], Stop [i], CLK, Start_edge [i], Stop_edge [i], and i value is 0 to 15.Start[i],
Stop [i] is respectively the output signal that Start signal and Stop signal propagate each phase inverter in ring retard, and CLK is sampling
Clock Start_edge [i], Stop_edge [i] are output signal, enable the defeated of reset signal generation module as counter
Enter；As shown in figure 18, the ROM memory graphical diagram of the present embodiment, the pin of ROM memory are WL [i], ROM_BL0, ROM_
BL1, ROM_BL2, ROM_BL3, i value are 0 to 15.WL [i] is the wordline of ROM memory, ROM_BL0, ROM_BL1, ROM_
BL2, ROM_BL3 are the bit line of ROM memory；As shown in figure 19, the ROM memory register graphical diagram in the present embodiment, ROM
The pin of memory register be en_ROM [j] _ reg, CLK, ROM [J] _ BL [0:3], rst_ROM [j] _ reg, ROM [j] _
Reg_Q [0:3], j value are 0 and 1.ROM [j] _ reg_Q [0:3] is output signal；As shown in figure 20, the meter in the present embodiment
Number device graphical diagram, the pin of counter are en_cnt [j], CLK, rst_cnt [j], cnt [j] _ Q [0:3], and j value is 0 and 1.
Cnt [j] _ Q [0:3] is output signal；As shown in figure 21, the counter in the present embodiment enables and reset signal generation module knot
Structure graphical diagram, pin are Start_edge [i], Stop_edge [i], en_cnt [j], rst_cnt [j], and j value is 0 and 1.Letter
Output Start_edge [i], the Stop_edge [i] of number detector are the input letter that counter enables reset signal generation module
Number, en_cnt [j] and rst_cnt [j] they are two enable signals and reset signal for postponing inner loop counter；As shown in figure 22, originally
Counter register graphical diagram in embodiment, the pin of counter register is en_cnt [j] _ reg [k], cnt [j] _ Q [0:
3], CLK, rst_cnt [j] _ reg [k], cnt [j] _ reg_Q [0:3], j take 0 and 1, and k takes 0 and 1.cnt[j]_reg_Q[0:3]
For the output of register；As shown in figure 23, the data processor graphical diagram in the present embodiment, the pin of data processor are ROM
[0]_reg_Q[0:3],ROM[1]_reg_Q[0:3],v,sub_Q[0:3].V and sub_Q [0:3] is output；As shown in figure 24,
Data processor register graphical diagram in the present embodiment, the pin of data processor register are en_sub_reg, v, sub_Q
[0:3],CLK,rst_sub_rsg,V,sub_reg_Q[0:3].V, sub_reg_Q [0:3] is output signal.To each of design
A module is emulated, and by the correctness of waveform checking function, sees whether waveform meets design requirement, is wanted if being unsatisfactory for function
It asks, design need to be remodified and emulated again, until functions meet your requirements.
Step S4: after functional simulation is verified, modules are formed into complete time-to-digital conversion circuit structure.
The serial number of the above embodiments of the invention is only for description, does not represent the advantages or disadvantages of the embodiments.
In the above embodiment of the invention, it all emphasizes particularly on different fields to the description of each embodiment, does not have in some embodiment
The part of detailed description, reference can be made to the related descriptions of other embodiments.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.The serial number of the above embodiments of the invention is only for description, does not represent the advantages or disadvantages of the embodiments.
Claims (8)
1. a kind of time-to-digital conversion circuit based on multiple repairing weld characterized by comprising
Counter for generating counter enable signal and counter reset signal enables and reset signal generation module；
Whether the signal for detecting each delay cell output in ring retard has the signal detector changed from 1 to 0；
The ROM memory specifically numbered for delay cell in ring retard where output signal；
Data register for memory counter count value, ROM memory output valve and data processor numerical value；
For handling the data processor of the binary numeral of ROM memory output；
Start signal delay ring, Stop signal delay ring；
And counter；
In Start signal and Stop signal input circuit, the Start signal delay ring and Stop signal delay ring are respectively enterd
It is propagated, connects a counter, the output end of the counter respectively after the last one delay cell of each ring retard
Linkage counter register, the enabled reset signal generation module are connected on counter, the output end point of each ring retard
Not Lian Jie 16 signal detectors be used for the multiple repairing weld to signal, sampled result inputs in ROM memory, the ROM storage
The output end of device connects ROM memory register, saves ROM memory output as a result, counter register, ROM memory are posted
The output end of input of the result of storage as data processor, the data processor connects data processor register, protects
Deposit processing result.
2. a kind of time-to-digital conversion circuit based on multiple repairing weld according to claim 1, it is characterised in that: described
Start signal delay ring and Stop signal delay ring are two completely identical in structure ring retards, single by 16 delays respectively
Member and an alternative multiple selector are constituted.
3. a kind of time-to-digital conversion circuit based on multiple repairing weld according to claim 1, it is characterised in that: the meter
Number devices include propagates for recording Start signal in prolonging ring to enclose the Start signal delay inner loop counter of number and for recording
Stop signal propagates the Stop signal delay inner loop counter of circle number in ring.
4. a kind of time-to-digital conversion circuit based on multiple repairing weld according to claim 1 is realized, it is characterised in that: institute
State data register include for store Start signal delay inner loop counter Stop signal arrive when count value, Start letter
Number delay inner loop counter Stop signal arrival after count value, the count value of Stop signal delay inner loop counter counter post
Storage, the ROM memory register of value for storing two ROM memories and the two of processor output for storing data
The data processor register of binary value.
5. a kind of time-to-digital conversion circuit based on multiple repairing weld according to claim 1, it is characterised in that: the number
It include one for handling the binary numeral of ROM memory output according to processor, the subtraction exported after subtracting each other with true form
Device.
6. a kind of time-to-digital conversion circuit based on multiple repairing weld according to claim 2, it is characterised in that: described to prolong
Delay cell in slow ring is to postpone identical phase inverter.
7. a kind of implementation method of the time-to-digital conversion circuit based on multiple repairing weld, which comprises the following steps:
The input of step 1:Start signal, Start signal are propagated in ring retard；
Step 2:Start signal delay inner loop counter counts the propagation circle number of Start signal in Start ring retard；
The input of step 3:Stop signal, while Start signal delay inner loop counter exports current count value, and continues to count,
Stop signal is propagated in ring retard identical with Start signal；
Step 4:Stop signal delay inner loop counter counts the propagation circle number of signal in Stop ring retard；
Step 5: while signal input, using propagating period τ small sampling clock in ring retard than signal to signal position
It sets and is detected, numbered by the delay cell of ROM memory output signal position, while Start signal delay ring meter
Number device and Stop signal delay inner loop counter export current count value respectively；
Step 6: by comparing the position of ring retard where Start signal and Stop signal, obtaining Start letter by data processing
Time interval number between Stop signal.
8. a kind of design method of the time-to-digital conversion circuit based on multiple repairing weld, which comprises the following steps:
Step S1: it by the logical relation of each signal in analysis time digital quantizer, is required according to specific implementation, carries out module
The division of function；
Step S2: the circuit diagram of each functional module of Cadence software design is utilized；
Step S3: the graphical diagram of each functional module in generation step S2, and simulating, verifying is carried out, judge the correctness of design；
By simulating, verifying, the circuit diagram of each functional module is optimized, is optimal the performance of each section circuit, by each function
Module forms complete circuit structure；Integrated circuit is emulated using Cadence software, and carries out the whole electricity of Time-Series analysis detection
Whether road can be realized purpose function；
Step S4: after functional simulation is verified, modules are formed into complete time-to-digital conversion circuit structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811142043.8A CN109104190B (en) | 2018-09-28 | 2018-09-28 | Time-to-digital conversion circuit based on multiple sampling |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811142043.8A CN109104190B (en) | 2018-09-28 | 2018-09-28 | Time-to-digital conversion circuit based on multiple sampling |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109104190A true CN109104190A (en) | 2018-12-28 |
| CN109104190B CN109104190B (en) | 2021-06-15 |
Family
ID=64867730
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811142043.8A Active CN109104190B (en) | 2018-09-28 | 2018-09-28 | Time-to-digital conversion circuit based on multiple sampling |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109104190B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110088696A (en) * | 2019-03-18 | 2019-08-02 | 深圳市汇顶科技股份有限公司 | Time-to-digital conversion circuit and correlation technique |
| CN111123687A (en) * | 2020-01-16 | 2020-05-08 | 中国科学技术大学 | Time measuring method and system |
| CN112035400A (en) * | 2020-09-08 | 2020-12-04 | 福州大学 | Stride access data stream detection circuit and method based on FPGA |
| CN112489713A (en) * | 2020-11-26 | 2021-03-12 | 昕原半导体(上海)有限公司 | Counting method, counting circuit, counting device, counting equipment and computer storage medium |
| CN115453849A (en) * | 2022-08-25 | 2022-12-09 | 灿芯半导体(天津)有限公司 | High-precision capturing circuit and capturing method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090027088A1 (en) * | 2007-07-23 | 2009-01-29 | Samsung Electronics Co., Ltd. | High resolution time detecting apparatus using interpolation and time detecting method using the same |
| CN101738947A (en) * | 2009-11-09 | 2010-06-16 | 杭州精久科技有限公司 | High-speed high-precision process parameter online calibration tester |
| CN204272278U (en) * | 2014-12-23 | 2015-04-15 | 天津大学 | For the high speed row level ADC based on TDC of imageing sensor |
| CN106338908A (en) * | 2016-08-31 | 2017-01-18 | 中国科学院上海高等研究院 | Edge extraction circuit and time-digital converter |
| CN108170018A (en) * | 2017-12-28 | 2018-06-15 | 东北大学 | It is a kind of to gate ring-like time-to-digit converter and time digital conversion method |
| US10193561B2 (en) * | 2015-12-23 | 2019-01-29 | Cirrus Logic, Inc. | Phase locked loops |
-
2018
- 2018-09-28 CN CN201811142043.8A patent/CN109104190B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090027088A1 (en) * | 2007-07-23 | 2009-01-29 | Samsung Electronics Co., Ltd. | High resolution time detecting apparatus using interpolation and time detecting method using the same |
| CN101738947A (en) * | 2009-11-09 | 2010-06-16 | 杭州精久科技有限公司 | High-speed high-precision process parameter online calibration tester |
| CN204272278U (en) * | 2014-12-23 | 2015-04-15 | 天津大学 | For the high speed row level ADC based on TDC of imageing sensor |
| US10193561B2 (en) * | 2015-12-23 | 2019-01-29 | Cirrus Logic, Inc. | Phase locked loops |
| CN106338908A (en) * | 2016-08-31 | 2017-01-18 | 中国科学院上海高等研究院 | Edge extraction circuit and time-digital converter |
| CN108170018A (en) * | 2017-12-28 | 2018-06-15 | 东北大学 | It is a kind of to gate ring-like time-to-digit converter and time digital conversion method |
Non-Patent Citations (3)
| Title |
|---|
| ZHANG,JIE等: "An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA", 《IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT》 * |
| 王巍等: "一种基于维纳延迟环的高线性度TDC", 《微电子学》 * |
| 金硕巍等: "过电平采样模数转换器误差源的建模", 《东北大学学报(自然科学版)》 * |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110088696A (en) * | 2019-03-18 | 2019-08-02 | 深圳市汇顶科技股份有限公司 | Time-to-digital conversion circuit and correlation technique |
| WO2020186414A1 (en) * | 2019-03-18 | 2020-09-24 | 深圳市汇顶科技股份有限公司 | Time-to-digital conversion circuit and related method |
| JP2021520756A (en) * | 2019-03-18 | 2021-08-19 | シェンチェン グーディックス テクノロジー カンパニー リミテッド | Time-to-digital conversion circuit and related methods |
| EP3828647A4 (en) * | 2019-03-18 | 2021-11-10 | Shenzhen Goodix Technology Co., Ltd. | Time-to-digital conversion circuit and related method |
| US11309899B2 (en) | 2019-03-18 | 2022-04-19 | Shenzhen GOODIX Technology Co., Ltd. | Time-to-digital conversion circuit and method of the same |
| JP7137636B2 (en) | 2019-03-18 | 2022-09-14 | シェンチェン グディックス テクノロジー カンパニー，リミテッド | Time-to-digital conversion circuit and related methods |
| CN111123687A (en) * | 2020-01-16 | 2020-05-08 | 中国科学技术大学 | Time measuring method and system |
| CN112035400A (en) * | 2020-09-08 | 2020-12-04 | 福州大学 | Stride access data stream detection circuit and method based on FPGA |
| CN112489713A (en) * | 2020-11-26 | 2021-03-12 | 昕原半导体(上海)有限公司 | Counting method, counting circuit, counting device, counting equipment and computer storage medium |
| CN115453849A (en) * | 2022-08-25 | 2022-12-09 | 灿芯半导体(天津)有限公司 | High-precision capturing circuit and capturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109104190B (en) | 2021-06-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109104190A (en) | A kind of time-to-digital conversion circuit based on multiple repairing weld | |
| CN106385256B (en) | With the multi-channel parallel acquisition system for storing synchronous identification function | |
| CN101231632A (en) | Method for processing floating-point FFT by FPGA | |
| CN108170018B (en) | It is a kind of to gate ring-like time-to-digit converter and time digital conversion method | |
| CN106681126B (en) | A kind of time-to-digit converter and its apparatus and method that calibrate for error | |
| KR940001693A (en) | Devices for measuring skew timing errors | |
| CN104077492B (en) | A kind of sampled data interpolating method based on FPGA | |
| CN116362168B (en) | Modeling method and device for GPGPU offline clock and storage medium | |
| CN104679719A (en) | Floating point calculation method based on FPGA | |
| CN113157637A (en) | High-capacity reconfigurable FFT operation IP core based on FPGA | |
| CN109445365A (en) | A kind of screening test method of the embedded multiplier of FPGA | |
| CN106527099B (en) | A kind of time-to-digit converter and its time measuring circuit and method | |
| Mohamed et al. | Concurrent driving method with fast scan rate for large mutual capacitance touch screens | |
| CN100538393C (en) | A kind of sample delay phase shift digital correlator and phase compensating method | |
| CN102129419B (en) | Based on the processor of fast fourier transform | |
| RU200621U1 (en) | Signal duration and time interval meter | |
| KR101334111B1 (en) | Quad-data rate controller and realization method thereof | |
| US11055240B2 (en) | Data processing method and device for performing a convolution operation | |
| US8008935B1 (en) | Tester and a method for testing an integrated circuit | |
| CN111123687B (en) | Time measuring method and system | |
| CN114152790B (en) | Ammeter box with error self-checking function and checking method thereof | |
| CN109726354A (en) | A kind of parallel cross-correlation calculation method towards mass data | |
| RU2242013C2 (en) | Correlation analyzer of frequency properties of linear system | |
| SU942037A1 (en) | Correlation meter of probability type | |
| CN210807222U (en) | Signal processing device with small edge slope and signal counting equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |