CN101881984B - Reference signal generator and method and system thereof - Google Patents
Reference signal generator and method and system thereof Download PDFInfo
- Publication number
- CN101881984B CN101881984B CN 201010168683 CN201010168683A CN101881984B CN 101881984 B CN101881984 B CN 101881984B CN 201010168683 CN201010168683 CN 201010168683 CN 201010168683 A CN201010168683 A CN 201010168683A CN 101881984 B CN101881984 B CN 101881984B
- Authority
- CN
- China
- Prior art keywords
- node
- voltage
- transistor
- circuit
- follows
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The invention provides a reference signal generator and a method and a system thereof for generating a differential reference voltage between a first output end and a second output end of the reference signal generator, comprising a first following transistor and a second following transistor; the first following transistor comprises a first controlling node, a first following node and a first voltage source node; the second following transistor comprises a second controlling node, a second following node and a second voltage source node; a first voltage reduced circuit is electrically connected between a circuit power node and a second power supplying node; the first voltage reduced circuit is bias arranged so that the voltage between the power node and the second voltage source node is more than the voltage between the circuit power node and the first voltage source node, and the voltage between the circuit power node and the second voltage source node is more than the voltage between the power node and the first controlling node, thereby obtaining a high PSRR value.
Description
Technical field
The present invention relates to semiconductor circuit, relate in particular to a kind of reference signal generator and method and system thereof.
Background technology
In analog to digital converter (analog-to-digital converters, ADC) was used, reference signal produces and gives birth to device was important parts.Reference signal generator be used for producing and the constant reference voltage that keeps an expectation to realize accurate analog to digital conversion as ADC.In analog to digital converter, by using the switching capacity load technology, provide a reference voltage that is complementary with change-over circuit (or reference voltage).
Because the generation of reference voltage is directly involved in analog to digital conversion and calculates, the mistake that occurs during reference voltage produces will cause the ADC reduction of performance, as signal to noise ratio (S/N ratio) (Signal-to-Noise Ratio, SNR) or etc. significance bit (Equivalent Number ofBits, ENOB).The main error of mis-behave comes from the switching process not exclusively to be set up and power supply noise.Relatively poor power supply ripple suppresses further to aggravate the impact of power supply ripple noise.
Power supply ripple rejection ratio (high power supply rejectionratio, PSRR) for improving reference signal generator can adopt large decoupling capacitance, and/or adopts the sheet external capacitive body in reference signal generator.However, this type of technology may be brought increases the expensive of chip area, and the chip pin that some are additional increases circuit complexity, and increases the outer device of sheet.
Summary of the invention
The embodiment of the invention provides a kind of reference signal generator and method and system thereof.
The embodiment of the invention provides a kind of reference signal generator to be used for producing the difference reference voltage between its first output terminal and the second output terminal on the one hand, and comprising: first follows transistor and second follows transistor; First follows transistor comprises: the first control node, first follow node and the first voltage source node with the first output terminal is electrically connected; Second follows transistor comprises: the second control node, second follow node and second voltage source node with the second output terminal is electrically connected; The first voltage drop circuit is electrically connected between circuit power node and the second source supply node; The biasing of the first voltage drop circuit arranges, so that the voltage between circuit power node and the second voltage source node is greater than the voltage between circuit power node and the first voltage source node; Also so that the voltage between circuit power node and the second voltage source node greater than circuit power node and the first control the voltage between the node.
The embodiment of the invention provides a kind of system for generation of the difference reference voltage on the other hand, be used for to be used for producing the difference reference voltage between its first output terminal and the second output terminal, to comprise: amplifier, first is followed transistor, second and is followed transistor, the 3rd and follow transistor, the 4th and follow transistor and biasing circuit; Amplifier has the first forward outgoing route, the second forward outgoing route, the first feed back input path and the second feed back input path;
First follows transistor comprises: be electrically connected at control node and the node of following that is electrically connected at the first feed back input path in the first forward outgoing route;
Second follows transistor comprises: be electrically connected at control node and the node of following that is electrically connected at the second feed back input path in the second forward outgoing route;
The 3rd follows transistor comprises: be electrically connected at control node and the node of following that is electrically connected at the first output terminal in the first forward outgoing route;
The 4th follows transistor comprises: be electrically connected at control node and the node of following that is electrically connected at the second output terminal in the second forward outgoing route; With
Biasing circuit is used for providing and is in first and follows transistor and the second bias voltage of following between the transistor voltage source node; And provide and be in the 3rd and follow transistor and the 4th and follow corresponding bias voltage between the transistor voltage source node.
The embodiment of the invention provides a kind of method for generation of the difference reference voltage on the other hand, may further comprise the steps:
Follow second of node and transistor seconds from first of the first transistor and follow driver output difference reference voltage between the node; Wherein, this difference reference voltage is used for so that come from reference voltage that first of the first transistor follows node less than the second reference voltage of following node that comes from transistor seconds;
The reference voltage voltage drop of the voltage source node that comes from transistor seconds is provided; With
Regulate this voltage drop so that the signal energy of transmitting the output from reference power source to the difference reference voltage is minimum.
The embodiment of the invention is by said method and device, and then obtained high PSRR value and/or at the broadband low output impedance that the output reference voltage node obtains, and then reduced the error of difference reference signal generator.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is a kind of difference reference signal of embodiment of the invention generator circuit diagram;
Fig. 2 is the difference reference signal synoptic diagram that the embodiment of the invention produces;
Fig. 3 is another difference reference signal generator circuit diagram of the embodiment of the invention;
Fig. 4 is another difference reference signal generator circuit diagram of the embodiment of the invention;
Fig. 5 is the bias voltage circuit in the embodiment of the invention circuit;
Fig. 6 is the grid bias circuit in the embodiment of the invention circuit; With
Fig. 7 is a kind of system schematic of using difference reference signal generator of the embodiment of the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
A kind of differential reference voltage that the embodiment of the invention provides can be followed transistor (source follower transistors) by the source in the open loop circuit and be produced, and this source is followed triode and setovered by replica bias circuit (replica-bias circuit).Should multiple biasing circuit comprise a differential amplifier and be arranged at copy source in the feedback control loop and follow transistor pair.A kind of voltage drop circuit (A voltage drop circuit) is connected to be electrically connected at least one source and to follow on the transistor.Optionally, reference voltage generator is integrated and integrated circuit (IC) chip inner (in the sheet) and then can quick-setting, and has higher power supply ripple rejection ratio (high power supply rejection ratio, PSRR).
As shown in Figure 1, the embodiment of the invention provides a kind of differential voltage circuit 100.The output terminal of this differential voltage circuit 100 is V
RefpAnd V
RefnDifference output.Differential voltage circuit 100 comprises that differential amplifier 102, open loop source follow transistor M
p, M
n, multiple monotectic pipe M
Pr, M
Nr, and voltage drop circuit 112,114.Transistor M
Pr,, M
Nr, M
pAnd M
nSetovered by current source 104,106,108 and 110 respectively.
Transistor M is followed in the open loop source
p, M
n, and multiple monotectic pipe M
Pr, M
NrThreshold voltage by the output voltage V of differential amplifier 102
DpAnd V
DnDrive.Multiple monotectic pipe M
Pr, M
nSource electrode by control node V
FnAnd V
FpRetroactive effect is on differential amplifier 102.Differential amplifier 102 and multiple monotectic pipe M
Pr, M
NrForm feedback control loop, and then can be by control node V
FnAnd V
FpAffect input voltage V
RefBe appreciated that loop feedback mechanism can be by control node V
FnAnd V
FpAffect input voltage V
Ref, and then act on the output V of differential voltage circuit 100
RefpAnd V
RefnOptionally, can pass through gain, direct current biasing and feedback factor in the regulation loop, and then by control node V
FnAnd V
FpGive input reference voltage V
RefProportional side-play amount is provided.Simultaneously, because transistor M is followed in the open loop source
p, M
nBe in the feedback control loop periphery, transistor M is followed in the open loop source
p, M
nCan transient response.
In the embodiment of the invention, optional, transistor M is followed in the open loop source
p, M
n, and multiple monotectic pipe M
Pr, M
NrSize (breadth length ratio) and bias current be complementary.Optionally, transistor M is followed in the open loop source
p, M
n, breadth length ratio N doubly to multiple monotectic pipe M
Pr, M
NrBreadth length ratio.Be appreciated that N is the integer greater than 0.
In the embodiment of the invention, voltage drop circuit 112 is electrically connected at supply voltage V
DdWith multiple monotectic pipe M
NrDrain electrode between; Voltage drop circuit 114 is electrically connected at supply voltage V
DdFollow transistor M with the open loop source
nDrain electrode between.By voltage drop circuit 112 and the 114 bias voltage V that produce
Adj, improved PSRR.In the embodiment of the invention, select bias voltage V
Adj, so that multiple monotectic pipe M
PrDrain-source voltage and multiple monotectic pipe M
pDrain-source voltage about equally, transistor M is followed in the open loop source
pDrain-source voltage and open loop source follow transistor M
pDrain-source voltage about equally.Optionally, V
AdjCan be used for determining the PSRR value of the maximum of differential voltage circuit 100, also can be used for other suitable PSRR values of definite differential voltage circuit 100.
Differential voltage schematic diagram as shown in Figure 2 is in the embodiment of the invention, by the V of amplifier input
CmEnd can provide the common mode reference voltage signal.Reference voltage can be in the output voltage V of differential voltage circuit 100
RefpAnd V
RefnBetween float.In the embodiment of the invention, common mode voltage V
CmCan be set to supply voltage V
DdHalf (V
DD/ 2).Optionally, according to user demand, common mode voltage V
CmCan be set to supply voltage V
Dd, perhaps by using a fixing reference voltage, for example use band gap reference voltage.
As shown in Figure 3, in the reference voltage generator 300 shown in another embodiment of the present invention, reference voltage generation module (VrefGen block) 302 is with band gap voltage V
BgAs input signal, and the reference voltage V of generation Single-end output
Ref, this reference voltage V
RefDifferential voltage output as maximum magnitude.In the embodiment of the invention, reference voltage generation module 302 can adopt the prior art means to realize, such as adopting ladder shaped resistance (resistorladder), reference voltage V
RefCan pass through common mode voltage V
CmBe converted to differential voltage.In the embodiment of the invention, common mode voltage V
CmCan be set to supply voltage V
Dd(V
DD) half (V
DD/ 2).Optionally, according to user demand, common mode voltage V
CmCan be set to supply voltage V
Dd, perhaps by using a fixing reference voltage, for example use band gap reference voltage.
In the embodiment of the invention, produce reference voltage by unity gain resistance feedback sign-changing amplifier 304.When followed transistor M by the source
1pAnd M
1nWhen being used for alleviating the high output impedance of trsanscondutance amplifier (Operational-transconductanceamplifier, OTA) 308 and then carrying out the unity gain resistance feedback, the OTA 308 of amplifier 304 inside is used for providing DC current gain.In the embodiment of the invention, OTA 308 is as the common-mode feedback pattern, and/or the fully-differential amplifier in the common mode output voltage control.Optionally, also can use non-unity gain resistance feedback.Further, OTA 308 also can replace with other amplifier topology structures, such as operational amplifier etc.
Differential voltage output V
RefpAnd V
RefnCan follow transistor M by the source in the output module 306
1pAnd M
1nFollow output in the source that consists of.Transistor M is followed in the source
1pAnd M
1nThe source of grid bias mirror image in loop follow transistor M
1psAnd M
1nsGrid bias.In the embodiment of the invention, transistor M is followed in the source in the output module 306
1pAnd M
1nThe source that decuples in the loop of size follow transistor M
1psAnd M
1nsSize.Optionally, transistor M is followed in the source in the output module 306
1pAnd M
1nThe size source that also can be several times as much as in the loop follow transistor M
1psAnd M
1nsSize.In the embodiment of the invention, follow transistor M by keeping the source in the outer output module 306 of loop
1pAnd M
1nAdjusting, the bandwidth of output reference voltage can be can't help the bandwidth that radio frequency source among the trsanscondutance amplifier OTA follows backfeed loop and be limited, and then can follow transistor M by the adjustment source
1pAnd M
1nSize and bias voltage, obtain to have the characteristic of wider bandwidth and than the output signal of low output impedance.Simultaneously, because transistor M is followed in the source
1pAnd M
1nThe source of grid bias mirror image in loop follow transistor M
1psAnd M
1nsGrid bias, resulting differential reference voltage signal level also can be maintained.
As shown in Figure 3, dc offset voltage Vadj can be followed by the source negative pole end introducing of (M1n) in the path, and then transistorized M among the NMOS (N channel metal-oxide-SIC (semiconductor integrated circuit))
1pAnd M
1nM1n drain-source voltage V
DsRoughly the same.For example, in the embodiment of the invention, V
Adj≈ V
RefOptionally, V
AdjCan be greater than or less than V
RefIn the embodiment of the invention, drain-source voltage V
DsSymmetry improved the PSRR performance of reference signal generator 300.Same dc offset voltage V
RefTransistor M is followed in the source that also is applicable to
1nsIn the circuit, and then improved the source and followed transistor to (M
1p, M
1n) and (M
1ps, M
1ns) the mirror image accuracy.Optionally, different dc offset voltages can be applicable to source electrode and follows transistor M
1nsIn.
As shown in Figure 4, another embodiment of the present invention has disclosed reference voltage generator 400.DC voltage V
AdjThat the resistance of following the negative output terminal in the transistor circuit by being connected to the source produces.For example be connected to transistor M
1nsOn resistance R and be connected to M
1nOn resistance R/10.In the present embodiment, can pass through formula V
Ref=I
1* R selects employed resistance.By M
2nOr M
2nsCascode stage (cascode stage) the series connection access resistance and the nmos device (M that consist of
1nOr M
1ns) in, to reduce M
1nOr M
1nsImpedance on drain node.
The embodiment of the invention also provides the low voltage operating pattern.It is right that all NMOS pipes use two sources to follow, for example, and M
1p, M
1n, M
1ps, M
1ns, M
2p, M
2n, M
2ps, M
2ns, all be to have than the depletion type NMOS of low threshold voltage pipe (native NMOS).For example threshold voltage is 0V.When present embodiment uses than the depletion type NMOS pipe of low threshold voltage, also can not need excitation voltage source.Optionally, in the embodiment of the invention, employed excitation voltage source can be used other special standards.The NMOS pipe can be used for other equipment and replaces in addition, for example, and P channel metal-oxide-SIC (semiconductor integrated circuit) (PMOS) or transistor (BJT).
As shown in Figure 5, at transistor M
1nAnd M
1nsDrain node on the virtual impedance that obtains can roughly be calculated as:
Wherein, R is the resistance value that is connected on the transistor, r
0Transistorized output impedance, g
mIt is transistorized mutual conductance coefficient.And then can be by changing cascode stage (cascode stage) gain g
mr
oRegulating resistance R.In the embodiment of the invention, by the high speed regulating frequency, low resistance R can reduce the peak value of the impedance of reference signal generator.For keeping the symmetry of forward outgoing route and negative sense outgoing route, can be with reference to figure 4, nmos device (M
2pAnd M
2ps) be placed in the forward outgoing route.In the embodiment of the invention, nmos device (M
2pAnd M
2ps) size and nmos device (M
2nAnd M
2ns) measure-alike.Optionally, use the nmos device (M of other sizes
2pAnd M
2ps) can ignore.
As shown in Figure 6, be cascode stage M in the embodiment of the invention
2nOr/and M
2nsGate bias voltage V
bProduce synoptic diagram.By selecting suitable R
OsAnd I
Os, M
2nOr/and M
2nsGate bias voltage can be set to:
V
b＝V
DD-V
ref＝V
DD-I
os×R
os
Wherein, V
DDSupply voltage, R
OsBiasing resistor, I
OsIt is bias current.
Shunt capacitance C among the figure
OsBe connected in M
2nOr/and M
2nsBetween grid and the ground end, by when the high frequency, provide to exchange the ground access, keeps a common gate connection.R
OsAnd I
OsForm a low-pass filter, to weaken M
2nAnd/or M
2nsThe current noise that produces of grid.For keeping positive and negative outgoing route symmetrical, as shown in Figure 4, M
2pAnd/or M
2ps, grid coupling identical R is set
OsAnd C
Os
Optionally, in the embodiment of the invention, V
DD=1.8V (volt), V
Ref=600mV, (millivolt) I
Os=20 μ A (microampere), and R
Os=30K Ohms (ohm), R=400Ohms (ohm), I
1=1.5mA (milliampere), the output stage electric current is: 10 * I
1=15mA.Shunt capacitance C
OsCan be set to 10pF (pico farad) so that M to be provided
2nAnd/or M
2nsThe interchange earth signal of grid.And then reference voltage generator can provide the reference voltage of the analog to digital converter ADC of 200Ms/s (sampling rate).Optionally, the embodiment of the invention is not limited to above-mentioned given particular value.
As shown in Figure 7, the embodiment of the invention provides a kind of analog to digital conversion circuit ADC system, and this system uses differential voltage generator 400 and then offers 702 1 reference signals of analog to digital conversion circuit.In the embodiment of the invention, analog to digital conversion circuit 702 can be a high speed, high-precision analog to digital conversion circuit.Optionally, difference reference voltage of the present invention provides circuit can be used for providing the difference reference voltage to use to the circuit of similar high speed, high-precision analog to digital conversion circuit.
In the embodiment of the invention, provide a kind of circuit, this circuit is used for producing the difference reference voltage at the first output terminal and the second output terminal, and this circuit comprises: first follows transistor and second follows transistor.
First follows transistor comprises: the first control node, first follow node and the first voltage source node with the first output terminal is electrically connected;
Second follows transistor comprises: the second control node, second follow node and second voltage source node with the second output terminal is electrically connected.
The first voltage drop circuit is electrically connected between circuit power node and the second source supply node.
The first voltage drop circuit biasing arranges, and then so that the voltage between circuit power node and the second voltage source node greater than the voltage between circuit power node and the first voltage source node; Also so that the voltage between circuit power node and the second voltage source node greater than circuit power node and the first control the voltage between the node.
In the embodiment of the invention, the first voltage drop circuit can also comprise: cascode transistors (also can be called serial transistor).Optionally, first follow transistor and second and follow the transistor acting in conjunction in open loop circuit.The first control node and the second control node can be setovered by a kind of multiple biasing circuit.Optionally, the first voltage drop circuit biasing arranges, and then so that the first voltage source node and first to follow voltage between the node and second voltage source node and the second voltage of following between the node roughly the same.Further, the biasing of the first voltage drop circuit arranges, and then so that has reduced in fact the signal energy of circuit power to reference voltage output.
The embodiment of the invention also provides a kind of circuit, and this circuit comprises: be electrically connected at the driving circuit between the first control node and the second control node.The present invention is among the embodiment, and driving circuit comprises: amplifier, this amplifier have first input end, the second input end, first amplifies output terminal and second and amplifies output terminal.First amplifies output terminal is electrically connected on the first control node; Second amplifies output terminal is electrically connected on the second control node.Optionally, this circuit comprises that also the 3rd follows transistor and the 4th and follow transistor.The 3rd follows transistor has and is electrically connected to the first the 3rd control node that amplifies output terminal, is electrically connected to the 3rd of first input end and follows node and tertiary voltage source node.The 4th follows transistor has and is connected to the second the 4th control node that amplifies output terminal, is electrically connected to the 4th of the second input end and follows node and the 4th voltage source node.
In the embodiment of the invention, this circuit also has second voltage and falls circuit, and this second voltage falls circuit and is used for being electrically connected between a reference voltage node and the 4th voltage source node.Further, this reference mode comprises aforesaid circuit power node.
In the embodiment of the invention, first follows transistor, second follows transistor, the 3rd and follows transistor and the 4th to follow transistor all be MOS (metal-oxide semiconductor (MOS)) transistor.Wherein, the first control node, the second control node, the 3rd control node and the 4th control node are the grid of MOS transistor; First follows node, second follows node, the 3rd and follows node and the 4th and follow the source electrode that node is MOS transistor; The first voltage source node, second voltage source node, tertiary voltage source node and the 4th voltage source node are the drain electrode of MOS transistor.Optionally, aforementioned circuit is integrated circuit.In conjunction with Fig. 1-Fig. 7, be appreciated that the first voltage source node, second voltage source node, tertiary voltage source node and the 4th voltage source node can be electrically connected on the circuit power node, so that electric current to be provided.Be appreciated that in above-described embodiment that the first voltage source node can be the M among Fig. 1
p, the second voltage source node can be the M among Fig. 1
n, the tertiary voltage source node can be the M among Fig. 1
Pr, the 4th voltage source node can be the M among Fig. 1
Nr
The embodiment of the invention also provides a kind of system and method for generation of reference voltage.Comprise and provide one to have the first forward outgoing route, the second forward outgoing route, the amplifier in the first feed back input path and the second feed back input path.First follows transistor and the 3rd follows transistorized control node and is electrically connected in the first forward outgoing route.Second follows transistor and the 4th follows transistorized control node and is electrically connected in the second forward outgoing route.First follows transistor and second follows the transistorized node of following and is electrically connected at respectively in the first feed back input path and the second feed back input path.The 3rd follows transistor and the 4th follows the transistorized output terminal that node is electrically connected at respectively the system of reference voltage of following, optionally, the output terminal of the system of reference voltage is respectively the first output terminal and second output terminal of differential signal, for generation of system's difference reference voltage.Biasing circuit is used for providing and is in first and follows transistor and the second bias voltage of following between the transistor voltage source node; And provide and be in the 3rd and follow transistor and the 4th and follow corresponding bias voltage between the transistor voltage source node.Be appreciated that, in the present embodiment first followed transistor and second and followed transistor and can follow transistor and the 4th corresponding to the 3rd described in the embodiment of front and follow transistor, and second in the present embodiment followed transistor and the 3rd and followed transistor and can follow transistor and second corresponding to first described in the embodiment of front and follow transistor.In the present embodiment first followed transistor and second and followed the restriction of " first " " second " such as transistor etc. and just be used for the different transistor of clear difference.
The embodiment of the invention also provides a kind of biasing circuit, comprises the first cascode transistors, the second cascode transistors, the 3rd cascode transistors and the 4th cascode transistors.This first cascode transistors is electrically connected on the voltage source node of the first follow circuit.This second cascode transistors is electrically connected on the voltage source node of the second follow circuit.The 3rd cascode transistors is electrically connected on the voltage source node of the 3rd follow circuit.The 4th cascode transistors is electrically connected on the voltage source node of the 4th follow circuit.In the embodiment of the invention, biasing circuit further comprises: be connected to the first resistance of the first cascode transistors voltage source node, the second resistance that is connected to the 3rd cascode transistors voltage source node, a RC (capacitance-resistance) low-pass filter, and be connected in the current source of the first cascode transistors control node.This biasing circuit further comprises: be connected in the current source that the second cascode transistors is controlled the 2nd RC (capacitance-resistance) low-pass filter, the 3rd RC (capacitance-resistance) low-pass filter of node, is connected in the 3rd cascode transistors control node, and be connected in the 4th RC (capacitance-resistance) low-pass filter of the 4th cascode transistors control node.
The amplifier that the embodiment of the invention provides comprises: differential transconductance OTA (differentialoperational transconductance amplifier), and resistance-feedback network.This differential transconductance is connected to the first forward outgoing route and the second forward outgoing route.This resistance-feedback network is electrically connected to the first feed back input path and the second feed back input path.
In the embodiment of the invention, first follows transistor, second follows transistor, the 3rd and follows transistor and the 4th to follow transistor all be MOS transistor.The first cascode transistors, the second cascode transistors, the 3rd cascode transistors and the 4th cascode transistors also all are MOS transistor.First follows transistor, second follows transistor, the 3rd and follows transistor, the 4th to follow the control node of transistor, the first cascode transistors, the second cascode transistors, the 3rd cascode transistors and the 4th cascode transistors be transistorized grid.First follows transistor, second follows transistor, the 3rd and follows transistor, the 4th to follow the node of following of transistor, the first cascode transistors, the second cascode transistors, the 3rd cascode transistors and the 4th cascode transistors be transistorized source electrode.First follows transistor, second follows transistor, the 3rd and follows transistor, the 4th to follow the voltage source node of transistor, the first cascode transistors, the second cascode transistors, the 3rd cascode transistors and the 4th cascode transistors be transistorized drain electrode.Optionally, first follow transistor, second and follow transistor, the 3rd and follow transistor and the 4th to follow transistor all be the MOS transistor of exhausting property.The first cascode transistors, the second cascode transistors, the 3rd cascode transistors and the 4th cascode transistors all are the MOS transistor of exhausting property.
The embodiment of the invention provide a kind of produce the difference reference voltage method, comprising: follow second of node and transistor seconds from first of the first transistor and follow driver output difference reference voltage between the node; This difference reference voltage is used for so that come from reference voltage that first of the first transistor follows node less than the second reference voltage of following node that comes from transistor seconds.The method further comprises: the reference voltage voltage drop that provides a kind of voltage source node that comes from transistor seconds to provide; Regulate this voltage drop so that the signal energy of transmitting the output from reference power source to the difference reference voltage is minimum.
In the embodiment of the invention, the first transistor, transistor seconds are MOS transistor.First follows node and second, and to follow node be transistorized source electrode, and the transistor seconds voltage source node is transistorized drain electrode.
In the embodiment of the invention, produce the difference reference voltage method also comprise: between the control node of the control node of the first transistor and transistor seconds, produce first a difference reference voltage.Optionally, this step further comprises: by amplifier, drive the control node of the first replica transistor and the control node of the second replica transistor and generate the first difference reference voltage; Provide the input end that feeds back at least one amplifier the node from following of the first replica transistor and the second replica transistor; In the circuit structure of an open loop, drive the first transistor and transistor seconds.
The beneficial effect of the embodiment of the invention comprises: the high PSRR value of acquisition and/or at the broadband low output impedance that the output reference voltage node obtains, and then reduced the error of difference reference signal generator.Be appreciated that by high PSRR value, reduced the error that power supply noise causes; By broadband low output impedance output characteristics, reduced the voltage peak burr that in switching process, produces, and then allowed the better scope of application of interlock circuit.
The beneficial effect of the embodiment of the invention further comprises: reference voltage generator provided by the invention is according to introducing the fixed reference potential circuit, band gap voltage generator for example, and then can export a FR difference reference voltage V
Re, and this reference voltage V
ReInsensitive to technique, voltage range and temperature coefficient.
One of ordinary skill in the art will appreciate that all or part of flow process that realizes in above-described embodiment method, to come the relevant hardware of instruction to finish by computer program, described program can be stored in the computer read/write memory medium, this program can comprise the flow process such as the embodiment of above-mentioned each side method when carrying out.Wherein, described storage medium can be magnetic disc, CD, read-only store-memory body (Read-Only Memory, ROM) or store-memory body (Random Access Memory, RAM) etc. at random.
The above only is several embodiments of the present invention, and those skilled in the art can carry out various changes or modification to the present invention and do not break away from the spirit and scope of the present invention according to application documents are disclosed.
Claims (9)
1. a reference signal generator is used for producing the difference reference voltage between its first output terminal and the second output terminal, it is characterized in that comprise: first follows transistor and second follows transistor;
First follows transistor comprises: the first control node, first follow node and the first voltage source node with the first output terminal is electrically connected;
Second follows transistor comprises: the second control node, second follow node and second voltage source node with the second output terminal is electrically connected;
The first voltage drop circuit is electrically connected between circuit power node and the second voltage source node;
The biasing of the first voltage drop circuit arranges, so that the voltage between circuit power node and the second voltage source node is greater than the voltage between circuit power node and the first voltage source node; Also so that the voltage between circuit power node and the second voltage source node greater than circuit power node and the first control the voltage between the node;
Be connected to the driving circuit of the first control node and the second control node, wherein, described driving circuit further comprises: amplifier, the 3rd is followed transistor and the 4th and is followed transistor;
Amplifier, this amplifier have first input end, the second input end, first amplifies output terminal and second and amplifies output terminal; Wherein, the first amplification output terminal is electrically connected on the first control node; Second amplifies output terminal is electrically connected on the second control node;
The 3rd follows transistor has and is electrically connected to the first the 3rd control node that amplifies output terminal, is electrically connected to the 3rd of first input end and follows node and tertiary voltage source node;
The 4th follows transistor has and is connected to the second the 4th control node that amplifies output terminal, is electrically connected to the 4th of the second input end and follows node and the 4th voltage source node.
2. reference signal generator according to claim 1 is characterized in that, described driving circuit further comprises: circuit falls in the second voltage that is connected in a reference power source node and the 4th voltage source node.
3. reference signal generator according to claim 2 is characterized in that, described reference power source node is the circuit power node.
4. reference signal generator according to claim 1 is characterized in that, first follows transistor, second follows transistor, the 3rd and follow transistor and the 4th to follow transistor all be MOS transistor; Wherein, the first control node, the second control node, the 3rd control node and the 4th control node are the grid of MOS transistor; First follows node, second follows node, the 3rd and follows node and the 4th and follow the source electrode that node is MOS transistor; The first voltage source node, second voltage source node, tertiary voltage source node and the 4th voltage source node are the drain electrode of MOS transistor.
5. reference signal generator according to claim 1 is characterized in that, described the first voltage drop circuit is cascode transistors.
6. reference signal generator according to claim 1 is characterized in that, described first follows transistor and described second follows the transistor acting in conjunction in open loop circuit.
7. reference signal generator according to claim 1 is characterized in that, by a replica bias circuit the first control node and the second control node is setovered.
8. reference signal generator according to claim 1, it is characterized in that it is roughly the same that the first voltage drop circuit biasing is arranged so that the first voltage source node and first is followed voltage between the node and second voltage source node and the second voltage of following between the node.
9. reference signal generator according to claim 1 is characterized in that, the biasing of the first voltage drop circuit is provided for reducing circuit power to the signal energy of reference voltage output.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17558409P | 2009-05-05 | 2009-05-05 | |
| US61175584 | 2009-05-05 | ||
| US12771944 | 2010-04-30 | ||
| US12/771,944 US8179194B2 (en) | 2009-05-05 | 2010-04-30 | System and method for a reference generator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101881984A CN101881984A (en) | 2010-11-10 |
| CN101881984B true CN101881984B (en) | 2013-04-24 |
Family
ID=43054016
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010168683 Active CN101881984B (en) | 2009-05-05 | 2010-05-05 | Reference signal generator and method and system thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101881984B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9201435B2 (en) | 2013-03-05 | 2015-12-01 | Infineon Technologies Ag | System and method for a power supply |
| US9746869B2 (en) * | 2013-12-05 | 2017-08-29 | Samsung Display Co., Ltd. | System and method for generating cascode current source bias voltage |
| CN106788434B (en) * | 2016-12-19 | 2020-03-17 | 电子科技大学 | Source follower buffer circuit |
| CN111367339B (en) * | 2018-12-26 | 2022-03-01 | 北京兆易创新科技股份有限公司 | Circuit for reducing threshold voltage of transistor, amplifier and NAND flash memory |
| CN110350876A (en) * | 2019-07-29 | 2019-10-18 | 深圳市锐能微科技有限公司 | Preamplifier, difference preamplifier and integrated circuit |
| CN113625812B (en) * | 2021-08-09 | 2022-08-30 | 珠海微度芯创科技有限责任公司 | Reference voltage circuit system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1524340A (en) * | 2001-05-25 | 2004-08-25 | �����ɷ� | High-bandwidth low-voltage gain cell and voltage follower having an enhanced transconductance |
| CN1585265A (en) * | 2003-07-30 | 2005-02-23 | 株式会社半导体能源研究所 | Circuit having source follower and semiconductor device having the circuit |
| US7019580B1 (en) * | 2003-11-11 | 2006-03-28 | Maxim Integrated Products, Inc. | NMOS composite device Vds bootstrappers |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6509727B2 (en) * | 2000-11-24 | 2003-01-21 | Texas Instruments Incorporated | Linear regulator enhancement technique |
| US7026824B2 (en) * | 2003-10-31 | 2006-04-11 | Faraday Technology Corp. | Voltage reference generator with negative feedback |
-
2010
- 2010-05-05 CN CN 201010168683 patent/CN101881984B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1524340A (en) * | 2001-05-25 | 2004-08-25 | �����ɷ� | High-bandwidth low-voltage gain cell and voltage follower having an enhanced transconductance |
| CN1585265A (en) * | 2003-07-30 | 2005-02-23 | 株式会社半导体能源研究所 | Circuit having source follower and semiconductor device having the circuit |
| US7019580B1 (en) * | 2003-11-11 | 2006-03-28 | Maxim Integrated Products, Inc. | NMOS composite device Vds bootstrappers |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101881984A (en) | 2010-11-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101881984B (en) | Reference signal generator and method and system thereof | |
| US6888482B1 (en) | Folding analog to digital converter capable of calibration and method thereof | |
| CN101562432B (en) | Variable gain amplifier | |
| CN110729995B (en) | Level conversion circuit and level conversion method | |
| KR100748462B1 (en) | Receiver circuit of semiconductor memory apparatus | |
| CN104007777B (en) | A kind of current source generator | |
| CN101630175A (en) | Matching current mirror | |
| TW200935752A (en) | Current steering DAC and voltage booster for current steering DAC | |
| CN101694963B (en) | High-precision low-voltage voltage/current switching circuit | |
| CN102541148B (en) | Two-way adjustable reference current generating device | |
| US8179194B2 (en) | System and method for a reference generator | |
| CN104102266A (en) | Reference voltage generating circuit | |
| US7821305B1 (en) | Dual voltage buffer with current reuse | |
| CN116488596A (en) | LVDS receiving circuit with wide input common mode range and chip | |
| CN106849938A (en) | A kind of input buffer circuit | |
| CN116107377A (en) | Circuit for generating bias voltage of passive self-mixer | |
| US7768324B1 (en) | Dual voltage buffer with current reuse | |
| US20180254750A1 (en) | Amplifier circuit | |
| CN203872141U (en) | Large-dynamic range variable gain amplifier | |
| CN207908576U (en) | Current sensor | |
| KR101939147B1 (en) | Variable Voltage Reference Generator and Analog-to-Digital Converter using thereof | |
| CN101382816A (en) | Constant current circuit | |
| CN104038171B (en) | Large dynamic range variable gain amplifier | |
| CN205507607U (en) | Double -purpose way electric current source generator | |
| CN116805859B (en) | Operational amplifier offset voltage regulation circuit and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |