CN105141303A - Slope control circuit - Google Patents
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- CN105141303A CN105141303A CN201510547023.9A CN201510547023A CN105141303A CN 105141303 A CN105141303 A CN 105141303A CN 201510547023 A CN201510547023 A CN 201510547023A CN 105141303 A CN105141303 A CN 105141303A
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Abstract
The invention discloses a slope control circuit. The slope control circuit is electrically coupled between a front-end replica circuit and a controller local network bus, wherein the front-end replica circuit is used for generating an upward feedback signal and a downward feedback signal; and the slope control circuit is used for receiving the two feedback signals in order to drive and control the voltage slopes of a high-voltage output level and a low-voltage output level of the controller local network bus. The slope control circuit comprises an upper-stage driving circuit and a lower-stage driving circuit, wherein the upper-stage driving circuit and the lower-stage driving circuit are connected between the front-end replica circuit and the high-voltage output level as well as between the front-end replica circuit and the low-voltage output level respectively, and comprise at least one first charging-discharging circuit and at least one second charging-discharging circuit respectively. The descending slope of the high-voltage output level is controlled through the charging-discharging states of the first charging-discharging circuit and the second charging-discharging circuit in order to be effectively symmetrical to the rising slope of the low-voltage output level. Meanwhile, the delay time of the whole circuit in switching among different modes can be kept equal.
Description
Technical field
The present invention relates to a kind of control circuit; Particularly can be widely used in the application systems such as CAN bus about one, and can carry out for the slope of output stage voltage level the circuit design that controls.
Background technology
Controller local area network (ControllerAreaNetwork, CAN) is in nineteen ninety for first formulated specification, and in 1993 through standardization (ISO11898-1), and be widely used on various vehicle and electronic installation.Generally speaking, controller local area network (CAN) comprises a serial bus, and it provides high safety grade and efficient real-time control, has had more debug standby and mechanism that priority differentiates, with under such mechanism, what the transmission of network message was become is more reliable and efficient.It seems with current development, existing controller local area network, not only have the elasticity adjustment capability of height, platform can be increased in existing network and not be used in operation software and hardware being done revise and adjust, in addition, the transmission of its information is not built on the platform of Special Category, further increases the convenience when upgrade of network.
Generally speaking, Fig. 1 discloses the Organization Chart of prior art one CAN bus, wherein, in controller local area network, such as there are two platforms, it is platform 101 and platform 103, jointly be connected to bus 300 via control transceiver (CAN-Transceiver) 200, and transmit differential (Differential) signal, to reach the transmission of control signal via a high voltage output level CANH and a low-voltage output level CANL.In existing Digital Logic, as shown in Figure 2, when high voltage output level CANH and low-voltage output level CANL is all 2.5 volts, the digital signal then exported is " 1 ", as for, if high voltage output level CANH rises to 3.5 volts, and when low-voltage output level CANL drops to 1.5 volts, then the digital signal exported is expressed as " 0 ".Wherein, the today of being finer division of labour, in order to reach the balance of dynamic control circuit, prior art is as U.S. Patent number US7,183,793 propose a kind of circuit framework then, it is utilize to control transistor operation when zone of saturation (Saturationregion), bias voltage is carried out with current source in its one end, and at the other end through manipulation type sensor amplifier (OperationalTransconductanceAmplifiers, OTA) produce circuit controls electric current, make the size of current on two current paths can reach consistent.Meanwhile, by the Current amplifier controlling current source and the slope reduced, control the symmetry of output stage high voltage output level and low-voltage output level voltage slope, reach the effect of slop control by this.
But, it should be noted that in order to such circuit design will be reached, no matter be at system end or chip design end, all must apply to a large amount of electric circuitry packages, and the complexity of circuit also promote with it significantly.In addition, prior art at the most only can be different from logical circuit connected mode set about go to evade, in the case, the design of integrated circuit is not only made to seem addition difficult, its component count that must expend and circuit cost also promote significantly, really considerably do not meet economy and cost benefit.
Be with, the present inventor improves thoughts on above-mentioned defect, and according to the correlation experience be engaged in for many years in this respect, concentrate one's attention on to observe and research, and coordinate the utilization of scientific principle, and a kind of modern design being proposed and effective the present invention improving above-mentioned defect, it discloses a kind of slope control circuit, and its concrete framework and execution mode will be specified in down.
Summary of the invention
For solving prior art Problems existing, an object of the present invention is to provide a kind of slope control circuit, a kind of circuit design innovated completely of its pioneering exposure, and designs by this precise hard_drawn tuhes reached output stage d. c. voltage signal.
Another object of the present invention is to provide a kind of slope control circuit, its resistance capacitance effect utilizing first charge-discharge circuit at least one road and the second charge-discharge circuit to generate, the charging and discharging state of control circuit, to complete the slop control to output stage voltage by this, and then reach the balance controlling dynamic slope, effectively to lower the direct current surging size of output stage.
Another object of the present invention is to provide a kind of slope control circuit, it is except can be applicable to CAN bus, more additionally can be connected with the self-feedback control circuit at least one road, can remain consistent with the time delay controlled when integrated circuit switches between different mode, with the advantage of control system being widely used in other industry.
Therefore, according to disclosed slope control circuit, it is electrically coupled between a front end duplicate circuit and a CAN bus, wherein, front end duplicate circuit produces on one feedback signal and once feedback signal, slope control circuit receives feedback signal and lower feedback signal on this, controls a high voltage output level of CAN bus and the voltage slope of a low-voltage output level with the driving via feedback signal on this and lower feedback signal.
According to embodiments of the invention, wherein, slope control circuit includes stage drive circuit on, and it is connected between front end duplicate circuit and high voltage output level, and comprise at least one first charge-discharge circuit, with the descending slope utilizing this first charge-discharge circuit to control high voltage output level; And once stage drive circuit, it is connected between front end duplicate circuit and low-voltage output level, and comprises at least one second charge-discharge circuit, with the rate of rise utilizing this second charge-discharge circuit to control low-voltage output level.By this circuit design, the present invention effectively can control the descending slope of the high voltage output level of output stage and the rate of rise of low-voltage output level, makes the two remain symmetrical.
On the other hand, the first charge-discharge circuit disclosed by the present invention more can comprise at least one first self-feedback control circuit, wherein, first self-feedback control circuit comprise one first time control switch with one first circuit for detecting being connected to this control switch first time, to utilize the first circuit for detecting generation one first feedback signal.Similarly, second charge-discharge circuit also can comprise at least one second self-feedback control circuit, wherein, the second self-feedback control circuit comprises a second time control switch and one second circuit for detecting being connected to this second time control switch, produces one second feedback signal to utilize the second circuit for detecting.Edge this, the present invention can utilize those signals to transmit in the mode of self-feedback and control to give first, second charge-discharge circuit in described, can maintain equal object to reach the time delay controlled further when main circuit switches between different mode.
In addition, front end duplicate circuit disclosed by the present invention, it more can be designed to a dual-loop architecture, to include on one feedback circuit and once feedback circuit, wherein, upper feedback circuit and lower feedback circuit are connected to the common-mode point in the duplicate circuit of front end jointly, and generation has described upper feedback signal and lower feedback signal separately, upper stage drive circuit and lower stage drive circuit is given, to reach extra effect controlling the direct voltage stable state of output stage high voltage output level and low-voltage output level by this for exporting respectively and driving.
Be with, by the ingehious design of slope control circuit disclosed by the present invention, pressure reduction between the high voltage output level of output stage and low-voltage output level successfully can be fixed as 2 volts by it, its abrupt voltage wave controls below 400 millivolts, and maintain the symmetry of output stage high-low voltage output level slope, realize the precise hard_drawn tuhes to dynamic DC level signal by this, reach goal of the invention of the present invention.
Under to coordinate by specific embodiment appended by graphicly to illustrate in detail, when the effect being easier to understand object of the present invention, technology contents, feature and reach.
Accompanying drawing explanation
Fig. 1 is the Organization Chart of prior art one CAN bus.
Fig. 2 is the oscillogram of the output stage voltage signal of prior art CAN bus.
Fig. 3 is the configuration diagram of the slope control circuit according to the embodiment of the present invention.
Fig. 4 is the internal circuit schematic diagram of the slope control circuit according to the embodiment of the present invention.
Fig. 5 is the internal circuit schematic diagram of the first charge-discharge circuit according to the embodiment of the present invention.
Fig. 6 is the internal circuit schematic diagram of the second charge-discharge circuit according to the embodiment of the present invention.
Fig. 7 is the waveform schematic diagram that the slope control circuit of the embodiment of the present invention is applied to a CAN bus.
Fig. 8 to Figure 10 discloses the schematic diagram of the self-feedback control circuit of one embodiment of the invention.
Figure 11 to Figure 13 discloses the schematic diagram of the self-feedback control circuit of another embodiment of the present invention.
Figure 14 is the waveform schematic diagram that the slope control circuit collocation self-feedback control circuit of one embodiment of the invention is applied to a CAN bus.
Figure 15 is the waveform schematic diagram that the slope control circuit collocation self-feedback control circuit of one embodiment of the invention is applied to the CAN bus of high-speed transfer.
16A figure and 16B figure are the internal circuit schematic diagram of the first circuit for detecting according to the embodiment of the present invention.
Figure 17 and Figure 18 is separately can in order to implement the internal circuit schematic diagram of the first circuit for detecting according to the embodiment of the present invention.
Figure 19 A and Figure 19 B is the internal circuit schematic diagram of the second circuit for detecting according to the embodiment of the present invention.
Figure 20 and Figure 21 is separately can in order to implement the internal circuit schematic diagram of the second circuit for detecting according to the embodiment of the present invention.
Description of reference numerals: 1-slope control circuit; 2-front end duplicate circuit; 3-CAN bus; 11-first charge-discharge circuit; 16a-detects amplifier; 16b-detects amplifier; 16c-detects amplifier; 16d-detects amplifier; 18-common factor logic lock; 21-second charge-discharge circuit; The upper feedback circuit of 22-; Feedback circuit under 24-; 26-common factor logic lock; 31-first self-feedback control circuit; 31 '-the first self-feedback control circuit; 32-second self-feedback control circuit; 32 '-the second self-feedback control circuit; 101-platform; The upper stage drive circuit of 102-; 103-platform; Stage drive circuit under 104-; 200-controls transceiver; 300-bus; 801-first circuit for detecting; 802-second circuit for detecting; P1, P2, N1, N2, M1, M2, M3, M4-transistor; S1, S2, S3, S4, S5, S6, U1, U2, U3, U4, U5, U6-transistor; Z1, Z2-diode; D1, D2, T1, T2, T3, V1, V2, V3, V4-passive component; R0, RL1, RL2, R1, R2, R3, R4-resistance; C1, C2, C3, C4-electric capacity; SWP1, SWN1, SWP2, SWN2-control switch; SWP3, SWN3, SWP4, SWN4-control switch.
Embodiment
More than have about description of contents of the present invention, with following execution mode in order to demonstrate and to explain spirit of the present invention and principle, and provide claim of the present invention further to explain.Feature for the present invention, implementation and effect, hereby coordinate and to be graphicly described in detail as follows do preferred embodiment.
Refer to shown in Fig. 3, it is the configuration diagram of the slope control circuit according to the embodiment of the present invention.As shown in Figure 3, disclosed slope control circuit 1 is electrically coupled between a front end duplicate circuit (Replicacircuit) 2 and a CAN bus (ControllerAreaNetworkBUS, CANBUS) 3.Wherein, CAN bus 3 is via an a high voltage output level CANH and low-voltage output level CANL to transmit differential (Differential) signal, and at high voltage output level CANH and an intermediary output level SPLIT and be serially connected with an output resistance R0 (or claiming terminal resistance) between intermediary output level SPLIT and low-voltage output level CANL separately.Generally speaking, the resistance of this output resistance R0 is such as chosen as 60 nurses difficult to understand, the personage only haveing the knack of technique field from can according to side circuit demand designed, designed, and be not used to limit invention scope of the present invention.
Fig. 4 discloses the detailed inner circuit diagram of one embodiment of the invention, Fig. 3 please be coordinate to consult in the lump, as shown in the figure, front end duplicate circuit 2 has a pair of loop structure, it to comprise on one feedback circuit 22 and once feedback circuit 24, wherein, upper feedback circuit 22 is connected to the common-mode point VCM in front end duplicate circuit 2 jointly with lower feedback circuit 24.For example, series resistor RL1 on the P type metal-oxide half field effect transistor P1 of series connection, P2, diode Z1 and can be included in upper feedback circuit 22; N-type metal-oxide half field effect transistor N1, the N2 of series connection, diode Z2 and once series resistor RL2 can be included in lower feedback circuit 24.Wherein, upper feedback circuit 22 and lower feedback circuit 24 can to have produced on one feedback signal VFBUP and once feedback signal VFBDN separately from common-mode point VCM, and feedback signal VFBUP on this and lower feedback signal VFBDN is exported give the first transistor M1 in slope control circuit 1 and third transistor M3 respectively, to control the DC voltage level (DClevelcontrol) of output stage high voltage output level CANH and low-voltage output level CANL by this, the only control device of this part and the emphasis of the real non-invention of technical characteristic, therefore do not repeat in this present invention.Technology emphasis of the present invention is be disclosed slope control circuit 1, it receives feedback signal VFBUP and lower feedback signal VFBDN on this, and via the driving driving of feedback signal VFBUP and lower feedback signal VFBDN (upper) of this binary signal, and reach the object of the control high voltage output level CANH of output stage and the voltage slope of low-voltage output level CANL.Below, first the present invention will carry out the following description for the circuit details of slope control circuit 1 and start thereof.
Specifically, according to Fig. 4, slope control circuit 1 to include on one stage drive circuit 102 and once stage drive circuit 104, wherein, upper stage drive circuit 102 is connected between the upper feedback circuit 22 of front end duplicate circuit 2 and high voltage output level CANH, further, upper stage drive circuit 102 includes a first transistor M1, at least one transistor seconds M2, one first passive component D1 and at least one first charge-discharge circuit 11.According to embodiments of the invention, described the first transistor M1, transistor seconds M2 and the first passive component D1 are sequentially serially connected with between an input power VDD and high voltage output level CANH, and, transistor seconds M2 is electrically connected at the first charge-discharge circuit 11, in addition, it should be noted that the magnitude setting of transistor seconds M2 fully should correspond to the magnitude setting of the first charge-discharge circuit 11.In other words, according to embodiments of the invention, if designer is for improving the withstand voltage holding capacity of circuit, then also can select to be serially connected with more than one transistor seconds M2 in circuit, only in the case, the magnitude setting of the first charge-discharge circuit 11 also should increase accordingly.Below, for ease of understanding technology of the present invention, the present invention is only provided with one group of transistor seconds M2 and first charge-discharge circuit 11 corresponding with it explanation Yunnan-Guizhou Plateau as a demonstration example in circuit, so have the knack of those skilled in the art scholar from a quantitative adjustment can be done according to the withstand voltage demand of side circuit, then also should be under the jurisdiction of invention category of the present invention.
Similarly, lower stage drive circuit 104 is connected between the lower feedback circuit 24 of front end duplicate circuit 2 and low-voltage output level CANL, further, lower stage drive circuit 104 includes a third transistor M3, at least one 4th transistor M4, one second passive component D2 and at least one second charge-discharge circuit 21.According to embodiments of the invention, described third transistor M3, the 4th transistor M4 and the second passive component D2 system are sequentially serially connected with between an earth terminal GND and low-voltage output level CANL, 4th transistor M4 is electrically connected at the second charge-discharge circuit 21, further, the magnitude setting of the 4th transistor M4 should correspond to the magnitude setting of the second charge-discharge circuit 21.Edge this, the present invention can utilize the charging and discharging state of control first charge-discharge circuit 11 to control the descending slope of high voltage output level CANH, utilize the charging and discharging state of control second charge-discharge circuit 21 to control the rate of rise of low-voltage output level CANL simultaneously, descending slope to reaching high voltage output level CANH successfully can be symmetrical in the rate of rise of low high voltage output level CANL, to realize goal of the invention of the present invention.
Continuing refers to shown in Fig. 5 and Fig. 6, and it discloses the internal circuit schematic diagram of the embodiment of the present invention first charge-discharge circuit 11 and the second charge-discharge circuit 21 respectively.As shown in the figure, the first charge-discharge circuit 11 includes control switch SWP1 on one first resistance R1, one first electric capacity C1, one first, one first time control switch SWN1, one second resistance R2 and one second electric capacity C2.Wherein, the first resistance R1 and the first electric capacity C1 is parallel with one another, and is jointly connected to input power VDD; On first, control switch SWP1 is series at this first resistance R1 and the first electric capacity C1; First time control switch SWN1 is series at control switch SWP1 on first, and on first time control switch SWN1 and first, control switch SWP1 system is connected between one first control inputs source HS_IN and one first output HS (i.e. the transistor seconds M2 of Fig. 4) jointly.After, the second resistance R2 connects first time control switch SWN1 and earth terminal GND; And the second electric capacity C2 connects earth terminal GND, and is parallel to the second resistance R2 simultaneously.
Similarly, as shown in Figure 6, then the second charge-discharge circuit 21 includes control switch SWP2 on one the 3rd resistance R3, one the 3rd electric capacity C3, one second, one second time control switch SWN2, one the 4th resistance R4 and the 4th electric capacity C4.Wherein, the 3rd resistance R3 and the 3rd electric capacity C3 is parallel with one another, and is jointly connected to input power VDD; On second, control switch SWP2 is series at the 3rd resistance R3 and the 3rd electric capacity C3; Second time control switch SWN2 is series at control switch SWP2 on second, and on second time control switch SWN2 and second, control switch SWP2 system is connected between one second control inputs source LS_IN and one second output LS (i.e. the 4th transistor M4 of Fig. 4) jointly.Afterwards, the 4th resistance R4 connects second time control switch SWN2 and earth terminal GND; And the 4th electric capacity C4 connects earth terminal GND, and is parallel to the 4th resistance R4 simultaneously.Specifically, according to one embodiment of the invention, as graphic in the present invention the 4th, 5, shown in 6 figure, the present invention adopts the first transistor M1 of stage drive circuit 102 and transistor seconds M2 to be P type metal-oxide half field effect transistor (Pmetaloxidesemiconductor, PMOS), the first passive component D1 is diode; Third transistor M3 and the 4th transistor M4 of lower stage drive circuit 104 are N-type metal-oxide half field effect transistor (Nmetaloxidesemiconductor, NMOS), and the second passive component D2 is diode; On first, control switch SWP1 is P type metal-oxide half field effect transistor (PMOS), and first time control switch SWN1 is N-type metal-oxide half field effect transistor (NMOS); And on second, control switch SWP2 is P type metal-oxide half field effect transistor (PMOS), and second time control switch SWN2 is N-type metal-oxide half field effect transistor (NMOS), as the explanation of one embodiment of the invention.
Be with, the first output HS designed by the present invention is via control switch SWP1 and first time control switch SWN1 on first, arrange in pairs or groups the first resistance R1 simultaneously, first electric capacity C1, the RC effect that second resistance R2 and the second electric capacity C2 produces controls the slope that it is charged to high voltage level or low voltage level, similarly, second output LS is also via control switch SWP2 and second time control switch SWN2 on second, arrange in pairs or groups the 3rd resistance R3 simultaneously, 3rd electric capacity C3, the RC effect that 4th resistance R4 and the 4th electric capacity C4 produces controls the slope that it is charged to high voltage level or low voltage level.Thus, through the slop control for the first output HS and the second output LS, then the present invention can successfully make output stage and the transistor seconds M2 of connection and the 4th transistor M4 open simultaneously or close, edge this, the object of the output surging size effectively reducing DC level can be reached.The slope control circuit that Fig. 7 discloses one embodiment of the invention is applied to the waveform schematic diagram of a CAN bus, as shown in Figure 7, then can obviously find out, utilize the technology disclosed by the present invention, direct current surging value P1, the P2 of high voltage output level CANH and low-voltage output level CANL can successfully control in 400 millivolts (mV) below by it.In addition, utilize the effect of first, second charge-discharge circuit of slope control circuit collocation shown in the 5 to 6 figure disclosed by the present invention, then the present invention more can control integrated circuit when switching alternately between aggressive mode (Dominantmode) and Passive Mode (Recessivemode), its high voltage output level CANH and low-voltage output level CANL respectively by common-mode pattern (Commonmode) rise to such as 3.5 volts with the voltage slope dropping to such as 1.5 volts, the two can be symmetrical.Be with, follow and take off accumulative evidence and data are known, slope control circuit disclosed by the present invention can perform effective control for the voltage level of output stage really, and can be widely used in the application systems such as CAN bus (CANBUS) or other industrial control systems, real for a kind of design good and can the slope control circuit design of effect brilliance.
On the other hand, for considering integrated circuit mutual time delay (timedelay) switched between aggressive mode and Passive Mode, the present invention more discloses a kind of mechanism of self-feedback control circuit, and it is as shown in graphic 8 to 13 figure.First, refer to shown in Fig. 8, it is that the first charge-discharge circuit 11 disclosed designed by the present invention more can connect at least one group of the first self-feedback control circuit 31, this the first self-feedback control circuit 31 is include a first time control switch SWP3 and one first circuit for detecting 801 being connected to this first time control switch SWP3, wherein, this first feedback signal HS_AFB in order to produce one first feedback signal HS_AFB, and transmits and controls to give first time control switch SWP3 by the output of the first circuit for detecting 801.In this embodiment, the first self-feedback control circuit 31 is be connected to control switch SWP1 on first, first time control switch SWN1, between the first control inputs source HS_IN, the first output HS and input power VDD.It is worth mentioning that, the setting of this first self-feedback control circuit 31 and link position are not limited with the enforcement aspect shown in Fig. 8, according to another embodiment of the present invention, as shown in Figure 9, then the first self-feedback control circuit 31 ' also can select control switch SWP1 in connection first, first time control switch SWN1, between the first control inputs source HS_IN, the first output HS and earth terminal GND.Now, this first feedback signal HS_AFB1 in order to produce the first feedback signal HS_AFB1, and transmits and controls to give first time control switch SWN3 by the output of the first circuit for detecting 801.Unlike, when the first self-feedback control circuit 31 is the first half (i.e. the input power VDD) being connected to circuit, then control switch SWP3 should be designed to a P type metal-oxide half field effect transistor for the first time, and the drain electrode system of this first time control switch SWP3 is connected to the contact (ginseng Fig. 8) of control switch SWP1 and first time control switch SWN1 on first.As for, when the first self-feedback control circuit 31 ' is connected to Lower Half (i.e. the earth terminal GND) of circuit, then control switch SWN3 should be designed to a N-type metal-oxide half field effect transistor this first time, and the drain electrode system of this first time control switch SWN3 is connected to the contact (ginseng Fig. 9) of control switch SWP1 and first time control switch SWN1 on first.
Similarly, consider the problem of the time delay that circuit switches between aggressive mode and Passive Mode, Figure 11 and Figure 12 system the second charge-discharge circuit 21 disclosed designed by the present invention more can connect the enforcement aspect of at least one group of the second self-feedback control circuit 32,32 '.Wherein, second self-feedback control circuit 32,32 ' comprises second time control switch SWN4, a SWP4 and is connected to one second circuit for detecting 802 of this second time control switch SWN4, SWP4, wherein, this the second feedback signal LS_AFB, LS_AFB1 in order to produce the second feedback signal LS_AFB, LS_AFB1, and transmit and control to give second time control switch SWN4, SWP4 by the output system of the second circuit for detecting 802.Embodiment as shown in figure 11, then the second self-feedback control circuit 32 can be connected to control switch SWP2 on second, second time control switch SWN2, between the second control inputs source LS_IN, the second output LS and earth terminal GND, now, it is a N-type metal-oxide half field effect transistor that second time control switch SWN4 system selects, and the drain electrode system of this second time control switch SWN4 is connected to the contact of control switch SWP2 and second time control switch SWN2 on second.As for, embodiment as shown in figure 12, then the second self-feedback control circuit 32 ' is be connected to control switch SWP2 on second, second time control switch SWN2, between the second control inputs source LS_IN, the second output LS and input power VDD, now, it is a P type metal-oxide half field effect transistor that second time control switch SWP4 should select, and the drain electrode system of this second time control switch SWP4 is connected to the contact of control switch SWP2 and second time control switch SWN2 on second.
Figure 14 system discloses the waveform schematic diagram being applied to a CAN bus according to embodiments of the invention, waveform schematic diagram as shown in Figure 14, can obviously find out, the architecture design of the slope control circuit collocation self-feedback control circuit of application disclosed by the present invention, when circuit enters Passive Mode by aggressive mode, for the second output LS, then can charge because of the gate of the electricity of the 3rd electric capacity C3 to the 4th transistor M4, make the unlatching that the lock source electrode pressure reduction of the 4th transistor M4 makes higher than Vtn fast, as shown in the S1 of region, similarly, first output HS also can control because of the impact of the second electric capacity C2 the gate electric discharge of transistor seconds M2, and then the unlatching that the lock source electrode pressure reduction of transistor seconds M2 is made higher than Vtp at once.After, as shown in the S2 of region, recycle the RC effect of aforementioned first charge-discharge circuit 11 and the second charge-discharge circuit 21, control the decline of high voltage output level CANH and low-voltage output level CANL and the rate of rise, then can issuable surging in effectively reduction process.
On the other hand, when circuit switches back aggressive mode by Passive Mode, see shown in the S3 of region, then on the second output LS and the first output HS respectively because first time control switch SWN3 or SWP3 can be unlocked instantaneously, and make the voltage on the second output LS drop to below VDD/2 soon, meanwhile, the voltage on the first output HS then rises to more than VDD/2 rapidly.After, first time control switch SWN3 or SWP3 closes by the effect recycling first, second circuit for detecting 801,802, and through the RC effect of aforementioned first charge-discharge circuit 11 and the second charge-discharge circuit 21, as shown in the S4 of region, control decline and the rate of rise of high voltage output level CANH and low-voltage output level CANL.So, the present invention not only can control the time that the 4th transistor M4 closes, this process can also be shortened widely, T1 time of delay making integrated circuit switch to Passive Mode by aggressive mode is equal with T2 time of delay that Passive Mode switches back aggressive mode, effective control lag time T1=T2.
Further, consider that the transmission rate of CAN bus is when the situation higher than 5Mb/s, then the embodiment of the present invention is applied to a schematic diagram when high-speed bus transmits, and it is refer to shown in Figure 10 and Figure 13.When this type of high-speed transfer, then the first charge-discharge circuit 11 is be connected with two group of first self-feedback control circuit 31,31 ' simultaneously, second charge-discharge circuit 11 is then connected with two group of second self-feedback control circuit 32,32 ' simultaneously, and its waveform schematic diagram being applied to high-speed bus transmission refers to shown in Figure 15.As shown in figure 15, the region S1 to S4 that wherein circuit switches between aggressive mode and Passive Mode is roughly as previously mentioned, therefore no longer repeats.Only what deserves to be explained is, due under high-speed transfer application, the time interval that circuit is in aggressive mode can shorten with comparing, and then the time delay had influence in RC effect, then as shown in the S5 of region, the voltage made on the first output HS and the second output LS sufficiently cannot be declined and rise to primary voltage level (i.e. FullLow and FullHigh).This problem will make the decline of high voltage output level CANH and low-voltage output level CANL and the rate of rise cannot be symmetrical, therefore in the case, then must utilize the first feedback signal HS_AFB1 that the first circuit for detecting 801 and the second circuit for detecting 802 produce, LS_AFB1 opens first time control switch SWN3 and second time control switch SWP4, then can realize the waveform as shown in the S6 of region, voltage on first output HS and the second output LS successfully can be declined and rise to primary voltage level (i.e. FullLow and FullHigh), and control lag time T1=T2, to implement goal of the invention of the present invention.
The continuous 16A figure that refers to is with shown in 16B figure, and it is the circuit details of the first circuit for detecting 801 be respectively according to graphic Fig. 8 and the Fig. 9 of the present invention.As shown in the figure, first circuit for detecting 801 is a common factor logic lock 18 that can comprise at least one detecting amplifier 16a, 16b and be series at this detecting amplifier 16a, 16b, with utilize the output of this common factor logic lock 18 produce described in the first feedback signal HS_AFB, HS_AFB1, and this first feedback signal HS_AFB, HS_AFB1 are transmitted and control first time control switch SWP3, SWN3 of giving in Fig. 8 and Fig. 9.Further, Figure 17 and Figure 18 system discloses two kinds respectively can in order to implement the enforcement aspect of the first circuit for detecting 801, as shown in figure 17, then detect amplifier 16a to be such as made up of multiple transistor S1 ~ S6 and passive component T1, T2, meanwhile, detecting amplifier 16b comprises passive component T3, but, also can select in circuit for detecting to be only provided with single detecting amplifier, namely detect amplifier 16a, and there is no detecting amplifier 16b (looking into the enforcement aspect shown in Figure 18).In other words, the aspect of just current practical application be it seems, as long as on the whole at least include a detecting amplifier in circuit for detecting, then in order to implement the present invention, and should be under the jurisdiction of invention scope of the present invention.
Similarly, refer to 19A figure with shown in 19B figure, it is the circuit details of the second circuit for detecting 802 be respectively according to graphic Figure 11 and the Figure 12 of the present invention.As shown in the figure, second circuit for detecting 802 can comprise at least one detecting amplifier 16c, 16d equally and be series at a common factor logic lock 26 of this detecting amplifier 16c, 16d, with utilize the output of this common factor logic lock 26 produce described in the second feedback signal LS_AFB, LS_AFB1, and this second feedback signal LS_AFB, LS_AFB1 are transmitted and control second time control switch SWN4, SWP4 of giving in Figure 11 and Figure 12.Further, Figure 20 and the 21st figure system disclose two kinds respectively can in order to implement the enforcement aspect of the second circuit for detecting 802, as shown in figure 20, then detect amplifier 16c to be such as made up of multiple transistor U1 ~ U6 and passive component V1, meanwhile, detect amplifier 16d and comprise passive component V2, V3.Or, as shown in the 21st figure, then detect amplifier 16d and also can select only to include a passive component V4, then equally can in order to implement the present invention.On the whole, above lifted embodiment is only that technological thought of the present invention and means used are described, its object understands content of the present invention implementing according to this enabling the personage of this area, when can not with restriction the scope of the claims of the present invention, the skill personage haveing the knack of this area, from change or the modification that can make an equalization according to disclosed embodiment, so must be encompassed in the scope of the claims of the present invention.
Be with, in sum, according to disclosed slope control circuit, it is for a kind of novelty and the circuit design of unconventionality, the control of its rate of rise and descending slope not only can be carried out for the output stage direct voltage of CAN bus, make the slope both this can be symmetrical, and when circuit being switched between aggressive mode and Passive Mode via Dynamic controlling alternately, its surging still can be controlled in specification limit (such as: 400 millivolts).In addition, the circuit design disclosed by the present invention, more can level off to equal by control circuit further, and extend to meet car rule demand with this framework the mutual time of delay switched between aggressive mode with Passive Mode.
Moreover the circuit design disclosed by the present invention, it more can utilize the mechanism of a self-feedback control circuit, can be effectively applied to the transmission level of high-speed bus, and maintains preferably circuit benefit simultaneously.See thus, compared to prior art, the present invention, not only with the low complex degree in circuit design, low cost and dynamical advantage, more can make integrated circuit have splendid Dynamic controlling effect, compared to known techniques, in fact there is splendid industry applications and competitiveness.
More than illustrate just illustrative for the purpose of the present invention, and nonrestrictive, and those of ordinary skill in the art understand; when not departing from the spirit and scope that following claims limit, many amendments can be made, change; or equivalence, but all will fall within the scope of protection of the present invention.
Claims (19)
1. a slope control circuit, be electrically coupled between a front end duplicate circuit and a CAN bus, this front end duplicate circuit produces on one feedback signal and once feedback signal, this slope control circuit system receives feedback signal and this lower feedback signal on this, a high voltage output level of this CAN bus and the voltage slope of a low-voltage output level is controlled with the driving via feedback signal on this and this lower feedback signal, it is characterized in that, this slope control circuit comprises:
Stage drive circuit on one, be connected between this front end duplicate circuit and this high voltage output level, wherein on this, stage drive circuit more comprises at least one first charge-discharge circuit, with the descending slope utilizing this first charge-discharge circuit to control this high voltage output level; And
Stage drive circuit once, be connected between this front end duplicate circuit and this low-voltage output level, wherein this lower stage drive circuit more comprises at least one second charge-discharge circuit, with the rate of rise utilizing this second charge-discharge circuit to control this low high voltage output level, the descending slope of this high voltage output level is made to be symmetrical in the rate of rise of this low high voltage output level.
2. slope control circuit according to claim 1, it is characterized in that, on this, stage drive circuit more comprises a first transistor, at least one transistor seconds and one first passive component, this the first transistor, this at least one transistor seconds and this first passive component are sequentially serially connected with between an input power and this high voltage output level, and this at least one transistor seconds connects this at least one first charge-discharge circuit.
3. slope control circuit according to claim 2, it is characterized in that, this lower stage drive circuit more comprises a third transistor, at least one 4th transistor and one second passive component, this third transistor, this at least one this second passive component of 4th transistor AND gate are sequentially serially connected with between an earth terminal and this low-voltage output level, and this at least one 4th transistor connects this at least one second charge-discharge circuit.
4. slope control circuit according to claim 3, is characterized in that, this first charge-discharge circuit more comprises:
One first resistance, connects this input power;
One first electric capacity, connects this input power, and is parallel to this first resistance;
Control switch on one first, connects this first resistance and this first electric capacity;
One first time control switch, is series at this control switch on first, and this first time control switch and this on first control switch system be jointly connected to one first control inputs source and this transistor seconds;
One second resistance, is connected between this first time control switch and this earth terminal; And
One second electric capacity, connects this earth terminal, and is parallel to this second resistance.
5. slope control circuit according to claim 4, is characterized in that, this second charge-discharge circuit more comprises:
One the 3rd resistance, connects this input power;
One the 3rd electric capacity, connects this input power, and is parallel to the 3rd resistance;
Control switch on one second, connects the 3rd resistance and the 3rd electric capacity;
One second time control switch, is series at this control switch on second, and this second time control switch and this on second control switch be jointly connected to one second control inputs source and the 4th transistor;
One the 4th resistance, is connected between this second time control switch and this earth terminal; And
One the 4th electric capacity, connects this earth terminal, and is parallel to the 4th resistance.
6. slope control circuit according to claim 3, is characterized in that, on this, this first transistor of stage drive circuit and this at least one transistor seconds are P type metal-oxide half field effect transistor, and this first passive component is diode.
7. slope control circuit according to claim 6, is characterized in that, this third transistor of this lower stage drive circuit and this at least one 4th transistor are N-type metal-oxide half field effect transistor, and this second passive component is diode.
8. slope control circuit according to claim 4, is characterized in that, this on first control switch be P type metal-oxide half field effect transistor, and this first time control switch is N-type metal-oxide half field effect transistor.
9. slope control circuit according to claim 5, is characterized in that, this on second control switch be P type metal-oxide half field effect transistor, and this second time control switch is N-type metal-oxide half field effect transistor.
10. slope control circuit according to claim 1, wherein the direct current surging value of this high voltage output level and this low-voltage output level can be controlled in below 400 millivolts.
11. slope control circuits according to claim 8, it is characterized in that, this first charge-discharge circuit more comprises at least one first self-feedback control circuit, this the first self-feedback control circuit comprise one first time control switch with one first circuit for detecting being connected to this control switch first time, wherein this first self-feedback control circuit is connected to this control switch on first, this first time control switch, between this first control inputs source and this transistor seconds, and this first self-feedback control circuit is optionally connected to this input power or this earth terminal.
12. slope control circuits according to claim 11, it is characterized in that, when this first self-feedback control circuit connects this input power, this, control switch was P type metal-oxide half field effect transistor first time, and this first time control switch drain electrode be connected to the contact of this control switch and this first time control switch on first.
13. slope control circuits according to claim 11, it is characterized in that, when this first self-feedback control circuit connects this earth terminal, this, control switch was N-type metal-oxide half field effect transistor first time, and this first time control switch drain electrode be connected to the contact of this control switch and this first time control switch on first.
14. slope control circuits according to claim 9, it is characterized in that, this second charge-discharge circuit more comprises at least one second self-feedback control circuit, this the second self-feedback control circuit comprises a second time control switch and one second circuit for detecting being connected to this second time control switch, wherein this second self-feedback control circuit is connected to this control switch on second, this second time control switch, between this second control inputs source and the 4th transistor, and this second self-feedback control circuit is optionally connected to this input power or this earth terminal.
15. slope control circuits according to claim 14, it is characterized in that, when this second self-feedback control circuit connects this input power, this second time control switch is P type metal-oxide half field effect transistor, and the drain electrode of this second time control switch is connected to the contact of this control switch and this second time control switch on second.
16. slope control circuits according to claim 14, it is characterized in that, when this second self-feedback control circuit connects this earth terminal, this second time control switch is N-type metal-oxide half field effect transistor, and the drain electrode of this second time control switch is connected to the contact of this control switch and this second time control switch on second.
17. slope control circuits according to claim 11, it is characterized in that, this first circuit for detecting more comprises at least one detecting amplifier and the common factor logic lock being series at this detecting amplifier, utilizing the output of this common factor logic lock to produce one first feedback signal, and this first feedback signal transmission is controlled to give this control switch first time.
18. slope control circuits according to claim 14, it is characterized in that, this second circuit for detecting more comprises at least one detecting amplifier and the common factor logic lock being series at this detecting amplifier, with utilize this common factor logic lock output produce one second feedback signal, and by this second feedback signal transmission and control give this second time control switch.
19. slope control circuits according to claim 3, it is characterized in that, this front end duplicate circuit to comprise on one feedback circuit and once feedback circuit, on this, feedback circuit and this lower feedback circuit are connected to a common-mode point of this front end duplicate circuit jointly, and produce separately feedback signal on this and export with this lower feedback signal confession and give this first transistor of stage drive circuit and this third transistor of this lower stage drive circuit on this, to control the DC voltage level of this high voltage output level and this low-voltage output level.
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| CN201510547023.9A CN105141303B (en) | 2015-08-31 | 2015-08-31 | Slope control circuit |
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| CN108604872A (en) * | 2016-02-08 | 2018-09-28 | 法国大陆汽车公司 | Device and method for the balanced load switching in H bridges |
| CN112834895A (en) * | 2019-11-24 | 2021-05-25 | 创意电子股份有限公司 | Test apparatus and test method |
| CN113037272A (en) * | 2020-12-07 | 2021-06-25 | 晶焱科技股份有限公司 | Bus driving device |
| CN116106600A (en) * | 2023-04-10 | 2023-05-12 | 上海灵动微电子股份有限公司 | System, circuit, method and equipment for controlling electric waveform on DUT (device under test) |
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| CN101527556A (en) * | 2008-03-07 | 2009-09-09 | 瑞昱半导体股份有限公司 | Output signal driving circuit and method for driving output signal |
| CN102177687A (en) * | 2008-10-09 | 2011-09-07 | Nxp股份有限公司 | Bus driver circuit |
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| CN108604872A (en) * | 2016-02-08 | 2018-09-28 | 法国大陆汽车公司 | Device and method for the balanced load switching in H bridges |
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| CN112834895A (en) * | 2019-11-24 | 2021-05-25 | 创意电子股份有限公司 | Test apparatus and test method |
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| CN113037272B (en) * | 2020-12-07 | 2023-09-26 | 晶焱科技股份有限公司 | Bus driving device |
| CN116106600A (en) * | 2023-04-10 | 2023-05-12 | 上海灵动微电子股份有限公司 | System, circuit, method and equipment for controlling electric waveform on DUT (device under test) |
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| CN105141303B (en) | 2018-08-03 |
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